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1 IoT FPGA 2016/12/1 IoT FPGA 200MHz 32 ASCII PCI Express FPGA OpenCL (Volvox) Volvox CPU 10 1 IoT (Internet of Things) [1] IoT IoT HTTP JSON ( Python Ruby) IoT IoT IoT (Hadoop [2] ) AI (Artificial Intelligence) FPGA (Field Programmable Gate Array) /3 FPGA [3] FPGA [4] OS FPGA GNU C Library (glibc) [5] FPGA OS CPU FPGA Intel ARM FPGA [6] ARM FPGA SoC (System on Chip) Zynq ARM CEO IoT ARM [8] kazuhiro.yamato@miraclelinux.com 1

2 PCI Express FPGA ( 1 ) 3 ( ( ) DMA ( ) 1: (Tokenizer kernel) OpenCL Volvox : FPGA FPGA ALPHA DATA ADM-PCIE-7V3 [11] FPGA Xilinx Virtex-7 XC7VX690T-2 8 DDR 8 GT/s 2 8GB ECC-SODIMM, 1333MT/s 2.2 (Tokenizer kernel) 2 L ( 4 ) C++ Vivado (HLS) C 2 2 MIRACLE LINUX Corporate color is green. ( ) num lines total length 1 lengths num lines lines \n 1 FPGA Linux 2

3 2: : I/O / num lines IN 32 scalar AXI slave (register) N/A total length IN 32 scalar AXI slave (register) N/A lines IN 8 array AXI master 32 lengths IN 16 array AXI master 16 markers OUT 32 array AXI master 8 positions OUT 16 array AXI master 16 markers num lines+1 positions positions markers N p = Z/B p (1) N p, Z B p positions markers positions N t N t = N p /2 (2) 3 W D AXI 3 / Reader lengths lines AXI / 1 Dispatcher lines Splitter Splitter 1 (8 ) W D /8 2 N s Splitter N s 1 Splitter Linearizer Splitter Unifier positions markers 4: L W D AXI N S 32 Splitters Q W p 64 positions

4 2: markers positions ( ) positions markers Positions formatter Marker formatter W D Q W p positions Writer markers positions Marker formatter markers L+1 5 AXI positions markers Q W p L+1 memcpy() for AXI (15) AWLEN Vivado HLS C/RTL co-simulation 5: AXI latency max read burst length lines 0 32 lengths 0 32 markers 0 default (16) positions 0 default (16) 200MHz FPGA ADM-PCIE-7V3 OpenCL Vivado HLS co-simulation N s 4

5 3: (Tokenizer kernel) 179 N s 2.3 OpenCL OpenCL The Khronos Group [10] CPU GPU FPGA C 1 API API OpenCL SDAccel OpenCL C pragma C C++ FPGA SDAccel C++ 4 OpenCL OpenCL Host application OpenCL framework on Host (API) FPGA RAM FPGA OpenCL C ( C/C++) PCI Express DDR RAM OpenCL 4: Volvox 2.4 Volvox Volvox FPGA 2 OpenCL API 5

6 SDAccel (β ) OpenCL Volvox OpenCL Volvox 5 FPGA DDR RAM Linux 5: Volvox FPGA 6 FPGA PCI Express LogiCORE IP 8 8GT/s PCI Express 256 AXI RDATA WDATA 250MHz AXI Bridge for PCI Express Gen3 AXI PCI Express AXI 1 ( ) PCI Express ( ) DMA 2 (1) Vivado HLS (2) AXI Bridge 6 FPGA (Splitter ) PCI Express 6

7 6: Volvox 6: LUT LUTRAM FF BRAM 20% 7% 11% 4% Volvox Linux 4MiB DMA 2 2 FPGA FPGA 2 Volvox mmap Linux streaming DMA API [12] DMA RAM FO a FV a (a) (b) (c) (d) FPGA L (c)(d) 7

8 C a CPU FO a FV a C (glibc) strtok() strtok v() FO s FV s (C s ) strtok v() (strtok()) 1 FPGA OS strtok v() FO s FV s positions markers FO a FV a char *strtok v(char *str) NULL str strtok strtok C s strtok() C a GNU C Library 7: FO a FV a C a FO s FV s C s strtok() FPGA FPGA CPU FPGA FPGA CPU OpenCL Volvox N/A OpenCL Volvox N/A : CPU Intel(R) Core(TM) i GHz RAM 8 GB 4 OS CentOS 6.8 (x86 64) Max payload size on PCIe 128 8

9 % 99% 9 13 ( L) 9: (Bytes) Frequency Word length 7: Frequency The number of consecutive separators 8: µs clock gettime(clock MONOTONIC) 2 [13] 50ns A T FO a C a FV a C a (T Ca ) A 10 3 FV a (T FVa ) A 10 4 C a T Ca /T FVa 1 FV s B/s 9

10 C a 4 FV a A µs A = 10 FV a 3 (1) DMA (2) DMA (3) µs (1) (3) (2) (3) 2.2 (C/RTL co-simulation) MHz 400 RAM 10 AXI FPGA ILA (Integrated Logic Analyzer) [14] ARVALID ( ) RVALID ( ) 100 lengths lines lengths lines FO a A < T 10 0 A = 10 FV a C a OpenCL (A > 10 8 ) FPGA with OpenCL CPU FPGA with Volvox 10-1 Process time (Sec.) Input data size (Bytes) 9: 90% strtok 11 1 C s FV s 7 10 (T Ca /T FVa ) clock gettime() 10

11 10: 10 AXI strtok v() NULL CPU CPU CPU CPU FPGA w/ OpenCL FPGA w/ Volvox 0 5x10 8 1x10 9 The count of calls per 1 second 11: strtok() strtok v() 4 IoT FPGA 200MHz 32 ASCII Volvox CPU 10 1 FPGA OS FPGA OpenCL SDAccel β OpenCL [1] Gartner s press release, Gartner says 6.4 Billion Connected Things Will Be in Use in 2016, Up 30 Percent From

12 [2] [3] Call-Deck.pdf [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] 12

1 osana@eee.u-ryukyu.ac.jp : FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T) LSI / PC clock accurate / Artix-7 XC7A100T Kintex-7 XC7K325T : CAD Hands-on: HDL (Verilog) CAD (Vivado HLx) : 28y4

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