A Study of Adaptive Array Implimentation for mobile comunication in cellular system GD133

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1 A Study of Adaptive Array Implimentation for mobile comunication in cellular system GD133

2 LSI DSP CMA 10km/s i

3 1 1 2 LS-CMA CMA LS-CMA ii

4 1 e ( 1.1 ) 1.1: 1

5 S/(N + I)( ) n x i (i =1, 2, n) w i (i =1, 2, n) ( 1.2) #1 #2 x w 2 2 x 1 w 1 Array Output #n x w n n Weight Vector Weight Estimator 1.2: 1) MMSE(Minimum Mean Square Error): 2 LMS (SMI) 2 (RLS ) 2

6 2) MSN(Maximum Signal-to-Noise ratio): SNR (S/(N + I)) (Jammer) 3) CMP(Constarained Minimization of Power): CMP DCMP( ) PI( ) 4) CMA(Constant Modulus Algorithm): ( ) MMSE CMA LSI DSP PHS [1] 3dB CMA 3

7 2 CMA 3 4 4

8 2 LS-CMA CMA CMA CMA FPGA 2.1 CMA CMA(Constant Modulus Algorithm) Treichler [2] CMA 1 CMA [3] CMA 2.1 MMSE MMSE 5

9 CMA 2.1: CMA CMA 2 (SD-CMA) 2 (LS-CMA) Marquardt Marquardt Gauss-Newton Marquardt LS-CMA Marquardt α =0 W SD-CMA W (m +1)=W (m) 4X(m)y (m)( y(m) 2 σ 2 ) LS-CMA W (m +1)=R 1 xx (m)r xd (m) n R xx (m) = X(i)X H (i) r xd (m) = δ(i) = i=0 n i=0 σ y(i) y(i) X(i)δ (i) y σ m ( ) n n 6

10 2.1.2 CMA IF A/D 8[GHz] 4 1 A/D IF 4 2.2: 2.1: Center Frequency 8.45[GHz] IF Modulation Bit rate 1 10[MHz] π/4shiftqpsk 2[Mbps] Number of element 4 Sampling Frequency Update Algorithm 4 40[MHz] LS-CMA,SD-CMA 7

11 : Power[dB] DOA[deg] Delay[µs] 1 st wave Desired nd wave Delayed rd wave CCI n= LS-CMA BER 2.5 1bit LS-CMA SD-CMA BER SD-CMA LS-CMA LS-CMA LS-CMA 8

12 Iteretion[time] Magnitude[dB] st wave 2 ndwave 3 rdwave Time 2.3: LS-CMA Magnitude[dB] st wave 2 ndwave 3 rdwave Time 2.4: SD-CMA 9

13 BER LS-CMA SD-CMA Eb/N[dB] 2.5: BER ( ) f D V λ f D = V/λ 100km/s 100km/s 8GHz 100km/s LS-CMA n

14 dB -41.3dB ( 2.6 ) n [µs] 8GHz 100km/s f D 2.6[MHz] IF 212[µs] λ/20 [4] 2.7 ( 200[µs]) n =5 10[sample] 1 1[MHz] n[µs] Iteretion[time] Magnitude[dB] Time 2.6: 11

15 Iteretion[time] nd 2 wave rd 3 wave < 200 s n 0 2.7: n Magnitude[dB] st wave nd 2 wave rd 3 wave Angle[degree] 2.8:

16 2.2 LS-CMA RF IF ADC 2.3: 8.45[GHz] 10[MHz] 2channnel,40MHz, 12bit resolution FPGA Altera epf10k200src240-3, eplk100qc208-3, epf6024aqc208-3 CPU Hitachi SH-4 200MHz (360MIPS,1.4GFLOPS) Interface OS 10base-T Ethernet(TCP/IP) NetBSD RF IF A/D FIFO FPGA CPU Ethernet 2.10 RF Input 8.45[GHz] IF Input 10[MHz] ADC 40MSPS FIFO FPGA Digital Down Convert I Q I Q CPU Rxx rxd Rxx rxd Input y=w*x Output weight caluculation PC TCP/IP 2.9: 13

17 2.10: A. ADC 8.45GHz RF 10MHz IF 3 IF ADC 4 40MHz IQ B. CMA CMA CPU CPU 200MHz FPU DSP C LS-CMA α 0 Omni (1,0) R xx C. PC OS NetBSD TCP IP Telnet PC 14

18 2.11: MHz 100kHz I/Q CMA ±30 549µs 8.45GHz 10km/s 15

19 Magnitude[dB] Angle[degree] 2.12: y Iteration 2.13: 2 16

20 2.2.3 LS-CMA A/D CPU TCP/IP PC 2 10km/s FPGA PC Pentium3-800MHz CPU 80µs 17

21 [5]

22 PS PS PS PS Rx PS:Phase Shifter 3.1: FET /( ) A/D D/A 19

23 PS PS Rx ADC w PS Rx ADC Rx Rx ADC ADC w w PS Rx ADC w D/A weight control weight control 3.2: n d 0.3λ -20dB r k (k =1,..., K) v k (k =1,..., K) [ v k (θ, φ, f) = exp j2π f ] [ c rt k L(θ, φ) = exp j 2π ] λ rt k L(θ, φ) L(θ, φ) = [sin θ cos φ, sin θ sin φ, cos θ] T 4 ( 3.4) 4 20

24 z x 0 φ θ rk L y 3.3: K d d y d z x 3.4: y 0 θ d v k (θ, φ, f) = exp [j2π f c d sin θ cos { φ 2π K (k 1)}] = exp [ j 2π λ d sin θ cos { φ 2π (k 1)}] K K =4 d =0.5λ θ = π/2 [ v k (φ) = exp jπcos {φ π }] 2 (k 1) (k =1, 2, 3, 4) 21

25 V (θ) =[v 1,v 2,v 3,v 4 ] T D p (θ) = 1 2 W optv H (θ) 2 W opt 3.5 ± : 4 / 3.5 sin y λ x y d d ( 3.7 ) 22

26 d d d y x 3.6: : / ± MMSE MMSE MSN CMA 23

27 RLS [ W opt = g V s P uv H ] u V s V u P n + KP u g = P s (P n + KP u ) P n (P n + KP s )(1 + P s V H s R 1 nn V s) P V s u n W opt V s V v P u W [ W opt = g V s P ] uv H u V s V P n + KP u = u a e jπθ 1 b e jπθ 2 c e jπθ 3 d e jπθ 4 W phase = e jπθ 1 e jπθ 2 e jπθ 3 e jπθ 4 a, b, c, d d = λ/2 exp( 3 2 jπ cos θ) exp( 1 V (θ) = 2 jπcos(θ π v 1 v 1 2 ) v 2 v 2 exp( 3 = = 2 jπ cos(θ π) v 3 v 1 exp( 1 2 jπcos(θ 3π 2 ) v 4 v2 24

28 0 Magnitude[dB] [degree] 3.8: 3,4 1,2 θ s θ u V (θ s ) V (θ u ) 3,4 1,2 a e jθ 1 exp(jθ 1 ) b e jθ 2 b W opt = = a exp(jθ 2) c e jθ 3 exp(jθ 1 ) d e jθ 4 b a exp(jθ 2) b/a 3.9 b/a=1 b/a 1 25

29 : b/a b/a 1 b/a 1 b/a Magnitude [db] Angle [degree] 3.10: 26

30 - 30dB -40dB ±5 ±5 ±5 D p (θ) D p (θ) = 1 W H V (θ) 2 W V (θ) W H V (θ) = 2 exp(jθ 1 ) b a exp(jθ 2) exp(jθ 1 ) b a exp(jθ 2) H exp( 3 2 jπ cos θ) exp( 1 2 jπ cos(θ π 2 ) exp( 3 2 jπ cos(θ π) exp( 1 2 jπ cos(θ 3π 2 ) [ ( )] = exp j 3 2 π cos θ θ 1 + a b exp [ j ( )] 1 2 π sin θ θ 2 = 1 2 [ ( )] + exp j 3 2 π cos θ θ 1 + a b exp [ j ( )] 1 2 π sin θ θ 2 { ( ) cos 3 2 π cos θ θ 1 + a b cos ( ) 1 } 2 π sin θ θ 2 b/a 1 θ u 3 2 πθ u θ π sin θ u θ 2 a b b/a > π/2 <θ 2 <π/2 θ 2 π/2 <θ 2 θ 2 < π/2 θ 2 b/a <

31 0 Magnitude[dB] Angle[degree] 3.11: [59,71]( ) b/a= [59,35]( ) 3.4 1/( ) 2 4 SNR 28

32 4 LS-CMA 20Mbps 10km/h 1/( )

33 M2 30

34 [1],,,,,,, PHS,,,B-5-74, Apr.1998 [2] J.R.Treichler and B.G.Agee A News Approach to Multipath Corection of Constant Modulus Signals,, IEEE Trans., Vol.ASSP-31,No.2, pp , Apr.1983 [3] T.Ohgane,T.Shimura,N.Matsuzawa,and H.Sasaoka An Implementation of a CMA Adaptive Array for High Speed GMSK Transmission in Mobile Communication, IEEE Trans,1993 [4] Masahiro Murase, Yoshikazu Tanaka, and Hiroyuki Arai Propagation and Anteenna Measurements Using Antenna Switching and Random Field Measurements IEEE Trans. Vehicular Tech., Vol.43, No.3, pp , Aug 1994 [5], 1996 [6] Adaptive Signal Processing with Array Anntena,

35 [1],, LS-CMA,, B-1-111, Mar, [2] Atsushi Suzuki, Shintaro Muramatsu, Koichi Ichige, Hiroyuki Arai A hardware implementation of LS-CMA adaptive array for high-speed mobile communication, PIMRC 2002, MPO2.6, Sep,2002. [1],,,, B-5-198, Mar, 2003.( ) 32

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untitled LMS FPGA 18 2 28 0244031 MMSE( Minimum Mean Square Error) MMSE LMS( Least Mean Square), RLS( Recursive Least Mean) ( ) LMS, N-LMS( Normalized - LMS) FPGA( Field Programmable Gate Array) FPGA, 2 FPGA N-LMS