MAX9471/2 DS.J

Transcription

1 ; Rev 0; 5/06 * * ± PART TEMP RANGE PIN- PACKAGE TOP VIEW X2 X1 FSO/SCL FS1/SDA PD FS TUNE 2 13 VDD 12 VDD 11 GND MAX9471 VDDA 3 AGND 4 GND 5 CLK1 TQFN (5mm x 5mm) GND I.C. CLK4 CLK3 CLK2 PKG CODE MAX9471ETP+** -40 C to +85 C 20 TQFN-EP* T M A X E U D + ** -40 C to +85 C 14 TSSOP U14-2 * ** + Maxim Integrated Products 1

2 ABSOLUTE MAXIMUM RATINGS to GND V to +4.0V A to AGND V to +4.0V AGND to GND V to +0.3V All Other Pins to GND V to + 0.3V Short-Circuit Duration (all LVCMOS outputs)...continuous ESD Protection (Human Body Model)...±2kV Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Continuous Power Dissipation (T A = +70 C) 20-Pin TQFN (derate 21.3mW/ C above +70 C) mW 14-Pin TSSOP (derate 9.1mW/ C above +70 C) mW Storage Temperature Range C to +150 C Maximum Junction Temperature C Operating Temperature Range C to +85 C Lead Temperature (soldering, 10s) C ( = A = +3.0V to +3.6V and T A = -40 C to +85 C. Typical values at = A = 3.3V, T A = +25 C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS INPUTS (PD, X1 as a reference INPUT CLK) Input High Level V IH1 2.0 V Input Low Level V IL V Input Current High Level I IH1 V IN = 20 µa Input Current Low Level I IL1 V IN = 0-20 µa THREE-LEVEL INPUTS (FS0, FS1, FS2, as FS2 = open) Input High Level V IH2 2.5 V Input Low Level V IL2 0.8 V Input Open Level V IO V Input Current I IL2, I IH2 V IL2 = 0 or V IH2 = µa SERIAL INTERFACE (SCL, SDA) (Note 2) Input High Level V IH 0.7 x V Input Low Level V IL 0.3 x V Input-Leakage Current I IH, I IL µa Low-Level Output V OL I SINK = 4mA 0.4 V Input Capacitance C I (Note 3) 8.4 pf CLOCK OUTPUTS (CLK_) Output High Level V OH I OH = -4mA Output Low Level V OL I OL = 4mA 0.4 V POWER SUPPLIES Digital Power-Supply Voltage V Analog Power-Supply Voltage A V Total Current for Digital and Analog Supplies I DC CLK1 at 125MHz and CLK2 at MHz; all outputs not loaded V 12 ma Total Power-Down Current I PD PD = low 60 µa 2

3 AC ELECTRICAL CHARACTERISTICS ( = A = +3.0V to +3.6V, T A = -40 C to +25 C. Typical values are at = A = 3.3V, T A = +25 C with f XTL = 27MHz, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUT CLOCKS (CLK1, CLK2) Minimum Frequency Range f OUT f IN = 5MHz to 50MHz 4 MHz Maximum Frequency Range f OUT f IN = 5MHz to 50MHz, C L < 5pF MHz Clock Rise Time t R 20% to 80% of, C L = 10p F, f OUT = MHz (Figure 5) Clock Fall Time t F 80% to 20% of, C L = 10p F, f OUT = MHz (Figure 5) 1.4 ns 1.2 ns Duty Cycle f OU T = M H z, C L = 10p F % Output Period Jitter J P MHz, C L = 10p F, f I N = 27M H z 125MHz, C L = 5p F, f I N = 27M H z 26.3 Soft Power-On Time T PO2 f OU T = M H z, f I N = 13M H z P D fr om l ow to hi g h, ( Fi g ur e 6) 33.6 RMSps 1 ms Hard Power-On Time t PO1 (Figure 6) 15 ms VCXO CLOCKS (CLK3, CLK4) Crystal Frequency f XTL 27 MHz Crystal Accuracy ±30 ppm Tuning Voltage Range V TUNE V VCXO Tuning Range V TUNE = 0 to 3V, C 1 = C 2 = 4.0p F ±150 ±200 ppm TUNE Input Impedance Z TUNE 95 kω Output CLK Accuracy V TUNE = 1.5V, C 1 = C 2 = 4.0p F ±50 ppm Output Duty Cycle C L = 10pF load, CLK % Output Period Jitter C L = 10pF 36 RMSps Output Rise Time t R 20% to 80% of (Figure 5), C L = 10p F 1.4 ns Output Fall Time t F 80% to 20% of (Figure 5), C L = 10p F 1.4 ns 3

4 SERIAL-INTERFACE TIMING CHARACTERISTICS ( = A = +3.3V, T A = -40 C to +85 C, unless otherwise noted.) (Note 1, Figure 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Serial Clock f SCL 400 khz Bus Free Time Between STOP and START Conditions Hold Time, Repeated START Condition Repeated START Condition Setup Time t BUF 1.3 µs t HD,STA 0.6 µs t SU,STA 0.6 µs STOP Condition Setup Time t SU,STO 0.6 µs Data Hold Time t HD,DAT (Note 4) ns Data Setup Time t SU,DAT 100 ns SCL Clock Low Period t LOW 1.3 µs SCL Clock High Period t HIGH 0.7 µs Rise Time of SDA and SCL, Receiving t R (Notes 3, 5) C b 300 ns Fall Time of SDA and SCL, Receiving t F (Notes 3, 5) C b 300 ns Fall Time of SDA, Transmitting t F,TX (Notes 3, 6) C b 250 ns Pulse Width of Spike Suppressed t SP (Notes 3, 7) 0 50 ns Capacitive Load for Each Bus Line C b (Note 3) 400 pf Note 1: All parameters are tested at T A = +25 C. Specifications over temperature are guaranteed by design. Note 2: No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level voltage. Note 3: Guaranteed by design. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the SCL signal) in order to bridge the undefined region of SCL s falling edge. Note 5: C b = total capacitance of one bus line in pf. t R and t F measured between 0.3( ) and 0.7( ). Note 6: Bus sink current is less than 6mA. C b is the total capacitance of one bus line in pf. t R and t F are measured between 0.3 x and 0.7 x. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. 4

5 ( = A = +3.3V, T A = +25 C, f XTL = 27MHz, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE f CLK1 = 125MHz f CLK2 = MHz TEMPERATURE ( C) MAX9471/2 toc01 RISE TIME (ns) RISE TIME vs. TEMPERATURE C L = 10pF f XTAL = 27MHz f CLK1 = 66MHz TEMPERATURE ( C) MAX9471/2 toc02 FALL TIME (ns) FALL TIME vs. TEMPERATURE C L = 10pF f XTAL = 27MHz f CLK1 = 66MHz TEMPERATURE ( C) MAX9471/2 toc JITTER vs. TEMPERATURE C L = 10pF f XTAL = 27MHz MAX9471/2 toc04 33MHz OUTPUT MAX9471/2 toc05 66MHz OUTPUT MAX9471/2 toc06 JITTER (ps) f CLK1 = 33MHz CLK1 1V/div CLK1 1V/div f CLK1 = 66MHz TEMPERATURE ( C) 10ns/div 10ns/div CLK1 1V/div 125MHz CLK OUTPUT MAX9471/2 toc07 DUTY CYCLE (%) DUTY CYCLE vs. TEMPERATURE C L = 10pF f XTAL = 27MHz f CLK1 = 33MHz MAX9471/2 toc08 VCXO ACCURACY (PPM) f IN = 27MHz f OUT = 45MHz VCXO TUNING RANGE vs. VCXO ACCURACY 6pF 5pF 4pF MAX9741/2 toc09 47 f CLK1 = 66MHz ns/div TEMPERATURE ( C) VCXO TUNING RANGE (V) 5

6 TUNE SERIAL INTERFACE 0.1μF 27MHz C V C 2 VDDA * X1 X2 FS0/SCL FS1/SDA FS2* AGND* GND VCXO MAX9471/ MAX9472 PLL1 PLL2 * CLK1 CLK2 CLK3 CLK4* +3.3V 0.1μF x 3 OTP *MAX9471 ONLY. MAX9471 MAX TUNE 2 A 3 AGND 4, 10, 11 6, 9, 11 GND 5 7 CLK CLK2 7 8 CLK3 8 CLK4 9 I.C. 12, 13, 16 4, FS PD X X1 19 FS0/SCL 20 FS1/SDA 2 SDA 3 SCL EP EP µ µ PD 6

7 ± PD PD ± ± ± PD µ VCXO OUTPUT FREQUENCY (MHz) ppm -200ppm 3V V TUNE FS2 Low or open High MODE Pin programmable I 2 C enabled 7

8 FS2 FS1 FS0 FREQUENCY (MHz) AUDIO FREQUENCIES Open Open Open Open Open Low Open Open High Open Low High Open Low Open Open Low Low Open High High Open High Open Open High Low Low Open High Low Open Open Low Open Low Low High High VIDEO FREQUENCIES Low Low Low Low Low High Low Low Open High X X Disable three-level pins and enable I 2 C A4 A3 A2 A1 FREQUENCY (MHz) AUDIO FREQUENCIES VIDEO FREQUENCIES SDA t SU, DAT t SU, STA t HD, STA t BUF t LOW t HD, DAT t SU, STO SCL t HIGH t HD, STA t R t F START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION 8

9 SDA SCL S START CONDITION P STOP CONDITION W W W MASTER-WRITE DATA STRUCTURE S SLAVE ADDRESS W A DATA A P MASTER-READ DATA STRUCTURE S SLAVE ADDRESS R A DATA A P MASTER TRANSFERS TO SLAVE SLAVE TRANSFERS TO MASTER A = ACK; A = 0: SUCCESSFUL, A = 1: UNSUCCESSFUL S = START CONDITION P = STOP CONDITION 9

10 t R t F CLK_ 20% 80% 80% 20% RISE AND FALL TIME MEASURES BETWEEN 20% AND 80% 2.2V t STOP PULSE AFTER WRITING STOP EDGE SDA CLK1 OR CLK2 t PO1 t FST CLK3 OR CLK4 t PO2 10

11 ± µ TOP VIEW X1 SDA SCL TUNE GND CLK MAX9472 TSSOP 14 X2 13 PD GND 10 CLK2 9 GND 8 CLK3 PROCESS: CMOS 11

12 japan.maxim-ic.com/packages QFN THIN.EPS 12

13 japan.maxim-ic.com/packages TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY G 1 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products, Inc. All rights reserved. is a registered trademark of Maxim Integrated Products, Inc. Springer