master.dvi

Transcription

1 ATLAS TGC

2 LHC CERN 2005 ATLAS LHC TGC Thin Gap Chamber ATLAS p T TGC φ TGC Slave Board 2.5 μs Star Switch Star Switch 20 Slave Board 80 m Local DAQ Master TGC Slave Board Star Switch HDL FPGA Slave Board ASIC ASIC HDL FPGA VDEC ASIC Star Switch Slave Board HDL 3 FPGA 30 MHz

3 5 8 ATLAS 9. Large Hadron Collider ATLAS B ATLAS ATLAS ATLAS ATLAS DAQ DAQ Detector Control System Central Trigger Processor MUCTPI TTC TGC TGC TGC TGC... 34

4 3.2 TGC TGC latency TGC ASD Board Patch Panel Slave Board High-p T Board Sector Logic TGC HDL HDL TGC TGC ATLAS Slave Board Slave Board Slave Board Star Switch Star Switch Star Switch Local Slave Link LS-Link Slave Board Star Switch LS-Link Star Switch Slave Board LS-Link LS-Link pt Slave Board ASIC Slave Board ASIC

5 Slave Board ASIC VDEC ASIC VDEC ASIC Star Switch HDL Star Switch Star Switch FPGA LS-Link A 02 A A.2 ATLAS B JTAG IEEE B. JTAG B.2 JTAG B.3 JTAG B.4 TGC JTAG C Slave Board C. Slave Board ASIC... C..... C C.2 Slave Board ASIC HDL... 3 D Xilinx FPGA 22 D. Xilinx FPGA D.2 Xilinx FPGA D.3 FPGA E pt3 28 E. pt E.2 pt E.3 VME CPLD

6 F Single Event Upset 43 F. Single Event Effect F.. Slave Board ASIC SEU F.2 FPGA G LVDS 46 H

7 ATLAS ATLAS ATLAS ATLAS R-z MDT Monitored Drift Tube TGC ATLAS DAQ ATLAS DAQ DCS Detector Control System Central Trigger Processor TTC TGC R-z TGC δr, δφ TGC TGC TGC TGC TGC Patch Panel PS-Pack Slave Board

8 3.4 Slave Board Slave Board High-p T Board ASIC High-p T Board High-p T Board High-p T Board ASIC Sector Logic Sector Logic Verilog-HDL TGC TGC TGC JTAG Slave Board Phase Adjust Star Switch Star Switch LS-Link pt pt pt Slave Board ASIC FPGA Slave Board ASIC FPGA Slave Board ASIC Design Analyzer Slave Board ASIC Foundation Slave Board ASIC VDEC Slave Board VDEC ASIC Star Switch Star Switch () (2)

9 5.7 FPGA FIFO FIFO FPGA Slave Board FPGA Slave Board LVDS LVDS TGC A A A A.4 ATLAS A.5 ATLAS Detector PBS B. JTAG B.2 JTAG B.3 JTAG TAP B.4 BSC B.5 JTAG C. Slave Board ASIC... 4 C.2 Slave Board ASIC... 5 D. FPGA D.2 CLB D.3 FPGA E. pt3 () E.2 pt3 (2) F. SEU Voting Logic G. LVDS G.2 LVDS point-to-point G.3 LVDS G.4 LVDS multidrop H. Slave Board

10 . LHC ATLAS TGC MeV TGC TGC LVL latency Slave Board TGC TGC TGC LDB TGC LS-Link Slave Board Star Switch LS-Link LS-Link Slave Board ASIC Slave Board ASIC B. TGC... 0 C. Slave Board ASIC... 2 C.2 Slave Board ASIC... 3 D. Xilinx FPGA D.2 FPGA E. pt G. LVDS DS90C G.2 LVDS DS90C

11 ATLAS. Large Hadron Collider LHC LHC Large Hadron Collider CERN 27 km LHC. High Luminosity Low Luminosity Energy at collision 7 TeV + 7 TeV Luminosity 0 34 cm 2 s cm 2 s 2 Current 0.56 A A Luminosity lifetime 0 h Bunch separation ns Bunch crossing rate MHz Circumference km. LHC LHC LEP 2002 LEP 4 ATLAS A Troidal LHC Apparatus CMS The Compact Muon Solenoid ALICE A Large Ion Collider Experiment B LHC-B 4 ATLAS B 22 m 44 m 7000 t Appendix A 9

12 .2 ATLAS ATLAS.2. H ATLAS..2.2 gluon-gluon m H W -W qq Hqq g g (a) t,b H H q q q W,Z H W,Z q (b) q q (c) H q q (d) W H q q g (e) t t H g g (f) t H t. (a) gluon-gluon (b) W -W Z-Z (c) q- q (d) W (e) (f) t t ATLAS m H 80 GeV TeV.3 m H m H t t W H H b b H b b m H < 2m W W t t H lνb b lνjjb bb b W t t p T WZ t tz Wb b t tb b 80 <m H < 25 GeV H γγ H γγ 00 <m H < 50 GeV q q γγ gḡ γγ irreducible jj jγ Z ee 0

13 (pp H+X) [pb] 0 2 σ s = 4 TeV gg H M t = 75 GeV 0 CTEQ4M 0 - qq _ HW qq Hqq gg,qq _ Hbb _ qq _ gg,qq _ M H [GeV] HZ Htt _.2 bb _ BR(H) WW ZZ τ + τ cc _ gg tt - γγ Zγ M H GeV.3

14 H W Z t t W S/N W H γγ 80 <m H < 40 GeV H ZZ 4l H ZZ 4l 20 GeV <m H < 2m Z.3 50 <m H < 80 GeV H WW H ZZ 4l m H = 70 GeV ZZ Zγ irreducible t t Zb b reducible η < 2.5 p T > 20 GeV 2 2 η < 2.5 p T > 7 GeV 2 4 m Z t t Zγ Zb b t t Zb b b b b H WW ( ) lνlν m H = 70 GeV H WW H ZZ 4l suppress H WW ( ) lνlν WW lνlν t t W 3 H ZZ 4l H ZZ 4l 80 <m H < 700 GeV ZZ 2 η 5 2

15 H ZZ ( ) llνν m H > 700 GeV H ZZ 4l TeV H ZZ ( ) llνν H WW lνjj H ZZ ( ) llνν Z 2 ET miss 400 <m H < 900 GeV E T miss qq qqh H H WW lνjj m H TeV higs-p T ET miss 2 W m H W -W fb ATLAS [7] ATLAS 80 GeV <m H < TeV 30 fb m H SUSY MSSM Minimal Supersymmetric extention of Standard Model 2 H ±, H, h, A 5 A CP odd H, h CP even m h <m H 5 2 tan β m A radiative correction h γγ h b b H ZZ 4l A ττ A μμ τ ν H/A t t, A Zh, H hh.2.3 SUSY ATLAS SYSY SUSY /2 q 0 q g /2 g 3

16 Signal significance 0 2 H γ γ tth (H bb) H ZZ (*) 4 l H WW (*) lνlν H ZZ llνν H WW lνjj Total significance 0 5 σ ATLAS L dt = 30 fb - (no K-factors) m H (GeV).4 ATLAS 30 fb χ ± i χ 0 i B L S R =( ) 3(B L)+2S R =+ SUSY R = R R SUSY SUSY R SUSY LSP = Lightest Supersymmetric Particle LSP χ 0 g 3/2 g LSP SUSY LSP LSP ET miss (a) + ET miss (b) 2 + jet + ET miss (c) 3 + ET miss 4

17 .2.4 B LHC b t b b 00 μb 0 33 cm 2 s b b e + e B Belle BaBar b CP CKM Cabbibo-Kobayashi-Maskawa Belle BaBar B S B S B S Δm S CKM B 0 d J/ψK S sin 2β Bd 0 ππ sin 2α B 0 s J/ψφ γ B 0 d D0 K 0 γ t t.3 ATLAS.3. ATLAS ATLAS ATLAS LHC 0 34 cm 2 s 2 ATLAS p T E miss T b-tagging LHC 25 ns η 3.5 ATLAS 44 m 22 m 7000 t.2m 5.3m 2T 3 η pseudo rapidity θ η = ln(tan(θ/2)) η 5

18 .5 ATLAS μm 300 μm SCT Semiconductor Tracker 4mm TRT Transition Radiation Tracker transition radiation.2 [5].3.3 ATLAS LAr 6

19 .6 ATLAS 7

20 System Position Layer σ (μm) Channels η coverage Pixels barrel Rφ =2, z = ±2.5 barrel 2 Rφ =2, z = ±.7 endcap 4 Rφ =2, z = Silicon Strips barrel 4 Rφ =6,z= ±.4 endcap 4 Rφ =6,z= TRT axial 70(per straw) ±0.7 radial 70(per straw) Towers in Sampling 3 = Trigger Tower 2X 0.7X 0 4.3X mm 470 mm x 36.8mmx4 =47.3mm 6X 0 Trigger Tower Square towers in Sampling 2 Double readout 37.5mm/8 = 4.69 mm Strip towers in Sampling Hadrons.7 r φ z.8 LAr.7 η < 3.2 presampler η H γγ H ZZ ( ) 4e 0%/ E[GeV] + % 40mrad/ E[GeV].8 WLS Wave Length Shift LAr 8

21 .5 < η < < η < ATLAS p T ATLAS φ 2 p T.9 R-z 4 MDT Monitored Drift Tube CSC Cathode Strip Chamber RPC Resistive Plate Chamber TGC Thin Gap Chamber MDT chambers Resistive plate chambers 2 m 0 Barrel toroid coil 8 Thin gap chambers 6 Radiation shield End-cap toroid Cathode strip chambers m 0.9 ATLAS R-z ATLAS MDT CSC RPC TGC MDT Monitored Drift Tube.0 30 mm 50 μm

22 Cross plate Multilayer In-plane alignment Longitudinal beam.0 MDT Monitored Drift Tube bar Ar-CH 4 -N 2 80 μm 500 ns CSC Cathode Strip Chamber MWPC 2.54 mm 5.08 mm 60 μm 25 ns 7ns CSC p T 6 p T MDT 500 ns MDT z φ MDT RPC TGC φ R-z 3 R z φ φ 20

23 TGC 2 RPC 3 RPC 2 RPC low p T MDT MDT MDT high p T M D T TGC M D T TGC 3 low p T Graphite layer +HV Pick-up strip.8 mm 50 μm wire.4 mm high p T m XX-LL0V0.6 mm G TGC.8 mm 2 RPC Resistive Plate Chamber RPC η < RPC mm 30.0 mm 39.5 mm.5 ns TGC Thin Gap Chamber TGC < η < 2.7 η < 2.4 TGC.2.8 mm 50 μm.4 mm 2.8 mm CO 2 -n pentan 55:45 20 khz/cm 2 25 ns 99% 2

24 2 ATLAS 2. ATLAS DAQ 2.. ATLAS 40 MHz Hz ATLAS.2 LHC ATLAS.2 p T e, μ, γ, τ, ET miss ET miss W Z B B ATLAS DAQ ATLAS LVL LVL2 2 EF Event Filter 3 LVL TGC, RPC granularity LA latency LA 2 μs LA 75 khz 00 khz DAQ LVL2 00 khz LA 22

25 Interaction rate ~ GHz Bunch crossing rate 40 MHz LEVEL TRIGGER < 75 (00) khz Regions of Interest CALO MUON TRACKING Pipeline memories Derandomizers Readout drivers (RODs) LEVEL 2 TRIGGER ~ khz EVENT FILTER ~ 00 Hz Event builder Readout buffers (ROBs) Full-event buffers and processor sub-farms Data recording 2. ATLAS DAQ ATLAS 3 LVL2 LVL High-p T RoI Region of Interest 0 ms LVL 2 khz LVL2 EF EF s 00 MB/s EF ATLAS MB EF 00 Hz 23

26 2..3 DAQ ATLAS 2.2 LA TTC latency 2 μs 500 ns 2.5 μs LVL ROD Readout Driver FIFO % LA 00 KHz 6% Level Buffer Derandomizer ROD RO Link ROB Detector TTC DAQ TTC Detector DCS 2.2 ATLAS DAQ ROD ROB ROB ATLAS ROD BCID ID LA LID ID ROD BCID, LID RO Link Readout Link ROB Readout Buffer 2. ATLAS [6] LVL2 ROB RoI LVL2 EF DAQ ROB ATLAS LVL2 EF ROB ROD 2..4 Detector Control System ATLAS DCS Detector Control System DCS 2 Derandomizer 2 24

27 Channels FE FE band- Detector count occupancy [%] width a [Gb/s] No. RODs Pixel SCT 9, 34, TRT 424, EM calorimeter 73, Hadron calorimeter 25, Muon trigger chambers 789, Muon precision chambers 43, Total b a assuming 75 khz LVL rate b additional ( 6) RODs will be used for LVL output data 2. ATLAS occupancy ROD Readout Driver ROD Gb/s LHC DCS 2.3 LMB Local Monitor Box LMB ADC DAC LMB CAN 3 CAN LMB CAN p T E T miss.2 B e/γ E T miss High-p T CTP Central Trigger Processor CTP LA TTC Timing, Trigger and Control TTC LA 3 Controller Area Network CAN 25

28 ATLAS Surface Control Room Operation Server USA5 Local Control System Local Area Network CAVERN LMB LMB T 50 m F Optional Fieldbus drivers Electronics Rack Expert workstations Fieldbus 00 m 500 kbits/s Detector element PLC Test HV Power supply Example of fieldbus nodes LMB Sensors P LMB 2.3 DCS Detector Control System USA5 USA5 80 m USA5 USA Central Trigger Processor CTP Central Trigger Processor 2.5 e/γ τ p T E T ET miss 26

29 Trigger Condition Symbol Rate[MHz] Single Muon, p T > 20 GeV MU20 4 Pair of Muon, p T > 6 GeV MU6 2 Single isolated EM cluster, E T > 30 GeV EM30I 22 Pair of isolated EM cluster, E T > 20 GeV EM20I 2 5 Single jet, E T > 290 GeV J Three jet, E T > 30 GeV J Four jet, E T > 90 GeV J Jet, E T > 00 GeV AND missing E T > 00 GeV J00 + XE Tau, E T > 60 GeV AND missing E T > 60 GeV T60 + XE60 Muon, E T > 0 GeV AND isolated EM cluster, E T > 5 GeV MU0 + EM5I 0.4 Other triggers 5 Total Trigger Condition Symbol Rate[MHz] Single Muon, p T > 6 GeV MU6 23 Single isolated EM cluster, E T > 20 GeV EM20I Pair of isolated EM cluster, E T > 5 GeV EM5I 2 2 Single jet, E T > 80 GeV J Three jet, E T > 75 GeV J Four jet, E T > 55 GeV J Jet, E T > 50 GeV AND missing E T > 50 GeV J50 + XE Tau, E T > 20 GeV AND missing E T > 30 GeV T20 + XE30 2 Other triggers 5 Total CTP 96 CTP TTC LA 8 LA 4 00 ns LA LA CTP CTP TTC DAQ 2 2 RoI 27

30 Calorimeter Trigger Muon Trigger Front-end Preprocessor Endcap Muon Trigger (TGC based) Barrel Muon Trigger (RPC based) Cluster Processor (electron/photon and hadron/tau triggers) Jet/Energy-sum Processor Muon Trigger / CTP Interface Central Trigger Processor TTC 2.4 CTP MUCTPI 2.6 RPC TGC p T MUCTPI Muon Trigger Interface to CTP CTP MUCTPI LVL2 DAQ LVL2 RoI TTC TTC Timing, Trigger and Control ATLAS TTC BC Clock MHz LHC LA Level Accept Signal CTP BCR Bunch Counter Reset s LHC ORBIT BCID ECR Event Counter Reset LID 28

31 2.5 Central Trigger Processor 29

32 RPC-detector TGC-detector FE electronics FE electronics hit pattern On detector Off detector DSL (RPC) 64 sectors Pt thresholds for max. 2 candidates per sector DSL (TGC) 44 sectors MUCTPI DAQ Information on hit strips DAQ Information on hit strips / wire groups LVL2 CTP DAQ ROI information Multiplicity for different transverse-momentum cuts Information on muon candidates and on multiplicities CHS0V0 2.6 MUCTPI RPC TGC CTP LVL2 DAQ TTC TTC ATLAS TGC 2.7 TTC TTC TTCvi VME TTCvi LHC 40 MHz BC Clock s ORBIT CTP LA VME TTC 25 ns A-channel B-channel 2 TTC TTCvi 30 nm TTCrx ASIC TTCrx BC Clock LA ECR BCR 30

33 Synchronisation Signals (global or sub-detector specific) Sub-detector Specific LA's Atlas LA LHC Orbit TTCvi VME Interface Electrical A and B channels LHC clock (BC) TTC crate Optical output :32 Tree Coupler :32 Tree Coupler TTCrx Electrical outputs: BC clock LA Synchronisation signals Commands 2.7 TTC TTCrx TTCrx LA A-channel LA B-channel TTCrx TTCrx 3

34 3 TGC 3. TGC 3.. TGC TGC ATLAS m 2 3. TGC R-z M 3 M2 M3 2 M2 M3 M, M2 I TGC TGC < η < < η < 2.4 η <.9 η >.9 R-z p T TGC 6 p T p T low-p T 6 GeV high-p T 20 GeV low-p T, high-p T 3 p T φ TGC TGC mm mm TGC 2 R 7 φ 2 6 R φ 4 mrad 8 mrad p T layer 2 layer 2 layer layer δr, δφ φ RPC 32

35 2000 DL-LL0V0 M2 M3 S L =.05 M pivot plane R (mm) 6000 I low P T end-cap = hi P T forward = S L = Z (mm) 3. TGC R-z M TGC M2 TGC M3 TGC I TGC S L MDT M, M2, M3 z δφ =0 R φ R φ p T δr, δφ TGC 3.3 layer δr, δφ 3 δr, δφ p T 2 33

36 TGC Doublet TGC Triplet δr δφ layer 2 R φ Z layer Readout Segments Readout Segments 3.2 TGC Interaction Point 3.3 δr, δφ TGC δr, δφ p T TGC TGC 44 TGC 2 MUCTPI 6 p T TGC r OR φ 3 TGC 3..2 TGC low-p T high-p T low-p T 6 GeV high-p T 20 GeV low-p T low-p T 2 low-p T 4 3 high-p T low-p T hi-p T low-p T

37 η =.0 Δφ = Sub-sector 4 Trigger Sector.5 37 Sub-sector = 37 x 4 = 48 m Sub-sector = 6 x 4 = TGC TGC TGC 90 % high-p T low-p T R 6 cm TGC 7mm mm 2 mm 5 < = δr < < = δr < = 20 5 < = δφ < = 5 TGC 3.5 low-p T high-p T p T 3. TGC [3] LA ATLAS 75 m 35

38 Efficiency 0 - a) Low-p T System Efficiency 0 - b) High-p T System 0-2 p T Threshold 6GeV 0-2 p T Threshold 0GeV 8GeV 5GeV 0-3 0GeV 2GeV GeV 35GeV p T (GeV) p T (GeV) YH9V TGC (a) low-p T (b) high-p T p T Low p T muons ( 6 GeV ) High p T muons ( 20 GeV ) Process in low luminosity in high luminosity π/k decays b c W Total TGC khz low-p T 200 Hz high-p T 0 Hz low-p T high-p T 250 Hz 6 Hz TGC TGC 2 MeV TGC 4.5 Hz/cm 2 TGC 2 2 TGC 2 MeV 3. Hz/cm 2 36

39 TGC 3 TGC 3 00 MeV 3.0 Hz/cm 2 TGC 2 2 TGC 3 00 MeV low-p T high-p T CSC 3.2 [7] low-p T 6 GeV rates [khz] high-p T 20 GeV rates [khz] TDR scheme Three station logic coincidence with EI/FI MeV TDR low-p T Three station low-p T EI/FI 3.2 TGC 3.2. TGC 3.6 TGC TGC ASD Amplifier Shaper Discriminator Board Patch Panel Patch Panel LHC LHC LHC Slave Board Slave Board Slave Board High-p T Board Slave Board δr δφ High-p T Board Slave Board High-p T Board R, δr φ, δφ Sector Logic R-φ R, δr, φ, δφ 6 p T Sector Logic p T 2 MUCTPI OR 37

40 wire pivot doublet ASD ASD Patch Panel 32 BID, OR 32 BID, OR Wire Doublet Slave Board 3 / 4 Coin. Matrix 8 Wire High-Pt Board inner doublet ASD ASD BID, OR BID, OR LB Derand R, δr R H-Pt L H Selector CTP triplet ASD ASD BID, OR BID, OR Wire Triplet Slave Board 2 / 3 Coincidence 8 H-Pt L H Selector 20 Sector Logic (Endcap) ASD 32 BID, OR LB Derand R- ϕ Coin. Hits Selector strip pivot doublet ASD ASD Patch Panel 32 BID, OR 32 BID, OR Strip Doublet Slave Board 3 / 4 Coin. Matrix 6 Strip High-Pt Board 8 20 MUCTPI inner doublet ASD ASD BID, OR BID, OR LB Derand ϕ, δϕ ϕ H-Pt L H Selector Sector Logic (Forward) R- ϕ Coin. Hits Selector triplet ASD ASD BID, OR BID, OR Strip Triplet Slave Board OR 20 H-Pt L H Selector 8 LB Derand SOS00V TGC High-p T TGC 3.7 Slave Board 32 2 High-p T Board High-p T Board 6 Slave Board Slave Board Board 4 Sector Logic R-φ 2 MUCTPI Slave Board Slave Board Star Switch USA5 Local DAQ Master Readout Driver TGC 320 k ASD Board Patch Panel Slave Board High-p T Board ASIC 200 Sector Logic Star Switch FPGA 38

41 2 Doublets Wire Doublet Slave Board 3 / 4 coin. 2 tracks / board ( track / 6-ch ) Triplet Slave Board 2 / 3 coin. High-Pt Board 2 coin. 4 tracks / board ( trk / 48-pvt-ch ) Triplet Wire 3 hits / board ( hit / -ch ) R. ϕ Coincidence Hit Selector Doublet Slave Board 3 / 4 coin. 2 tracks pivot TGC 2 tracks sector MUCTPI 2 Doublets Strip Triplet Strip 2 tracks / board ( track / 6-ch ) Triplet Slave Board OR 4 hits / board ( hit / 8-ch ) High-Pt Board 2 coin. 2 tracks / pivot TGC End: trk / 48-pvt-ch ( Fwd: trk / 6-pvt-ch) SOS09V TGC Item Number Details Channel 32,824 Wire: 220,448 Strip: 0,376 ASD Chip 80,928 ASD Board 20,784 Patch Panel,600 Wire:,056 Strip: 480 Inner: 64 Slave Board 2,880 Wire: 2,06 Strip: 768 Inner: 96 High-p T Board 480 Wire: 288 Strip: 92 Sector Logic 44 Star Switch 208 Local DAQ Master 208 Readout Driver TGC TGC USA5 TGC 3.8 ASD Patch Panel Slave Board High-p T Board Star Switch Sector Logic USA5 Slave Board High-p T Board m Star Switch 9m 39

42 MUCTPI TGC electronics location Sector Logic (r-φ coin / hit-selection) High-Pt / Low-Pt trigger outputs ROB Star-switch outputs High-Pt Star-SW TGC M2 M3 ROD Local DAQ Master Local DAQ Master in USA5 EI Star-switch outputs Star-SW Slave Board Slave Board (2-out-of-3) Patch-panel (BID, "OR") TGC M Slave Board Low-Pt (3-out-of-4) Patch-panel (BID, "OR") Patch-panel (BID, "OR") TGC EI in UXA5 MDT EI MDT EM HIW00V TGC ASD High-p T Board USA5 80 m latency latency ATLAS latency p-p LA ATLAS latency 2.5 μs 0.5 μs 2.0 μs latency TOF USA5 80 m 0.5 μs USA5 LA 2.0 μs latency.5 μs 46 TGC.5 μs MUCTPI latency

43 Module/Transmission Latency Total TOF to TGC 3 3 TGC response 4 ASD Board 5 Cable to Patch Panel 6 Patch Panel 2 8 Cable to Slave Board 9 Slave Board 4 3 Cable to High-p T Board 3 6 High-p T Board 5 2 Cable to Sector Logic (80 m) 6 37 Sector Logic 8 45 Cable to MUCTPI (5 m) TGC LVL latency 3.3 TGC 3.3. ASD Board ASD Amplifier Shaper Discriminator Board TGC 4 ASD 4 6 TGC TGC ASD LVDS Patch Panel threshold V th Patch Panel Patch Panel ASD Board Patch Panel Patch Panel ASD Board Slave Board Patch Panel 3.9 Patch Panel ASIC Patch Panel ASD Board LVDS 40 MHz LHC BCID OR Slave Board R OR OR ASD Board ±3 V threshold V th 5 Slave Board 3.3 V LHC LA, BCR, ECR TTC OR Slave Board Patch Panel TGC η = const. 5 threshold Patch Panel ASIC Service Patch Panel LMB

44 Slave Board Patch Panel 9 Patch Panel LVDS Patch Panel 40 MHz BCID OR Logic 6ch ASD Board 20 twisted pair cable Mask + 3 V analog power GND (analog) Test strobe TTC signals (LHC clock LA, BCR, ECR) Other control Slave Board (covers 32ch for each TGC layer) analog output Vth +3.3 V digital power Temp. sensor Test pulse GND (digital) DCS KAY002V Patch Panel Patch Panel Slave Board 3.0 PS-Pack Patch Panel 2 Slave Board PS-Pack Service Patch Panel TTC TTCrx DCS LMB Slave Board Slave Board Patch Panel 3.6 Slave Board 3. Slave Board Slave Board Slave Board ASIC 5 ASIC Slave Board 3. Slave Board Slave Board Patch Panel Slave Board Phase Adjust 42

45 Service Patch-Panel TTC DCS DCS signals TTC signals PS-pack TGC signals from ASD Patch-Panel Slave Board Slave Board Slave Board Patch-Panel ~ 50cm Slave Board Slave Board Patch-Panel pivot TGC (octant) PS-pack 3.0 PS-Pack PS-Pack Patch Panel 2 Slave Board PS-Pack Service Patch Panel TTC DCS Type Input[/layer] Layer Input Output Coincidence Doublet Wire /4 Triplet Wire /3 Doublet Strip /3 Triplet Strip /2 EI/FI /2 3.5 Slave Board 5 Slave Board ASIC Patch Panel Patch Panel Slave Board Patch Panel φ A B 7 < = δr < = 7 43

46 Slow read-out middle doublet 2x x6 Phase adjust Phase adjust Phase adjust Phase adjust ECR BCR FE_BCID COUNTER FE_LID COUNTER L buffer Derandomizer LS-Link Clock Snap shot Mask Clock LA pivot doublet 2x Phase adjust Phase adjust Phase adjust Mask 3-out-of-4 Coin. Matrix 2x2 Phase adjust Position + δ R 8-bit SOS04V08 Clock Snap shot Slow read-out 3. Slave Board 2 p T δr 5 R 4 δr 8 High-p T Board Slave Board δr < = ±5 δr δφ < = ±3 δφ Slave Board 8 6 Slave Board Slave Board Slave Board Slave Board High-p T Board Slave Board Slave Board Slave Board OR Slave Board Slave Board High-p T Board 40 44

47 from adjacent doublet 6x2 inputs from TGC from adjacent doublet 6x2 inputs from TGC from adjacent doublet(pivot) 2x2 inputs from TGC 2nd 2 layers of doublet 32x2 inputs from TGC a st 2 layers(pivot) of doublet 32x2 inputs from TGC from adjacent doublet(pivot) 2x2 inputs from TGC A A B B C C B D 72x88 3-out-of-4 Coincidence Matrix D d (5-bit) δr from Low-Pt Matrix 72 inputs from LowPt Matrix 72 inputs from Low-Pt Matrix declustering, encode, highest Pt hit Only highest-pt hits in A and in B are encoded 8-bit encoded (wire) position 5-bit δr 4-bit ( ) x 2 position 5-bit δr 4-bit A: B: SOS042V δr 2x2 (middle doublet) inputs 4x2 (pivot doublet) inputs OR ed Y 8 outputs to encoder section a b c C D AB C C = a & b & c + a & b & c Y X = Y = A & C + A & D + B & D X δr OR ed X SOS043V out-of 4 45

48 3x Phase adjust Phase adjust Phase adjust Slow read-out ECR BCR FE_BCID COUNTER FE_LID COUNTER L buffer Derandomizer LS-Link 32 Phase adjust 3x2 Phase adjust Clock Snap shot Mask Clock LA 2-out-of-3 Coincidence 2-out-of-3 8-bit SOS05V Slave Board C0 B A C A2 B2 C2 36x3 (triplet) inputs out out = A & B2& C0& C2 + C & A & B + C & B2 & A2 00 declustering and encoder hit / 32 inputs hit position hit position hit position 8 bits (3 hits) / Triplet Slave Board SOS052V out-of 3 46

49 Clock Snap shot Slow read-out ECR BCR FE_BCID COUNTER FE_LID COUNTER Phase adjust Phase adjust Derandomizer LS-Link Slow read-out L buffer 32 Phase adjust 32 Phase adjust Clock Snap shot Mask Mask Clock LA OR OR SOS054V07 2x20 = 40-bit 3.6 Slave Board strip (triplet) 32x2 (triplet) inputs (no neighbor input) 64 declustering and encoder hit / 6 inputs abc d hit position hit position hit position hit position out out = b & c + b & a & c + a & c & b + c & b & d + b & d & c 20 bits (4 hits) / Triplet Slave Board SOS053V OR 47

50 3.3.4 High-p T Board High-p T Board High-p T Board 2 High-p T Board ASIC 3.8 High-p T Board ASIC High-p T Board ASIC 3 Slave Board 4 Slave Board Slow read-out from 3 wire triplet Slave Boards Phase adjust Phase adjust Phase adjust Phase adjust from 3 wire doublet Slave Boards Clock Phase adjust Phase adjust Phase adjust Snap shot Decoder Decoder 92 x fold Coin. Matrix window size: + 20 H/L Pt hit position δr x 2 Slow read-out track selector SOS063V0 Position + δ R 7-bit x 6 Position + δ R 0-bit x High-p T Board ASIC High-p T Board ASIC 3 Slave Board 4 Slave Board Slave Board = Slave Board δr 2 Slave Board Slave Board 4 Slave Board δr Slave Board Slave Board p T δr δr 20 < = δr < = < = X < = +5 δr > 0 2 δr 8 2 High-p T Board 4 Sector Logic 48

51 encoded hit-channel from triplet encoded hit-channel from triplet SOS06V05 decoder to 96-bit decoder to 96-bit A A encoded hit-channel (3-out-of-4 satisfied) decoder to 64 bits B B C C D H/L hit Pt position δr D encoded δr for Low-Pt 64x04 2-fold Coincidence Matrix window size: (3-bit) δr for High-Pt δr encoder -bit -bit 5-bit δr + positon 4-bit 3.9 High-p T Board inputs from triplet SOS062V05 8 inputs from low-pt matrix A B X = A & B X δr OR ed X window size -5 < = X < = < = δr < = +20 δr < = 0 : OR ed in a diagonal δr > = : OR ed in two diagonals 3.20 High-p T Board

52 High-p T Board High-p T Board δφ 3.2 Slow read-out from 3 strip triplet Slave Boards Phase adjust Phase adjust Phase adjust Clock Snap shot Decoder OR Decoder OR Decoder OR from 3 strip doublet Slave Boards Phase adjust Phase adjust Phase adjust Clock Snap shot Decoder Slow read-out x 64 2-fold Coin. Matrix H/L Pt hit position δϕ x 2 KHA00V02 Position + δϕ 6-bit x 6 track selector Position + δϕ 9-bit x High-p T Board ASIC High-p T Board High-p T Board Slave Board Slave Board High-p T ASIC Slave Board ASIC ASIC Sector Logic Sector Logic High-p T Board R, δr High-p T Board φ, δφ R-φ 6 p T p T 2 MUCTPI SSC Sub-Sector Clustor SSC R-φ p T δr, δφ p T 6 p T 9 p T p T 2 2 p T 2 MUCTPI Sector Logic 44 FPGA Sector Logic latency 8 FPGA δr, δφ p T 50

53 H/L hit Pt position δ R δr ( L / H ) x 8 0-bit decoder (position) " position " " Pt ( 6 - level ) " decoder (position) δϕ ( L / H ) track pre-selector 2 highest-pt tracks per pivot TGC track selector " position " " Pt ( 6 - level ) " 2 highest-pt tracks MUCPTI EI / FI hits decoder (position) H/L Pt hit position ϕ δ SOS08V07 δϕ ( L / H ) 9-bit x Sector Logic Sector Logic R-φ 2 MUCTPI SubSector Cluster(SSC) Trigger Sector (End Cap) candidate/ssc #9 Truck Pre-Selector Truck Selector #8 SubSector # To MUCTPI 4 5 # 6 RI Sector Logic 9 SSC Sub-Sector Clustor p T p T 2 5

54 4 TGC 4. ATLAS TGC FE Front-end TGC Slave Board Star Switch HDL ATLAS TGC URD User Required Document URD 52

55 ASIC Hardware Description Language HDL HDL HDL ASIC ASIC NAND NOR RTL Register Transfer Level RTL HDL RTL HDL HDL RTL Behavior Level HDL RTL HDL VHDL Verilog-HDL ATLAS TGC Verilog-HDL Verilog-HDL 4. 4 Verilog-HDL Synopsys Design Analyzer HDL HDL ASIC FPGA ASIC Application Specific Integrated Circuit LSI LSI 53

56 module counter(clk, reset, enable, q); input clk, reset, enable; output [3:0] q; reg [3:0] q; clk or negedge reset ) begin if(!reset ) q <= 0; else if(enable) q <= q + b; end endmodule q[3] q[3:0] enable q[2] q[] q[0] clk reset_ 4. Verilog-HDL HDL ASIC FPGA HDL HDL HDL HDL HDL 54

57 FPGA ASIC ASIC IC IC FPGA ASIC ASIC ASIC FPGA FPGA HDL HDL RTL HDL HDL ASIC FPGA HDL HDL HDL HDL HDL HDL HDL 4.3 TGC 4.3. TGC φ TGC TGC TGC 320 k 20 k 3.3 LA 00 khz 2 Tb/s TGC 4. [2]

58 Rates [Hz] Hits per event Wires Strips Wires Strips Inner Triplet Doublet TGC Hits per event TGC TGC USA5 USA5 ROB TGC 4.2 [3] TGC 0 0 CMOS ATLAS Radiation Level Radiation Tolerance Worst Location Best Location CMOS Bipolar Neutrons [n/cm 2 ] MeV Equivalent Neutrons [n/cm 2 ] Dose [Gy] TGC TGC TGC USA5 80 m 0 m 56

59 4.3.2 Slave Board Slave Board USA5 Slave Board m Slave Board Slave Slave Board USA5 80 m Slave Board master master slave slave slave slave slave slave slave slave Slave Board Slave Board Slave Board Slave Slave Board 4.5 Slave Board Slave Board Slave Board 2 Patch Panel Slave Board Patch Panel OR Patch Panel Patch Panel ASIC 6 Patch Panel ASIC Patch Panel Slave Board Patch Panel 57

60 Slave Board Slave Board Slave Board master master switch slave slave slave slave slave slave slave slave TGC Slave Board Slave Board Slave Board Slave Board 80 m 80 m 3 TGC TGC TGC 4.6 TGC Slave Board Star Switch Star Switch 20 Slave Board Star Switch Slave Board USA5 LDM Local DAQ Master ROD LDM RO-Link ROB ROB ATLAS DAQ 2 RoI Star Switch LDB Local DAQ Block LDB Star Switch 4.6 LDB LDB Slave Board TGC Star Switch TGC 0 m LS-Link Local Slave Link LS-Link Slave Board Star Switch Source Synchronous Data Transmission 0 m 2 LS-Link 4.6 Star Switch Local DAQ Master 80 m 3 X-Bus 58

61 to ROB Gb/s optical link ROD crate in USA5 B U S LDAQ LDAQ Master LDAQ Master LDAQ Master Master ROD to TGC DAQ Bi-dir optical links 00Mb/s, ~80m Star Switch 40Mb/s LVDS bi-dir links Inner Doublet Triplet Doublet pair LL04V0 4.6 TGC Slave Board Star Switch USA5 LDM LDB LDB Star Switch FE-Link Front End Link 00 Mb/s Slave Board TGC LID BCID High-p T Board Slave Board R, φ, δr, δφ Slave Board Slave Board High-p T Board TGC occupancy TGC LS-Link Star Switch Star Switch Slave Board Star Switch [2] 4.3 LDB

62 24 24 Slave Board LID BCID LA 00 MB/s Wires Strips Total LDB Type No. SB Chan. SB Chan. SB Chan. Raw[MB/s] hits/evt Cmp[kB/s] Doublet F Doublet E Triplet F Triplet E Inner F Inner E No. = Number per Octant SB = Slave Board, Chan. = Channels, Raw = Raw Data, Cmp = Compressed Data F = Forward, E = Endcap 4.3 TGC LDB LDB Slave Board 00 khz 24 LDB Type No. LDB No. SB Chan. Raw[MB/s] hits/evt Cmp[kB/s] Doublet F Doublet E Triplet F Triplet E Inner F Inner E Total Sides LDB = Local DAQ Block, SB = Slave Board, Chan. = Channels Raw = Raw Data, Cmp = Compressed Data F = Forward, E = Endcap 4.4 TGC Slave Board 00 khz 24 2 Sides TGC 60

63 4.3.4 ASIC FPGA ASIC FPGA 000 ASIC ASIC IC ATLAS ASIC FPGA FPGA FPGA Slave Board Slave Board TGC 2880 Slave Board TGC LA 2.5 μs Slave Board 40 MHz Star Switch 0 k Slave Board Slave Board ASIC Slave Board Slave Board ASIC Star Switch 208 Star Switch TGC Slave Board Star Switch FPGA ATLAS Slave Board Star Switch USA5 LDB ATLAS FE Front-end ATLAS FE [0, ] TGC 2.5 μs LVL latency LA LA TTC LA ROD ROB LA 75 khz % 00 khz 6% 6

64 LA 4 LA 24 LID 2 BCID ROD FE 24 2 ROB 00 μs ROB BUSY LID BCID TTC TTC LA, ECR Event Counter Reset, BCR Bunch Counter Reset BCID LID LVL ROB FE ATLAS DCS TGC FE Service Patch Panel Service Patch Panel Patch Panel Slave Board PS-Pack 3.0 TTC DCS CAN ASD threshold Slave Board Star Switch Star Switch Slave Board Patch Panel Star Switch DCS Local DAQ Master DCS Star Switch Local DAQ Master 62

65 TTC LA BCR ECR LID, BCID counter TGC signal LVL Buffer Trigger Matrix Derandomizer parameter setting control ROD,ROB MUCTPI DCS 4.7 TGC CAN ASD threshold Star Switch DCS Star Switch Slave Board Slave Board Patch Panel Slave Board 2 Slave Board Star Switch Slave Board Star Switch Slave Board Slave Board Star Switch LS-Link Local Slave Link Star Switch Slave Board LS-Link JTAG IC 4 IC Instruction I 2 C SDA Serial Data SCL Serial Clock 2 63

66 IC TTCrx I 2 C I 2 C CAN TGC JTAG JTAG IC JTAG TGC JTAG JTAG Appendix B TGC JTAG JTAG Slave Board Star Switch Patch Panel High-p T Board JTAG Patch Panel JTAG Slave Board ASIC Patch Panel ASIC Slave Board ASIC 8 Patch Panel ASIC Patch Panel ASIC Patch Panel ASIC Slave Board ASIC 4.8 Patch Panel ASIC Slave Board ASIC Patch Panel ASIC Patch Panel ASIC 2 JTAG Slave Board ASIC Slave Board ASIC Patch Panel 6ch 6ch 6ch PP ASIC PP ASIC PP ASIC 32ch Slave Board SB ASIC to High-pT Board Star Switch SSW FPGA?? DCS FE-link 6ch PP ASIC 32ch 4.8 TGC JTAG JTAG JTAG Patch Panel Slave Board 4.4 Slave Board 4.4. Slave Board Slave Board Slave Board Slave Board Appendix C Slave Board ASIC HDL Appendix C 64

67 from TTCrx BCR ECR LA CLK LID counter from Patch Panel B S C BCID counter Phase Adjust LVL buffer Derandomizer Parallel Serial Converter B S C L V D S to Star Switch to Patch Panel ASIC JTAG Selector Trigger Mask Trigger Matrix B S C Command Decorder JTAG Interface B S C L V D S from Star Switch Star Switch LVDS High-pT Board 4.9 Slave Board BSC Boundary Scan Cell TGC LA LA LVDS Star Switch TTL-LVDS ASIC 4.9 Slave Board Patch Panel TGC Phase Adjust LA 2.5 μs LA LVDS LS-Link Star Switch Star Switch LID BCID LID BCID TTC LA, ECR, BCR Slave Board LID 24 BCID 2 Slave Board BCID High-p T Board High-p T Board Slave Board Slave Board Star Switch JTAG TTL LVDS 65

68 Slave Board 4.9 Phase Adjust Patch Panel Slave Board Slave Board Slave Board TTC Phase Adjust JTAG Phase Adjust 4.0 Slave Board Phase Adjust IN OUT CLK 4.0 Phase Adjust Slave Board Trigger Matrix 0 JTAG JTAG LS-Link Slave Board 5 LA LVL latency 2.5 μs 00 TGC BCID TTC 28 JTAG 66

69 FIFO LID BCID TGC Appendix H ATLAS FE 5 8 Parallel Serial Converter LS-Link Star Switch Command Decorder Star Switch LS-Link 4 LS-Link LS-Link 4.6 TTL - LVDS Slave Board High-p T Board Star Switch LVDS JTAG Slave Board JTAG JTAG JTAG Appendix B BSC Boundary Scan Cell JTAG Appendix B JTAG JTAG Slave Board 4 Patch Panel 4.8 JTAG 4.5 Star Switch 4.5. Star Switch Star Switch Slave Board Local DAQ Master Star Switch 20 Slave Board BCID LID Slave Board FE-Link Front-end Link Local DAQ Master Star Switch Star Switch DCS FE-Link Slave Board Star Switch 4. Star Switch Slave Board LS-Link LVDS TTL 67

70 LS-link L V D S S P C Zero Suppress FIFO Data Collection & Format FIFO P S C E O C FE-link LS-link to Slave Board L V D S P S C controller JTAG central controller JTAG DCS or FE-link SPC : Serial Parallel Converter PSC : Paraller Serial Converter EOC : Electrical Optical Converter 4. Star Switch 20 Slave Board Local DAQ Master SPC Serial Parallel Converter LS-Link Slave Board Slave Board BCID LID PSC Parallel Serial Converter EOC Electrical Optical Converter FE-Link Local DAQ Master FIFO Slave Board JTAG Slave Board Star Switch Star Switch Slave Board Star Switch 20 Slave Board Star Switch Slave Board 20 Star Switch Star Switch Slave Board LS-Link, JTAG Slave Board FE-Link Local DAQ Master 68

71 4.2 Control BUS Data BUS Receiver Module Transmitter Module optical link Controller Module 4.2 Star Switch Star Switch Slave Board Local DAQ Master DCS LVDS-TTL LS-Link LVDS LVDS TTL SPC Serial Parallel Converter Slave Board TGC (a) TGC 4.4 (b) TGC 8 FIFO 69

72 LS-link L V D S S P C Zero Suppress FIFO BUS IF LS-link to Slave Board L V D S P S C JTAG Interface Sequencer controller CONTROLBUS DATABUS 4.3 FIFO FIFO BUSIF Slave Board 000,0000,0000,0,0000,0000,0000, ,0000,0000,0,0000,0000,0000, #hit= #hitcell=2 7 4 (a) (b) 4.4 (a) (b) 4 LSB 0 TTL LVDS FPGA 70

73 4.5 TTL LVDS FPGA 4 4 Slave Board FPGA Slave Board FPGA Slave Board FPGA 20 pin header to Slave Board TTL->LVDS LVDS->TTL FPGA to Slave Board TTL->LVDS LVDS->TTL FPGA to Slave Board to Slave Board TTL->LVDS LVDS->TTL TTL->LVDS LVDS->TTL FPGA FPGA CONTROL BUS DATABUS Slave Board LVDS-TTL FPGA 4.6 Local Slave Link 4.6. LS-Link LS-Link Local Slave Link Slave Board Star Switch TGC Slave Board BCID LID LS-Link Star Switch Star Switch Star Switch Slave Board Star Switch JTAG Slave Board Star Switch JTAG 5 TCK, TMS, TDI, TDO, TRST* 5 4 Xilinx FPGA Virtex LVDS TTL LVDS 5 TRST* 4 7

74 Slave Board Star Switch 40 MHz LHC LHC LHC Slave Board Star Switch 0 m TTL 40 MHz LVDS JTAG TCK TCK TTL LS-Link LVDS 40 MHz Slave Board Star Switch JTAG 40 MHz LHC LS-Link 4.6 LS-Link CLOCK, DATA, SYNC 3 CLOCK SYNC SYNC = 0, DATA = 0 SYNC = 0, DATA = SYNC = CLOCK SYNC SYNC = LVDS SYNC = 0 CLOCK DATA Variable Length Data SYNC Start Stop One Packet Frame Next Packet Chip Action Reset Receiver Sequence Execute Received Command HSA050V LS-Link Slave Board Star Switch LS-Link Slave Board Star Switch TGC TGC LID BCID Slave Board 3 Slave Board Star Switch 4.5 CLOCK 40 MHz LA 75 khz khz khz LA 3 72

75 send mode BC per event 2 BC per event 3 BC per event start code header address BCID LID hitdata trigger output trailer terminator total LS-Link Slave Board Slave Board Star Switch DATA 2 Slave Board Star Switch 4.6 Header (8) Address(8) BCID(8) LID(8) Data(28) Status(28) Checksum Header (8) Address(8) BCID(8) LID(8) Prev. Data(28) Next. Data(28) Checksum 4.6 Slave Board Star Switch LS-Link Star Switch Slave Board LS-Link Star Switch Slave Board LS-Link DATA LS-Link Slave Board Star Switch 73

76 Command Code Command Code Initialize 0000 Reset 000 Read Parameter 00 Standby 000 Read Counter 00 Run 00 Read Status LS-Link 4 Slave Board Star Switch CLOCK, SYNC, DATA0, DATA 4 TGC LVDS 4.6 Star Switch Slave Board CLOCK, SYNC, DATA 3 4 LVDS JTAG 4 5 LVDS LVDS 2 Slave Board Star Switch

77 pt3 ATLAS TGC FPGA pt3 5. pt3 pt3 Xilinx FPGA 4 6U VME pt3 5.2 FPGA Spartan XCS40 Plastic Quad Flat Package 208 VME P A24D6 A6D FPGA VME VME CPLD XC MHz NIM 2 CPLD CPLD FPGA Spartan FPGA XCS CLB Configurable Logic Block 206 CLB RAM CLB RAM 25 kb Spartan FPGA Spartan FPGA FPGA pt3 Slave Board ASIC Star Switch pt3 Slave Board ASIC Star Switch Slave Board ASIC ASIC ASIC ASIC ASIC FPGA FPGA Appendix D pt3 Appendix E 75

78 5. pt3 4 Xilinx Spartan FPGA CPLD 5..2 pt3 FPGA CLB Selected RAM Appendix D VME FPGA VME MHz VME MHz Selected RAM 76

79 Block Diagram of pt3 module FPGA XCS40 34pin header VME P address decoder CPLD XC9526 FPGA XCS40 FPGA XCS40 TTL-NIM Clock Out NIM-TTL External Clock 40MHz Clock FPGA XCS pt3 2 FPGA pt3 40 MHz 53 MHz FPGA CLB 53 MHz Slave Board Star Switch Foundation 50 % 2 77

80 Error rate Frequency [MHz] 5.3 pt3 53 MHz 5.2 Slave Board ASIC 5.2. Slave Board ASIC Slave Board ASIC 4 Slave Board ASIC HDL Verilog-HDL HDL pt3 FPGA HDL Appendix C C. C.2 Appendix C HDL 3 FPGA 5. Verilog HDL Slave Board ASIC Slave Board ASIC Slave Board 78

81 Patch Panel ASIC 28 8 BCID Slave Board ASIC SEU Single Event Upset SEU Appendix F LS-link JTAG Slave Board ASIC Slave Board Verilog Cadence Verilog-XL Slave Board ASIC Cadence Verilog-XL HDL 5.4 UDAT0, UDAT, USYN, UCLK Slave Board LS-Link Slave Board 6 LS-Link UDAT0 = 0, UDAT = 0, USYN = 0 UDAT0 =, UDAT =, USYN = 0 LA 6 TGC LS-Link HDL pt3 FPGA FPGA Xilinx Foundation ver FPGA CLB 72 % MHz 7 ns 79

82 Header: User: Date: Jan, :33:3 Time Scale From: To: Page: of SYSCLK TGCSIG7 TGCSIG6 TGCSIG5 TGCSIG4 TGCSIG3 TGCSIG2 TGCSIG TGCSIG0 BCR ECR LA UDAT0 UDAT USYN UCLK TIME Slave Board ASIC UDAT0, UDAT, USYN, UCLK Slave Board LS-Link Slave Board 6 80

83 5.2.2 FPGA pt3 FPGA 5..2 FPGA MHz FPGA Slave Board ASIC 20 MHz MHz LS-Link Slave Board ASIC ASIC FPGA 43 MHz FPGA Slave Board ASIC ASIC FPGA 8

84 Error rate Frequency [MHz] 5.6 FPGA Slave Board ASIC 43 MHz PSM Programmable Switch Matrix Appendix D PSM FPGA CLB Configurable Logic Block Appendix D D.2 CLB LUT Look-up Tabke LUT LUT ASIC ASIC FPGA FPGA ASIC Slave Board ASIC FPGA Slave Board ASIC Slave Board ASIC HDL 2 NAND Synopsys Design Analyzer Xilinx Foundation VDEC ASIC FPGA 82

85 CMOS 0.6 μm Xilinx FPGA Virtex HDL HDL 5. Foundation TGC Design Analyzer 28 ASIC UltraSPARC-II 300 MHz CPU Design Analyzer 5.8 Foundation 2 8 Design Analyzer Slave Board ASIC PSC 28 ASIC Gate Count [ 0 3 ] Number of Channels 5.7 Design Analyzer Slave Board ASIC Rohm CMOS 0.6 μm PSC Design Analyzer k Foundation k 83

86 Equivalent Gate Count [ 0 3 ] Number of Channel 5.8 Foundation Slave Board ASIC Virtex k 5 Slave Board ASIC k 500 k ASIC Slave Board ASIC 5.9 (a) FIFO FIFO FIFO FIFO FIFO 5.9 (b)

87 Gate Count Number of Net Net/Gate Ratio Trigger Mask Level Buffer Derandomizer Parallel Serial Converter Others Total Slave Board ASIC Design Analyzer 28 Others (a) Level Buffer (Shift Register) (b) Derandomizer (FIFO) 5.9 (a) (b) ns 40 MHz ASIC 5.3 VDEC ASIC 5.3. VDEC FPGA Slave Board ASIC ASIC VDEC VLSI Design and Education Center, ASIC 3 2 ASIC FIFO 3 85

88 VDEC VLSI Very Large Scale Integration VDEC VLSI ASIC VDEC VLSI CMOS 0.6 μm 4.5 mm 4.5 mm k Slave Board ASIC HDL ASIC HDL HDL Cadence Verilog-XL Synopsys Design Analyzer CMOS 0.6 μm Cadence Verilog-XL VDEC Avant Apollo DRC Design Rule Check LVS Layout vs Schematic Cadence Dracula ASIC ASIC Slave Board ns Spartan FPGA 9. ns 86

89 DROVF LACC LSIG PWRON* L CNT LSLDCLK LSLDSYN LSLDDAT LSLCMD CRESET SYSRESET XFRMODE DERSEQ DRWPNT DRRPNT DR PSCEMPTY DRRDY DRDOUT RDOSEQ PSCLOAD PSCCLK PSCIN PSCSYN PSCOUT PSC 5.0 VDEC Slave Board 5. VDEC ASIC 87

90 ASIC ASIC 5. ASIC Slave Board ASIC ASIC VDEC ASIC Star Switch 5.4. HDL Star Switch Slave Board ASIC Verilog HDL pt3 Star Switch 5.2 Star Switch Slave Board LS-Link FIFO FIFO RESET LSLUCLK LSLUSYN LSLUDAT 2 DSYN Sync2 DDAT 2 Serial Parallel Converter 256 SPCOUT 8 HEADER SPCCOMPLETE SPC Output Switch MODE 28 HITDATA_PREV 28 HITDATA_CUR 28 HITDATA_NEXT 28 HEADER,BCID,etc ZSLOAD Zero Suppress Receiver Sequencer 64X3 CELLIDLIST 28X3 DATALIST 6X3 NHITCELL Derandomizer Preformatter START STEPCOUNT 32 FDATAIN CTRLIN WRITE 32 FDATAOUT Data BUS Interface CTRLOUT ACKNOWLEDGE* 32 COMMAND ADDRESS* DATABUS 5.2 Star Switch 8 COMMAND ACKNOWLEDGE* COMMAND high ACKNOWLEDGE* low Star Switch Star Switch

91 BCID 6 32 Slave Board 28 TGC TGC TGC Slave Board Verilog Star Switch pt3 FPGA pt3 module () Clock Generator PPG ECL to TTL Converter FPGA receiver module databus FPGA 2 bus master EXTCLK pt3 module (2) FPGA pattern recorder 5.3 Star Switch 5.3 PPG TTL pt3 pt3 COMMAND high pt3 pt Slave Board ASIC 5.3 TGC 89

92 0 MHz NBit CLB usage Number of Flip Flop Frequency [MHz] (37%) 43 (26%) (56%) 568 (36%) (67%) 669 (42%) (72%) 86 (52%) (83%) 940 (59%) (9%) 064 (67%) (96%) 88 (75%) NBit TGC FPGA 5.4 Foundation 30 MHz 35 MHz TGC MHz MHz 30 MHz 30 MHz 40 MHz Spartan FPGA Appendix D D.2 FPGA Virtex FPGA D.2 Spartan 3 40 MHz Virtex XCV MHz 3 40 MHz FPGA FPGA Star Switch 90

93 Error rate Error rate Error rate Frequency [MHz] Frequency [MHz] Frequency [MHz] Error rate Error rate Error rate Frequency [MHz] Frequency [MHz] Frequency [MHz] Error rate Frequency [MHz] 5.4 () N TGC Star Switch pt3 pt3 9

94 Error rate Error rate Error rate Frequency [MHz] Frequency [MHz] Frequency [MHz] Error rate Error rate Error rate Frequency [MHz] Frequency [MHz] Frequency [MHz] Error rate Frequency [MHz] 5.5 (2) 30 MHz N TGC Slave Board Local DAQ Master BCID LID Slave Board JTAG LS-Link Star Switch pt4 pt4 92

95 Maximum Frequency [MHz] Data Length 5.6 TGC 30 MHz FPGA 40 MHz VME VME LVDS TTL FPGA pt4 FPGA Xilinx Foundation Xilinx FPGA 93

96 HDL Foundation FPGA HDL FPGA Slave Board LA 3 TGC TGC 2 3 FIFO FIFO Slave Board FPGA FPGA pt4 FPGA FPGA 40MHz LHC Xilinx FPGA FPGA FPGA Slave Board FIFO k Spartan FPGA FPGA XC4000XLA XC4000XV Virtex Xilinx FPGA Appendix D 5.7 FPGA FPGA FPGA CLB Configurable Logic Block CLB 2 4 FPGA Appendix D FPGA FPGA XC4000XLA XC4000XV 20 MHz 40 MHz 40 MHz Virtex FPGA 4 Virtex CLB 4 SLICE 2 Virtex CLB SLICE 94

97 Maximum Frequency [MHz] Size of FPGA (Number of CLB) 5.7 FPGA FIFO FPGA FPGA Virtex FPGA Virtex XCV600 4HQ240 FPGA 692 CLB SLICE FPGA FIFO FIFO FPGA FIFO CLB FIFO FIFO TGC 0 FIFO FIFO FIFO 95

98 Number of CLB Maximum Frequency [MHz] Depth of Derandomizer Depth of Derandomizer 5.8 FIFO 5.9 FIFO FPGA Slave Board FPGA Slave Board FPGA Slave Board Slave Board FPGA Slave Board FIFO Slave Board FPGA Xilinx Virtex 40 MHz FIFO FPGA Slave Board FPGA pt4 FPGA Slave Board FPGA FIFO FPGA FIFO FPGA IC FPGA FIFO FPGA FPGA CLB RAM Virtex RAM FPGA Slave Board Star Switch TGC 0 cm 2 96

99 Number of CLB Maximum Frequency [MHz] Number of Slave Board covered by one FPGA Number of Slave Board covered by one FPGA 5.20 FPGA Slave 5.2 FPGA Slave Board Board FPGA FPGA FPGA FPGA SEU Appendix F FPGA FPGA ASIC Star Switch 5.5 LS-Link Slave Board Star Switch LS-Link 9m LHC 40 MHz LVDS Appendix G LVDS LS-Link LVDS DS90C03 4 TTL LVDS DS90C032 4 LVDS TTL 00 Ω IC 5.22 LVDS 34 4 LS-Link MHz m 50 MHz TTL LVDS DS90C03 DS90C MHz 50 MHz 6 m 97

100 PPG ECL to TTL Converter TTL to LVDS Converter LVDS to TTL Converter logic analyzer DS90C03 twist pair cable DS90C032 Clock Generator 5.22 LVDS 45 MHz LVDS LS-Link 40 MHz 0 m Maximum Frequency[MHz] Cable Length[m] 5.23 LVDS 5 MHz 28 m 33 m 28 m 33 m 98

101 6 ATLAS TGC Slave Board Star Switch Slave Board Slave Board ASIC HDL HDL pt3 FPGA Slave Board ASIC Slave Board ASIC ASIC VDEC ASIC ASIC HDL ASIC ASIC 200 k Star Switch Slave Board HDL FPGA pt MHz FPGA LHC 40 MHz LS-Link LVDS LS-Link 40 MHz 0 m TGC 6. TGC ATLAS TGC TGC Star Switch 40 MHz FPGA FPGA Xilinx Virtex 40 MHz Star Switch 40 k 99

102 Level- Muon End-cap Electronics Schedule Item ASD Board ASD chip R&D ASD chip mass production ASD board R&D ASD board mass production Patch panel Patch-panel IC prototype-0 Patch-panel IC prototype- + rad. tol. test Patch-panel IC prototype-2 + rad. tol. test Patch-panel IC mass production Patch-panel board prototype- Patch-panel board prototype-2 Patch-panel board mass production Slave board / High-pt board Trigger IC prototype-0 Trigger IC prototype- + rad. tol. test Trigger IC prototype-2 + rad. tol. test Trigger IC mass production Trigger board prototype- Trigger board prototype-2 Trigger board mass production Sector Logic Sector-logic board prototype- Sector-logic board prototype-2 Sector-logic board mass production Readout Protocol test Star-switch board prototype- Star-switch board prototype-2 Star-switch board mass production Local-DAQ-Master board prototype- Local-DAQ-Master board prototype-2 Local-DAQ-Master board mass production ROD board prototype- ROD board prototype-2 ROD board mass production Assembly On-chamber pre-assembly System installation System integration System test st full system test: Sept Full system test before mass production: Sept TGC Slave Board FPGA Slave Board ASIC VDEC ASIC 2000 Slave Board ASIC Slave Board Star Switch 00

103 KEK KEK ICEPP KEK ATLAS TGC 0

104 Appendix A A. ATLAS [7] A. 02

105 Scope Planning [S] Scope Definition [S] Activity Definition [T] Resource Planning [C] Activity Sequecing [T] Activity Duration Estimating [T] Cost Estimating [C] Schedule Development [T] Cost Budgeting [C] Project Plan Development [I] A. S = Scope, T = Time, C = Cost, I = Integration Scope Planning Scope Definition WBS Work Breakdown Structure WBS Activity Definition WBS Resource Planning WBS Cost Estimating WBS Activity Sequencing A.2 Activity Duration Estimating Schedule Development A.3 Cost Budjeting WBS Project Plan Development [7] 03

106 Start A D B E C F Finish Start A D B E C F Finish A.2 PDM Precedence Diagramming Method ADM Arrow Diagramming Method Activity A Activity B Activity C Activity D Jun Jul Aug Sep Oct Nov Time A.3 A.2 ATLAS ATLAS ATLAS A.4 4 [9] WHERE? WHAT? HOW? WHO? ABS PBS WBS OBS Assembly Breakdown Structure (the project dismantled into bits and pieces) Project/product Breakdown structure The tasks to be performed on the components The responsible persons Standard Tasks A.4 ATLAS 4 ABS Assembly Breakdown Structure BOM Bill Of Material ABS PBS 04

107 Product Breakdown Structure Project Breakdown Structure WBS ATLAS 4 PBS ATLAS WBS PBS OBS Organizational Breakdown Structure PBS ATLAS ATLAS Detector, ATLAS General Facilities, ATLAS Assembly & Test Areas, ATLAS Offine Computing, ATLAS Technical Coordination 5 PBS ATLAS Detector A.5 Slave Board Star Switch ATLAS ATLAS Vacuum Beam V Inner Beam VI. Argon Beam VA.2 Torroid Beam VT.3 Shielding Beam VJ.4 PBS number Inner Detector I 2 Pixel Detector IP 2. Semi Cond. Tracker IS 2.2 TRT IT 2.3 Common Items IC 2.4 Solenoid Magnet S 3 Coil SC 3. Cryostat SY 3.2 Chimney/- dewar SD 3.3 Control/ Safety SS 3.4 LAr Calorimet- A 4 Barrel AB 4. End-Cap AE 4.2 Proximity Services AP 4.3 Electronics AL 4.4 PBS name ATLAS Detector ATL Tile Calorimet- L 5 Barrel LB 5. Extended LE 5.2 Optics LO 5.3 Electronics LL 5.4 Control LC 5.5 Toroid Magnets T 6 Barrel TB 6. End-Cap TE 6.2 Muon Chamber- M 7 MDT Chambers MM 7. CSC Chambers MC 7.2 RPC Chambers MR 7.3 TGC Chambers MT 7.4 Off-chamber Gas Systems MG 7.5 Off-chamber Electronics ME 7.6 Position Monitoring MA 7.7 Support MH 7.8 Shielding J 8 Disk JD 8. Forward JF 8.2 END CAP Toroid JT 8.3 Moderator JM 8.4 Support Structur- H 9 Barrel Rail System HB 9. Forward Rail System HF 9.2 Surrounding Structure HS 9.3 Access Structure HX 9.4 Big wheel rail support HX 9.5 End wall HO 9.6 DAQ Trigger D 0 under discussion A.5 ATLAS Detector PBS 05

108 Appendix B JTAG IEEE49. B. JTAG IC JTAG Joint Test Action Group IEEE Institute for Electrical and Electronics Engineering 49. [8] NDI BSC Core Logic BSC NDO TDI TDO B. JTAG IC JTAG B. IC JTAG IC boundary boundary scan B.2 JTAG JTAG IEEE49. B.2 TCK TMS TDI TDO 4 TCK TMS TDI TDO 3 TRST* 5 06

109 TRST* TAP Test-Logic-Reset Boundary-Scan Register Test-Logic-Reset OE BSC 0 BSC BSC Run-Test/Idle Select-DR-Scan Select-IR-Scan Input Pins TDI BSC BSC BSC Core Logic User Data Register Bypass Resister BSC BSC BSC Output Pins Capture-DR 0 Shift-DR 0 Exit-DR 0 Pause-DR 0 Capture-IR 0 Shift-IR Exit-IR 0 Pause-IR 0 0 TMS TCK TAP Instruction Register Exit2-DR Update-DR 0 0 Exit2-IR Update-IR TDO 0 0 Note: The boundary-scan register is shifted TDI to TDO. B.2 JTAG B.3 JTAG TAP Boundary Scan Cell BSC Boundary Scan Register BSR TDI TDO BSR Instruction Register IR IR Data Register (DR) DR BSR (BYPASS Register) (Device ID Register) IC TAP (Test Access Port) TAP TCK TMS TCK TMS TAP B.3 Test-Logic-Reset IR Shift-IR TMS 0 TDI Shift-DR TDI IR DR B.4 BSC IC 07