スライド 1

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1 STRJ WS: March 9, 2006,

2 0.35µm 0.8µm 0.3µm STRJ WS: March 9, 2006, 2

3 0.35µm Lot-to-Lot, Wafer-to-Wafer, Die-to-Die(D2D) D2D 0.8µm (WID: Within Die) D2D vs. WID 0.3µm D2Dvs. WID STRJ WS: March 9, 2006, 3

4 0.35µm:Good Old Days Ids (ma) 5 All Lots 0 Single Lot 5 58 Lots, Vds(V) STRJ WS: March 9, 2006, Wafers

5 0.35µm, D2D Ids (ma) 5 All Lots 0 Single Wafer 5 58 Lots, Vds(V) STRJ WS: March 9, 2006, Wafers

6 0.35µm Id_sat (pmos vs nmos) (?) STRJ WS: March 9, 2006, 6

7 0.8µm TEG 0.8µm, 2.9 mm, 20 TEG Ids 6 Transistors/chip Ring OSC TEGs Transistor TEG 20 RO 2,800 RO TEG 2 RO TEG STRJ WS: March 9, 2006, 7

8 WID 0.8µm, ~5% ~5% 5% 5% ( ) STRJ WS: March 9, 2006, 8

9 0.8µm: Ring OSC TEG 7 0 Sections Inv RO :7,3,9,29 : 5,0,20,40,60, NAND2 NAND4 RO 0 types of ROs STRJ WS: March 9, 2006, 9

10 : (WID) 3% : 9 :00 70 STRJ WS: March 9, 2006, 0

11 (WID) :00, 9 3% (D2D) (WID) (D2D) STRJ WS: March 9, 2006,

12 : Ids: : % TEG < TEG 2 % TEG < TEG 2 2% TEG Layout TEG2 STRJ WS: March 9, 2006, 2

13 0.3µm µ 3σ in a chip Drain Current 6 transistors/chip 56 chips/wafer (D2D) (WID) # (WID) (D2D) STRJ WS: March 9, 2006, 3

0.3µm: Ids (WID) (D2D) W 0µm 34 5 6 7 0.

14 0.3µm: Ids (WID) (D2D) W 0µm µm 2 Transistor sizes µm 0µm L STRJ WS: March 9, 2006, 4

15 Ids (WID) VDS=0.(V), VGS=.0(V) WL [Pelgrom, et al., J-SSC 989] Okada et.al., JJAP, p.3, 2005 STRJ WS: March 9, 2006, 5

16 STRJ WS: March 9, 2006, 6

17 C, R S W H T C R ( ) STRJ WS: March 9, 2006, 7

18 ITRS2005 Intermediate W,T,H : 3σ=30% resistance variation[%] resistance variation[%] capacitance variation[%] capacitance variation[%] S=W S=7W ( 00%) ( 25%) STRJ WS: March 9, 2006, 8

19 0.5 Xp SF=(-0.8,0.4) TT FF FS=(0.6,-0.5) FF, SS, TT, SF, FS Idsat nmos pmos SS Xn STRJ WS: March 9, 2006, 9

20 + STRJ WS: March 9, 2006, 20

21 Monte Carlo (CDF) ( ) probability probability Id(sat) 0 delay time nmos Idsat CDF Inv (FO4) CDF STRJ WS: March 9, 2006, 2

22 ( + ) Rtr R C CL W,T,H (Rtr) D = 0.4RC + 0.7( RtrC + RtrCL + RCL ) STRJ WS: March 9, 2006, 22

23 Intermediate S=W (lopt = 94µm, Xopt=32) regression coefficient output resistance width thickness height regression coefficient output resistance width thickness height wire length [um] wire length [um] X X6 STRJ WS: March 9, 2006, 23

24 Global S=W (lopt = 60 µm, Xopt = 67) regression coefficient output resistance width thickness height regression coefficient output resistance width thickness height wire length [um] wire length [um] X4 X32 STRJ WS: March 9, 2006, 24

25 Probability Density D n= = max D i,2 n i circuit =,..., i n=0 n=00 n=000 D i : N(5, ) n D circuit STRJ WS: March 9, 2006, 25

26 Probability Density D circuit σ = 0.5 = max D,2,..., 00 i σ =.0 σ = 2.0 i= D circuit i D i : N(5, σ) STRJ WS: March 9, 2006, 26

27 Probability Density D circuit = max D,2,..., 00 i i= D circuit i ρ = 0.0 ρ = 0.2 ρ = 0.4 ρ = 0.6 ρ = 0.8 ρ =.0 D i : N(5, σ) : ρ P,V,T STRJ WS: March 9, 2006, 27

28 Good News Bad News ( ) ( ) STRJ WS: March 9, 2006, 28

29 0.35µm 0.8µm 0.3µm STRJ WS: March 9, 2006, 29

30 (D2D,WID) ( ) (WID) / (Yamaoka et.al., ISSCC04/05) STRJ WS: March 9, 2006, 30

31 D2D, WID ACV ( ) LUT/ /PE STRJ WS: March 9, 2006, 3

32 P BC TYP WC L eff Cell Cell delay/si delay/si models models STRJ WS: March 9, 2006, 32

33 STA P WC P WC P WC L eff L eff L eff P P P L eff L eff L eff STRJ WS: March 9, 2006, 33

34 ( STA) P PDF(CDF) STRJ WS: March 9, 2006, 34

35 vs. DFF STRJ WS: March 9, 2006, 35

36 vs. vs. STRJ WS: March 9, 2006, 36

37 ( ) LUT Katsuki, et.al. CICC05 Processing Unit (): LUT,, PE, etc. STRJ WS: March 9, 2006, 37

38 (0.35, 0.8, 0.3 µm) ( ) + LUT/ /PE STRJ WS: March 9, 2006, 38

39 STRJ WS: March 9, 2006, 39

MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated

1 -- 7 6 2011 11 1 6-1 MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated Injection Logic 6-3 CMOS CMOS NAND NOR CMOS 6-4 6-5 6-1 6-2 CMOS 6-3 6-4 6-5 c 2011 1/(33)