お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com) 2010 年 4 月 1 日ルネサスエレクトロニクス株式会社 発行 ルネサスエレクトロニクス株式会社 (http://www.renesas.com) 問い合わせ先 http://japan.renesas.com/inquiry
ご注意書き 1. 本資料に記載されている内容は本資料発行時点のものであり 予告なく変更することがあります 当社製品のご購入およびご使用にあたりましては 事前に当社営業窓口で最新の情報をご確認いただきますとともに 当社ホームページなどを通じて公開される情報に常にご注意ください 2. 本資料に記載された当社製品および技術情報の使用に関連し発生した第三者の特許権 著作権その他の知的財産権の侵害等に関し 当社は 一切その責任を負いません 当社は 本資料に基づき当社または第三者の特許権 著作権その他の知的財産権を何ら許諾するものではありません 3. 当社製品を改造 改変 複製等しないでください 4. 本資料に記載された回路 ソフトウェアおよびこれらに関連する情報は 半導体製品の動作例 応用例を説明するものです お客様の機器の設計において 回路 ソフトウェアおよびこれらに関連する情報を使用する場合には お客様の責任において行ってください これらの使用に起因しお客様または第三者に生じた損害に関し 当社は 一切その責任を負いません 5. 輸出に際しては 外国為替及び外国貿易法 その他輸出関連法令を遵守し かかる法令の定めるところにより必要な手続を行ってください 本資料に記載されている当社製品および技術を大量破壊兵器の開発等の目的 軍事利用の目的その他軍事用途の目的で使用しないでください また 当社製品および技術を国内外の法令および規則により製造 使用 販売を禁止されている機器に使用することができません 6. 本資料に記載されている情報は 正確を期すため慎重に作成したものですが 誤りがないことを保証するものではありません 万一 本資料に記載されている情報の誤りに起因する損害がお客様に生じた場合においても 当社は 一切その責任を負いません 7. 当社は 当社製品の品質水準を 標準水準 高品質水準 および 特定水準 に分類しております また 各品質水準は 以下に示す用途に製品が使われることを意図しておりますので 当社製品の品質水準をご確認ください お客様は 当社の文書による事前の承諾を得ることなく 特定水準 に分類された用途に当社製品を使用することができません また お客様は 当社の文書による事前の承諾を得ることなく 意図されていない用途に当社製品を使用することができません 当社の文書による事前の承諾を得ることなく 特定水準 に分類された用途または意図されていない用途に当社製品を使用したことによりお客様または第三者に生じた損害等に関し 当社は 一切その責任を負いません なお 当社製品のデータ シート データ ブック等の資料で特に品質水準の表示がない場合は 標準水準製品であることを表します 標準水準 : コンピュータ OA 機器 通信機器 計測機器 AV 機器 家電 工作機械 パーソナル機器 産業用ロボット高品質水準 : 輸送機器 ( 自動車 電車 船舶等 ) 交通用信号機器 防災 防犯装置 各種安全装置 生命維持を目的として設計されていない医療機器 ( 厚生労働省定義の管理医療機器に相当 ) 特定水準 : 航空機器 航空宇宙機器 海底中継機器 原子力制御システム 生命維持のための医療機器 ( 生命維持装置 人体に埋め込み使用するもの 治療行為 ( 患部切り出し等 ) を行うもの その他直接人命に影響を与えるもの )( 厚生労働省定義の高度管理医療機器に相当 ) またはシステム等 8. 本資料に記載された当社製品のご使用につき 特に 最大定格 動作電源電圧範囲 放熱特性 実装条件その他諸条件につきましては 当社保証範囲内でご使用ください 当社保証範囲を超えて当社製品をご使用された場合の故障および事故につきましては 当社は 一切その責任を負いません 9. 当社は 当社製品の品質および信頼性の向上に努めておりますが 半導体製品はある確率で故障が発生したり 使用条件によっては誤動作したりする場合があります また 当社製品は耐放射線設計については行っておりません 当社製品の故障または誤動作が生じた場合も 人身事故 火災事故 社会的損害などを生じさせないようお客様の責任において冗長設計 延焼対策設計 誤動作防止設計等の安全設計およびエージング処理等 機器またはシステムとしての出荷保証をお願いいたします 特に マイコンソフトウェアは 単独での検証は困難なため お客様が製造された最終の機器 システムとしての安全検証をお願いいたします 10. 当社製品の環境適合性等 詳細につきましては製品個別に必ず当社営業窓口までお問合せください ご使用に際しては 特定の物質の含有 使用を規制する RoHS 指令等 適用される環境関連法令を十分調査のうえ かかる法令に適合するようご使用ください お客様がかかる法令を遵守しないことにより生じた損害に関して 当社は 一切その責任を負いません 11. 本資料の全部または一部を当社の文書による事前の承諾を得ることなく転載または複製することを固くお断りいたします 12. 本資料に関する詳細についてのお問い合わせその他お気付きの点等がございましたら当社営業窓口までご照会ください 注 1. 注 2. 本資料において使用されている 当社 とは ルネサスエレクトロニクス株式会社およびルネサスエレクトロニクス株式会社がその総株主の議決権の過半数を直接または間接に保有する会社をいいます 本資料において使用されている 当社製品 とは 注 1 において定義された当社の開発 製造製品をいいます
User s Manual 16 M16C/60M16C/20 M16C/Tiny 16 www.renesas.com Rev.4.002004.01
bit,bit,anbit, bit,an An bit, bit,an bit
bit,base bit base base bit
SBFB SBFBSB FB base bit An base An
dsp:8[a0] dsp:8[a1] dsp:16[a0] dsp:16[a1] d A0 / A1 address dsp
#IMM #IMM #IMM8 #IMM8 #IMM16 #IMM20 #IMM16 #IMM20 R0L R0H R0L / R1L R1L R1H R0 R0H / R1H R1 R0 / R1 / R2 / R2 R3 / A0 / A1 R3 A0 A1 [A0] [A1] A0 / A1 address
dsp:8[a0] dsp:8[a1] dsp:16[a0] dsp:16[a1] A0 / A1 address dsp dsp:8[sb] dsp:16[sb] SB address dsp address dsp:8[fb] FB dsp address dsp dsp address dsp
dsp:8[sp] SP dsp dsp address dsp address dsp
abs20 abs20 dsp:20[a0] dsp:20[a1] LDESTE A0 address dsp JMPIJSRI A0 / A1 address dsp [A1A0] PC A1 A0 address-h address-l address
R2R0 R3R1 A1A0 SHLSHA R2R0 R3R1 JMPIJSRI R2R0 R3R1 A1A0 PC INTBL INTBH ISP SP SB FB FLG INTBL INTBH ISP USP SB FB FLG
label dsp label dsp dsp dsp dsp label label
BCLRBSETBNOTBTSTBNTSTBANDBNANDBORBNORBXORBNXORBMCnd BTSTSBTSTC bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit, R0 R0 bit,a1 bit,base:16 base [A0] [A1]
base:8[a0] base:8[a1] base:16[a0] base:16[a1] base SB bit,base:8[sb] bit,base:11[sb] bit,base:16[sb] SB address base address
FB bit,base:8[fb] base ( ) FB address base base address base FLG U I O B S Z D C FLG U I O B S Z D C
MOV MOV.size (:format), MOVe G, Q, Z, S B, W MOV R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 dsp:8[sp] R2R0 R3R1 A1A0 dsp:8[sp] U I O B S Z D C MOV.B:S MOV.W #0ABH,R0L #-1,R2 LDE,STE,XCHG 92
MOV.size (: format), G, Q, S, Z B, W MOV.size (: format),
MOV MOV.size (:format), MOVe G, Q, Z, S B, W MOV R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 dsp:8[sp] R2R0 R3R1 A1A0 dsp:8[sp] U I O B S Z D C MOV.B:S MOV.W #0ABH,R0L #-1,R2 LDE,STE,XCHG 92
R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 dsp:8[sp] R2R0 R3R1 A1A0 dsp:8[sp]
JMP JMP (.length) label JuMP S, B, W, A JMP JMP (.length) label S, B, W, A JMP.length label
ABS ABSolute ABS ABS.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C ABS.B ABS.W R0L A0
ADC ADdition with Carry ADC ADC.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C ADC.B #2,R0L ADC.W A0,R0 ADC.B A0,R0L ADC.B R0L,A0 ADCF,ADD,SBB,SUB
ADCF ADdition Carry Flag ADCF ADCF.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C ADCF.B ADCF.W R0L Ram:16[A0] ADC,ADD,SBB,SUB
ADD ADD.size (:format), ADDition G, Q, S B, W ADD R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C ADD.B A0,R0L ADD.B R0L,A0 ADD.B Ram:8[SB],R0L ADD.W #2,[A0] ADC,ADCF,SBB,SUB
G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 Q R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1
ADJNZ ADJNZ.size,,label ADdition then Jump on Not Zero B, W ADJNZ if then label R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 #IMM [A0] [A1] dsp:8[a0] PC 126labelPC +129 dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] U I O B S Z D C ADJNZ.W # 1,R0,label SBJNZ
AND AND.size (:format), AND G, S B, W AND R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C AND.B Ram:8[SB],R0L AND.B:G A0,R0L AND.B:G R0L,A0 AND.B:S #3,R0L OR,XOR,TST
S G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1
BAND BAND Bit AND carry flag BAND bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BAND BAND BAND BAND flag 4,Ram 16,Ram:16[SB] [A0] BOR,BXOR,BNAND,BNOR,BNXOR
BCLR BCLR (:format) Bit CLeaR G, S BCLR bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BCLR BCLR BCLR BCLR flag 4,Ram:8[SB] 16,Ram:16[SB] [A0] BSET,BNOT,BNTST,BTST,BTSTC,BTSTS
BMCnd BMCnd Bit Move Condition BMCnd if true then else U I O B S Z D C bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] BMN BMZ 3,Ram:8[SB] C JCnd
BNAND Bit Not AND carry flag BNAND BNAND bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BNAND BNAND BNAND BNAND flag 4,Ram 16,Ram:16[SB] [A0] BAND,BOR,BXOR,BNOR,BNXOR
BNOR BNOR Bit Not OR carry flag BNOR bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BNOR BNOR BNOR BNOR flag 4,Ram 16,Ram:16[SB] [A0] BAND,BOR,BXOR,BNAND,BNXOR
BNOT BNOT(:format) Bit NOT G, S BNOT bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BNOT BNOT BNOT BNOT flag 4,Ram:8[SB] 16,Ram:16[SB] [A0] BCLR,BSET,BNTST,BTST,BTSTC,BTSTS
BNTST Bit Not TeST BNTST BNTST bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BNTST BNTST BNTST BNTST flag 4,Ram:8[SB] 16,Ram:16[SB] [A0] BCLR,BSET,BNOT,BTST,BTSTC,BTSTS
BNXOR Bit Not exclusive OR carry flag BNXOR BNXOR bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BNXOR BNXOR BNXOR BNXOR flag 4,Ram 16,Ram:16[SB] [A0] BAND,BOR,BXOR,BNAND,BNOR
BOR Bit OR carry flag BOR BOR bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BOR BOR BOR BOR flag 4,Ram 16,Ram:16[SB] [A0] BAND,BXOR,BNAND,BNOR,BNXOR
BRK BRK BReaK BRK U I O B S Z D C BRK INT,INTO
BSET BSET (:format) Bit SET G, S BSET bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BSET BSET BSET BSET flag 4,Ram:8[SB] 16,Ram:16[SB] [A0] BCLR,BNOT,BNTST,BTST,BTSTC,BTSTS
BTST BTST (:format) Bit TeST G, S BTST bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BTST BTST BTST BTST flag 4,Ram:8[SB] 16,Ram:16[SB] [A0] BCLR,BSET,BNOT,BNTST,BTSTC,BTSTS
BTSTC BTSTC Bit TeST & Clear BTSTC bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BTSTC BTSTC BTSTC BTSTC flag 4,Ram 16,Ram:16[SB] [A0] BCLR,BSET,BNOT,BNTST,BTST,BTSTS
BTSTS BTSTS Bit TeST & Set BTSTS bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BTSTS BTSTS BTSTS BTSTS flag 4,Ram 16,Ram:16[SB] [A0] BCLR,BSET,BNOT,BNTST,BTST,BTSTC
BXOR BXOR Bit exclusive OR carry flag BXOR bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] base:8[a0] base:8[a1] bit,base:8[sb] bit,base:8[fb] base:16[a0] base:16[a1] bit,base:16[sb] bit,base:16 C bit,base:11[sb] U I O B S Z D C BXOR BXOR BXOR BXOR flag 4,Ram 16,Ram:16[SB] [A0] BAND,BOR,BNAND,BNOR,BNXOR
CMP CMP.size (:format), CoMPare G, Q, S B, W CMP R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C CMP.B:S #10,R0L CMP.W:G R0,A0 CMP.W # 3,R0 CMP.B #5,Ram:8[FB] CMP.B A0,R0L
G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 Q R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1
DADC DADC.size, Decimal ADdition with Carry B, W DADC R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C DADC.B DADC.W #3,R0L R1,R0 DADD,DSUB,DSBB
DADD DADD.size, Decimal ADDition B, W DADD R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C DADD.B DADD.W #3,R0L R1,R0 DADC,DSUB,DSBB
DEC DECrement DEC DEC.size B, W R0L R0H dsp:8[sb] dsp:8[fb] A0 A1 U I O B S Z D C DEC.W DEC.B A0 R0L INC
DIV DIVide DIV DIV.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM R2R0 R3R1 A1A0 U I O B S Z D C DIV.B A0 DIV.B #4 DIV.W R0 DIVU,DIVX,MUL,MULU
DIVU DIVide Unsigned DIVU DIVU.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM R2R0 R3R1 A1A0 U I O B S Z D C DIVU.B A0 DIVU.B #4 DIVU.W R0 DIV,DIVX,MUL,MULU
DIVX DIVide extension DIVX DIVX.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM R2R0 R3R1 A1A0 U I O B S Z D C DIVX.B A0 DIVX.B #4 DIVX.W R0 DIV,DIVU,MUL,MULU
DSBB Decimal SuBtract with Borrow DSBB DSBB.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C DSBB.B DSBB.W #3,R0L R1,R0 DADC,DADD,DSUB
DSUB Decimal SUBtract DSUB DSUB.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C DSUB.B DSUB.W #3,R0L R1,R0 DADC,DADD,DSBB
ENTER ENTER ENTER function ENTER #IMM U I O B S Z D C ENTER #3 EXITD
EXITD EXITD EXIT and Deallocate stack frame EXITD U I O B S Z D C EXITD ENTER
EXTS EXTend Sign EXTS EXTS.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C EXTS.B EXTS.W R0L R0
FCLR FCLR Flag register CLeaR FCLR C D Z S B O I U U I O B S Z D C FCLR FCLR I S FSET
FSET Flag register SET FSET FSET C D Z S B O I U U I O B S Z D C FSET FSET I S FCLR
INC INCrement INC INC.size B, W R0L R0H dsp:8[sb] dsp:8[fb] A0 A1 U I O B S Z D C INC.W INC.B A0 R0L DEC
INT INTerrupt INT INT #IMM U I O B S Z D C INT #0 BRK,INTO
INTO INTO INTerrupt on Overflow INTO U I O B S Z D C INTO BRK,INT
JCnd JCnd label Jump on Condition JCnd if true then label Cnd PC 127 label PC +128 GEU/C,GTU,EQ/Z,N,LTU/NC,LEU,NE/NZ,PZ PC 126 label PC +129 LE,O,GE,GT,NO,LT U I O B S Z D C JEQ JNE label label BMCnd
JMP JMP(.length)label JuMP S, B, W, A JMP.length label.s PC +2 label PC +9.B PC 127 label PC +128.W PC 32767 label PC +32768.A abs20 U I O B S Z D C JMP label JMPI,JMPS
JMPI JuMP Indirect JMPI JMPI.length W, A R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C JMPI.A JMPI.W A1A0 R0 JMP,JMPS
JMPS JMPS JuMP Special page JMPS #IMM U I O B S Z D C JMPS #20 JMP,JMPI
JSR JSR(.length)label Jump SubRoutine W, A JSR.length label.w PC 32767 label PC +32768.A abs20 U I O B S Z D C JSR.W JSR.A func func JSRI,JSRS
JSRI JSRI.length Jump SubRoutine Indirect W, A JSRI R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C JSRI.A JSRI.W A1A0 R0 JSR,JSRS
JSRS JSRS Jump SubRoutine Special page JSRS #IMM U I O B S Z D C JSRS #18 JSR,JSRI
LDC LoaD Control register LDC LDC, R0L/R0 R0H/R1 R1L/R2 R1H/R3 FB SB SP *1 ISP A0/A0 A1/A1 [A0] [A1] FLG INTBH INTBL dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM R2R0 R3R1 A1A0 U I O B S Z D C LDC LDC R0,SB A0,FB POPC,PUSHC,STC,LDINTB
LDCTX LDCTX,abs20 LoaD ConTeXt LDCTX FB SB A1 A0 R3 R2 R1 R0 U I O B S Z D C LDCTX Ram,Rom_TBL STCTX
LDE LDE.size, LoaD from EXtra far data area B, W LDE R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 [A1A0] R2R0 R3R1 A1A0 U I O B S Z D C LDE.W LDE.B [A1A0],R0 Rom_TBL,A0 STE,MOV,XCHG
LDINTB LDINTB LoaD INTB register LDINTB #IMM20 U I O B S Z D C LDINTB #0F0000H LDC,STC,PUSHC,POPC
LDIPL LDIPL LoaD Interrupt Permission Level LDIPL #IMM U I O B S Z D C LDIPL #2
MOV MOV.size (:format), MOVe G, Q, Z, S B, W MOV R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 dsp:8[sp] R2R0 R3R1 A1A0 dsp:8[sp] U I O B S Z D C MOV.B:S MOV.W #0ABH,R0L # 1,R2 LDE,STE,XCHG
G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 dsp:8[sp] R2R0 R3R1 A1A0 dsp:8[sp] Q R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 S R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 Z R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #0 A0 A1
MOVA MOVA, MOVe effective Address MOVA R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C MOVA Ram:16[SB],A0 PUSHA
MOVDir MOVDir, MOVe nibble MOVDir Dir HH HL LH LL Dir HH HL LH LL R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C MOVHH MOVHL R0L,[A0] R0L,[A0]
MUL MUL.size, MULtiple B, W MUL R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C MUL.B A0,R0L MUL.W #3,R0 MUL.B R0L,R1L MUL.W A0,Ram DIV,DIVU,DIVX,MULU
MULU MULtiple Unsigned MULU MULU.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C MULU.B A0,R0L MULU.W #3,R0 MULU.B R0L,R1L MULU.W A0,Ram DIV,DIVU,DIVX,MUL
NEG NEGate NEG NEG.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C NEG.B NEG.W R0L A1 NOT
NOPNOP No OPeration NOP U I O B S Z D C NOP
NOT NOT.size (:format) NOT G, S B, W NOT R0L /R0 R0H /R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C NOT.B NOT.W R0L A1 NEG
OR OR.size (:format), OR G, S B, W OR R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C OR.B Ram:8[SB],R0L OR.B:G A0,R0L OR.B:G R0L,A0 OR.B:S #3,R0L AND,XOR,TST
S G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1
POP POP POP.size (:format) G, S B, W POP R0L /R0 R0H /R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C POP.B POP.W R0L A0 PUSH,POPM,PUSHM
POPC POPC POP Control register POPC FB SB SP *2 ISP FLG INTBH INTBL U I O B S Z D C POPC SB PUSHC,LDC,STC,LDINTB
POPM POPM POP Multiple POPM FB SB A1 A0 R3 R2 R1 R0 R0 R1 R2 R3 A0 A1 SB FB U I O B S Z D C POPM R0,R1,A0,SB,FB POP,PUSH,PUSHM
PUSH PUSH PUSH.size (:format) G, S B, W PUSH R0L /R0 R0H /R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM R2R0 R3R1 A1A0 U I O B S Z D C PUSH.B #5 PUSH.W #100H PUSH.B R0L PUSH.W A0 POP,POPM,PUSHM
PUSHA PUSH effective Address PUSHA PUSHA R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C PUSHA PUSHA Ram:8[FB] Ram:16[SB] MOVA
PUSHC PUSHC PUSH Control register PUSHC FB SB SP *2 ISP FLG INTBH INTBL U I O B S Z D C PUSHC SB POPC,LDC,STC,LDINTB
PUSHM PUSHM PUSH Multiple PUSHM R0 R1 R2 R3 A0 A1 SB FB R0 R1 R2 R3 A0 A1 SB FB U I O B S Z D C PUSHM R0,R1,A0,SB,FB POP,PUSH,POPM
REIT REIT REturn from InTerrupt REIT U I O B S Z D C REIT
RMPA RMPA.size Repeat MultiPle & Addition B, W RMPA Repeat Until U I O B S Z D C RMPA.B
ROLC ROtate to Left with Carry ROLC ROLC.size B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C ROLC.B ROLC.W R0L R0 RORC,ROT,SHA,SHL
RORC RORC.size ROtate to Right with Carry B, W RORC R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C RORC.B RORC.W R0L R0 ROLC,ROT,SHA,SHL
ROT ROTate ROT ROT.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H /3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C ROT.B #1,R0L ROT.B # 1,R0L ROT.W R1H,R2 ROLC,RORC,SHA,SHL
RTS RTS ReTurn from Subroutine RTS U I O B S Z D C RTS
SBB SuBtract with Borrow SBB SBB.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C SBB.B #2,R0L SBB.W A0,R0 SBB.B A0,R0L SBB.B R0L,A0 ADC,ADCF,ADD,SUB
SBJNZ SBJNZ.size,,label SuBtract then Jump on Not Zero B, W SBJNZ if then label R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 #IMM [A0] [A1] dsp:8[a0] PC 126 label PC +129 dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] U I O B S Z D C SBJNZ.W #1,R0,label ADJNZ
SHA SHA.size, SHift Arithmetic B, W, L SHA R0L/R0 R0H/R1 R1L/R2 R1H /3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C SHA.B #3,R0L SHA.B # 3,R0L SHA.L R1H,R2R0 ROLC,RORC,ROT,SHL
SHL SHift Logical SHL SHL.size, B, W, L R0L/R0 R0H/R1 R1L/R2 R1H /3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C SHL.B #3,R0L SHL.B # 3,R0L SHL.L R1H,R2R0 ROLC,RORC,ROT,SHA
SMOVB SMOVB.size String MOVe Backward B, W SMOVB Repeat Repeat Until Until U I O B S Z D C SMOVB.B SMOVF,SSTR
SMOVF SMOVF.size String MOVe Forward B, W SMOVF Repeat Repeat Until Until U I O B S Z D C SMOVF.W SMOVB,SSTR
SSTR SSTR.size String SToRe B, W SSTR Repeat Repeat Until Until U I O B S Z D C SSTR.B SMOVB,SMOVF
STC STC, STore from Control register STC FB SB SP *1 ISP R0L/R0 R0H/R1 R1L/R2 R1H/R3 FLG INTBH INTBL A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 PC R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 U I O B S Z D C STC STC SB,R0 FB,A0 POPC,PUSHC,LDC,LDINTB
STCTX STore ConTeXt STCTX STCTX,abs20 FB SB A1 A0 R3 R2 R1 R0 U I O B S Z D C STCTX Ram,Rom_TBL LDCTX
STE STore to EXtra far data area STE STE.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 [A1A0] U I O B S Z D C STE.B STE.W R0L,[A1A0] R0,10000H[A0] MOV,LDE,XCHG
STNZ STNZ, STore on Not Zero STNZ if then #IMM8R0L R0H dsp:8[sb] dsp:8[fb] A0 A1 U I O B S Z D C STNZ #5,Ram:8[SB] STZ,STZX
STZ STore on Zero STZ STZ, ifthen #IMM8R0L R0H dsp:8[sb] dsp:8[fb] A0 A1 U I O B S Z D C STZ #5,Ram:8[SB] STNZ,STZX
STZX STZX 1,2, STore on Zero extention STZX Ifthen else #IMM8R0L R0H dsp:8[sb] dsp:8[fb] A0 A1 U I O B S Z D C STZX #1,#2,Ram:8[SB] STZ,STNZ
SUB SUB.size (:format), SUBtract G, S B, W SUB R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C SUB.B A0,R0L SUB.B R0L,A0 SUB.B Ram:8[SB],R0L SUB.W #2,[A0] ADC,ADCF,ADD,SBB
S G R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 SP/SP R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1 R0L R0H dsp:8[sb] dsp:8[fb] R0L R0H dsp:8[sb] dsp:8[fb] #IMM A0 A1
TST TeST TST TST.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C TST.B #3,R0L TST.B A0,R0L TST.B R0L,A0 AND,OR,XOR
UND UND UNDefined instruction UND U I O B S Z D C UND
WAIT WAIT WAIT WAIT U I O B S Z D C WAIT
XCHG XCHG.size, exchange B, W XCHG R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 [A1A0] R2R0 R3R1 A1A0 U I O B S Z D C XCHG.B R0L,A0 XCHG.W R0,A1 XCHG.B R0L,[A0] MOV,LDE,STE
XOR exclusive OR XOR XOR.size, B, W R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:16[a0] dsp:16[a1] dsp:16[sb] dsp:20[a0] dsp:20[a1] abs20 #IMM dsp:20[a0] dsp:20[a1] abs20 R2R0 R3R1 A1A0 R2R0 R3R1 A1A0 U I O B S Z D C XOR.B A0,R0L XOR.B R0L,A0 XOR.B #3,R0L XOR.W A0,A1 AND,OR,TST
LDIPL (1) LDIPL #IMM b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 0 1 0 IMM4 2/2 (1) MOV.size:G #IMM, MOV b7 b0 b7 b0 0 1 1 1 0 1 0 SIZE 1 1 0 0 DE ST dsp8 dsp16/ #IMM8 #IMM16.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 3/2 3/2 3/3 4/3 4/3 5/3 5/3 5/3
b7 b0 b7 b0 0 1 1 1 0 1 0 SIZE 1 1 0 0 DEST dsp8 #IMM8 dsp16/ #IMM16.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111
ABS (1) ABS.size b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 1 1 1 1 DEST dsp8 dsp16/.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/3 2/3 2/5 3/5 3/5 4/5 4/5 4/5 ADC (1) ADC.size #IMM, b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 0 1 1 0 DEST dsp8 dsp16/ #IMM8 #IMM16.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An 3/2 3/2 3/4 dsp:8 4/4 dsp:8[sb/fb] dsp:16 dsp:16[sb] 4/4 5/4 5/4 5/4
ADC (2) ADC.size, b7 b0 b7 b0 1 0 1 1 0 0 0 SIZE SRC DEST dsp8 dsp16/ dsp8 dsp16/.size SIZE / SRC/DEST / SRC/DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 An 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 2/3 2/3 2/4 3/4 3/4 4/4 4/4 4/4 dsp:8 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 dsp:8[sb/fb] 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 dsp:16 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 dsp:16[sb] 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4
ADCF (1) ADCF.size b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 1 1 1 0 DEST dsp8 dsp16/.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/1 2/1 2/3 3/3 3/3 4/3 4/3 4/3 ADD (1) ADD.size:G #IMM, b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 0 1 0 0 DEST dsp8 dsp16/ #IMM8 #IMM16.size SIZE DEST DEST.B.W 0 1 R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An 3/2 3/2 3/4 dsp:8 4/4 dsp:8[sb/fb] dsp:16 dsp:16[sb] 4/4 5/4 5/4 5/4
ADD (2) ADD.size:Q#IMM, b7 b0 b7 b0 1 1 0 0 1 0 0 SIZE IMM4 DEST dsp8 dsp16/.size SIZE #IMM IMM4 #IMM IMM4.B 0 0 0000 8 1000.W 1 +1 0001 7 1001 +2 0010 6 1010 +3 0011 5 1011 +4 0100 4 1100 +5 0101 3 1101 +6 0110 2 1110 +7 0111 1 1111 DEST DEST R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/1 2/1 2/3 3/3 3/3 4/3 4/3 4/3
ADD (3) ADD.B:S #IMM8, b7 1 0 0 0 0 DEST b0 #IMM8 dsp8 R0H R0L dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] DEST 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 2/1 dsp:8[sb/fb] 3/3 4/3
(4) ADD.size:G, b7 b0 b7 b0 1 0 1 0 0 0 0 SIZE SRC DEST dsp8 dsp8 dsp16/ dsp16/ ADD.size.B.W SIZE 0 1 An / R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] SRC/DEST 0000 0001 0010 0011 0100 0101 0110 0111 / dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] SRC/DEST 1000 1001 1010 1011 1100 1101 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 An 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 2/3 2/3 2/4 3/4 3/4 4/4 4/4 4/4 dsp:8 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 dsp:8[sb/fb] dsp:16 3/3 4/3 3/3 4/3 3/4 4/4 4/4 5/4 4/4 5/4 5/4 6/4 5/4 6/4 5/4 6/4 dsp:16[sb] 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4
ADD (5) ADD.B:S, R0L/R0H b7 0 0 1 0 0 DEST SRC b0 dsp8 R0L/R0H dsp:8[sb/fb] dsp:8[sb] dsp:8[fb] SRC 0 0 0 1 1 0 1 1 R0L R0H DEST 0 1 1/2 dsp:8[sb/fb] 2/3 3/3 ADD (6) ADD.size:G #IMM, SP b7 b0 b7 b0 0 1 1 1 1 1 0 SIZE 1 1 1 0 1 0 1 1 #IMM8 #IMM16.size.B.W SIZE 0 1 3/2
ADD (7) ADD.size:Q#IMM, SP b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 0 1 1 IMM4 #IMM 0 +1 +2 +3 +4 +5 +6 +7 IMM4 0000 0001 0010 0011 0100 0101 0110 0111 #IMM 8 7 6 5 4 3 2 1 IMM4 1000 1001 1010 1011 1100 1101 1110 1111 2/1
ADJNZ (1) ADJNZ.size #IMM,, label b7 b0 b7 b0 1 1 1 1 1 0 0 SIZE IMM4 DEST dsp8 dsp16/ label dsp8.size.b.w SIZE 0 1 #IMM 0 +1 +2 +3 +4 +5 +6 +7 IMM4 0000 0001 0010 0011 0100 0101 0110 0111 #IMM 8 7 6 5 4 3 2 1 IMM4 1000 1001 1010 1011 1100 1101 1110 1111 An R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] DEST 1000 1001 1010 1011 1100 1101 1110 1111 An 3/3 3/3 3/5 dsp:8 4/5 dsp:8[sb/fb] dsp:16 4/5 5/5 dsp:16[sb] 5/5 5/5
AND (1) AND.size:G #IMM, b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 0 0 1 0 DEST dsp8 dsp16/ #IMM8 #IMM16.size.B.W SIZE 0 1 An R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] DEST 1000 1001 1010 1011 1100 1101 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 3/2 3/2 3/4 4/4 4/4 5/4 5/4 5/4 (2) AND.B:S #IMM8, b7 b0 1 0 0 1 0 DEST #IMM8 dsp8 AND R0H R0L dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] DEST 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 2/1 dsp:8[sb/fb] 3/3 4/3
AND (3) AND.size:G, b7 b0 b7 b0 1 0 0 1 0 0 0 SIZE SRC DEST dsp8 dsp8 dsp16/ dsp16/.size.b.w SIZE 0 1 An / R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] SRC/DEST 0000 0001 0010 0011 0100 0101 0110 0111 / dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] SRC/DEST 1000 1001 1010 1011 1100 1101 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 2/3 2/3 2/4 3/4 3/4 4/4 4/4 4/4 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4
(4) AND.B:S, R0L/R0H b7 b0 0 0 0 1 0 DEST SRC dsp8 AND R0L/R0H dsp:8[sb/fb] dsp:8[sb] dsp:8[fb] SRC 0 0 0 1 1 0 1 1 R0L R0H DEST 0 1 1/2 dsp:8[sb/fb] 2/3 3/3
BAND (1) BAND b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 1 0 0 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 base:8 bit,base:8 bit, bit,an [SB/FB] 3/3 3/3 2/7 3/7 3/4 base:16 bit,base:16 bit,base:16 [SB] 4/7 4/4 4/4 BCLR (1) BCLR:G b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 0 0 0 DE ST dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 base:8 bit,base:8 [SB/FB] base:16 DEST base:8[a0] 1000 base:8[a1] 1001 bit,base:8[sb] 1010 bit,base:8[fb] 1011 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/2 bit,an 3/2 2/6 base:8 bit,base:8 base:16 [SB/FB] 3/6 3/3 4/6 bit,base:16 bit,base:16 [SB] 4/3 4/3
(2) BCLR:S bit, base:11[sb] b7 b0 0 1 0 0 0 BIT dsp8 BCLR 2/3
BMCnd (1) BMCnd b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 0 1 0 DEST dsp8 dsp16 CND DEST DEST bit, bit,r0 bit,r1 bit,r2 0000 0001 0010 base:8 bit,base:8 base:8[a0] base:8[a1] bit,base:8[sb] 1000 1001 1010 bit,r3 0011 [SB/FB] bit,base:8[fb] 1011 bit,an bit,a0 bit,a1 0100 0101 base:16 base:16[a0] base:16[a1] 1100 1101 [A0] [A1] 0110 0111 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 Cnd CND Cnd CND GEU/C GTU EQ/Z N LE O GE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 LTU/NC LEU NE/NZ PZ GT NO LT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 bit, bit,an base:8 bit,base:8 [SB/FB] base:16 bit,base:16 bit,base:16 [SB] 4/6 4/6 3/10 4/10 4/7 5/10 5/7 5/7
(2) BMCnd C b7 b0 b7 b0 0 1 1 1 1 1 0 1 1 1 0 1 CND BMCnd Cnd GEU/C GTU EQ/Z N LTU/NC LEU NE/NZ CND 0000 0001 0010 0011 0100 0101 0110 Cnd PZ LE O GE GT NO LT CND 0111 1000 1001 1010 1100 1101 1110 2/1 BNAND (1) BNAND b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 1 0 1 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 base:8 bit,base:8 base:16 bit,base:16 bit, bit,an bit,base:16 [SB/FB] [SB] 3/3 3/3 2/7 3/7 3/4 4/7 4/4 4/4
BNOR (1) BNOR b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 1 1 1 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 3/7 bit,base:8 [SB/FB] 3/4 base:16 bit,base:16 bit,base:16 [SB] 4/7 4/4 4/4 BNOT (1) BNOT:G b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 0 1 0 DE ST dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 base:8 bit,base:8 [SB/FB] base:16 DEST base:8[a0] 1000 base:8[a1] 1001 bit,base:8[sb] 1010 bit,base:8[fb] 1011 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 base:8 bit,base:8 base:16 bit,base:16 bit, bit,an bit,base:16 [SB/FB] [SB] 3/2 3/2 2/6 3/6 3/3 4/6 4/3 4/3
(2) BNOT:S bit, base:11[sb] b7 b0 0 1 0 1 0 BIT dsp8 BNOT 2/3 BNTST (1) BNTST b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 0 1 1 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 3/7 bit,base:8 [SB/FB] 3/4 base:16 bit,base:16 bit,base:16 [SB] 4/7 4/4 4/4
BNXOR (1) BNXOR b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 1 0 1 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 bit,base:8 base:16 [SB/FB] 3/7 3/4 4/7 bit,base:16 bit,base:16 [SB] 4/4 4/4 BOR (1) BOR b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 1 1 0 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 bit,base:8 base:16 bit,base:16 bit,base:16 [SB/FB] [SB] 3/7 3/4 4/7 4/4 4/4
(1) BRK b7 b0 0 0 0 0 0 0 0 0 BRK 1/27 BSET (1) BSET:G b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 0 0 1 DEST dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 base:8 bit,base:8 [SB/FB] base:16 DEST base:8[a0] 1000 base:8[a1] 1001 bit,base:8[sb] 1010 bit,base:8[fb] 1011 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/2 bit,an 3/2 2/6 base:8 3/6 bit,base:8 [SB/FB] 3/3 base:16 bit,base:16 bit,base:16 [SB] 4/6 4/3 4/3
BSET (2) BSET:S bit, base:11[sb] b7 b0 0 1 0 0 1 BIT dsp8 2/3 BTST (1) BTST:G b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 0 1 1 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/2 bit,an 3/2 2/6 base:8 3/6 bit,base:8 [SB/FB] 3/3 base:16 bit,base:16 bit,base:16 [SB] 4/6 4/3 4/3
(2) BTST:S bit, base:11[sb] b7 b0 0 1 0 1 1 BIT dsp8 BTST 2/3 BTSTC (1) BTSTC b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 0 0 0 DE ST dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 base:8 bit,base:8 [SB/FB] base:16 DEST base:8[a0] 1000 base:8[a1] 1001 bit,base:8[sb] 1010 bit,base:8[fb] 1011 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 3/7 bit,base:8 [SB/FB] 3/4 base:16 4/7 bit,base:16 bit,base:16 [SB] 4/4 4/4
BTSTS (1) BTSTS b7 b0 b7 b0 0 1 1 1 1 1 1 0 0 0 0 1 DE ST dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 base:8 bit,base:8 [SB/FB] base:16 DEST base:8[a0] 1000 base:8[a1] 1001 bit,base:8[sb] 1010 bit,base:8[fb] 1011 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 bit, 3/3 bit,an 3/3 2/7 base:8 3/7 bit,base:8 [SB/FB] 3/4 base:16 bit,base:16 bit,base:16 [SB] 4/7 4/4 4/4 BXOR (1) BXOR b7 b0 b7 b0 0 1 1 1 1 1 1 0 1 1 0 0 SRC dsp8 dsp16 bit, bit,an bit,r0 bit,r1 bit,r2 bit,r3 bit,a0 bit,a1 [A0] [A1] SRC 0000 0001 0010 0011 0100 0101 0110 0111 SRC base:8 base:8[a0] 1000 base:8[a1] 1001 bit,base:8 [SB/FB] bit,base:8[sb] bit,base:8[fb] 1010 1011 base:16 base:16[a0] 1100 base:16[a1] 1101 bit,base:16[sb] bit,base:16[sb] 1110 bit,base:16 bit,base:16 1111 base:8 bit,base:8 base:16 bit,base:16 bit, bit,an bit,base:16 [SB/FB] [SB] 3/3 3/3 2/7 3/7 3/4 4/7 4/4 4/4
CMP (1) CMP.size:G #IMM, b7 b0 b7 b0 0 1 1 1 0 1 1 SIZE 1 0 0 0 DEST dsp8 dsp16/ #IMM8 #IMM16.size.B.W SIZE 0 1 An R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] DEST 0000 0001 0010 0011 0100 0101 0110 0111 dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] DEST 1000 1001 1010 1011 1100 1101 1110 1111 An 3/2 3/2 3/4 dsp:8 4/4 dsp:8[sb/fb] dsp:16 dsp:16[sb] 4/4 5/4 5/4 5/4
CMP (2) CMP.size:Q#IMM, b7 b0 b7 b0 1 1 0 1 0 0 0 SIZE IMM4 DEST dsp8 dsp16/.size SIZE #IMM IMM4 #IMM IMM4.B 0 0 0000 8 1000.W 1 +1 0001 7 1001 +2 0010 6 1010 +3 0011 5 1011 +4 0100 4 1100 +5 0101 3 1101 +6 0110 2 1110 +7 0111 1 1111 DEST DEST R0L/R0 R0H/R1 R1L/R2 R1H/R3 0000 0001 0010 0011 dsp:8 dsp:8[sb/fb] dsp:8[a0] dsp:8[a1] dsp:8[sb] dsp:8[fb] 1000 1001 1010 1011 An A0 A1 0100 0101 dsp:16 dsp:16[a0] dsp:16[a1] 1100 1101 [A0] [A1] 0110 0111 dsp:16[sb] dsp:16[sb] 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/1 2/1 2/3 3/3 3/3 4/3 4/3 4/3
(3) CMP.B:S #IMM8, b7 b0 1 1 1 0 0 DEST #IMM8 dsp8 CMP R0H R0L dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] DEST 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 2/1 dsp:8[sb/fb] 3/3 4/3
CMP (4) CMP.size:G, b7 b0 b7 b0 1 1 0 0 0 0 0 SIZE SRC DEST dsp8 dsp16/ dsp8 dsp16/.size.b.w SIZE 0 1 An / R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0 A1 [A0] [A1] SRC/DEST 0000 0001 0010 0011 0100 0101 0110 0111 / dsp:8[a0] dsp:8 dsp:8[a1] dsp:8[sb] dsp:8[sb/fb] dsp:8[fb] dsp:16[a0] dsp:16 dsp:16[a1] dsp:16[sb] dsp:16[sb] SRC/DEST 1000 1001 1010 1011 1100 1101 1110 1111 An dsp:8 dsp:8[sb/fb] dsp:16 dsp:16[sb] 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 An 2/2 2/2 2/3 3/3 3/3 4/3 4/3 4/3 2/3 2/3 2/4 3/4 3/4 4/4 4/4 4/4 dsp:8 3/3 3/3 3/4 4/4 4/4 5/4 5/4 5/4 dsp:8[sb/fb] dsp:16 3/3 4/3 3/3 4/3 3/4 4/4 4/4 5/4 4/4 5/4 5/4 6/4 5/4 6/4 5/4 6/4 dsp:16[sb] 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4 4/3 4/3 4/4 5/4 5/4 6/4 6/4 6/4