CPU ICT mizutani@ic.daito.ac.jp 2014
SI: Systèm International d Unités SI SI 10 1 da 10 1 d 10 2 h 10 2 c 10 3 k 10 3 m 10 6 M 10 6 µ 10 9 G 10 9 n 10 12 T 10 12 p 10 15 P 10 15 f 10 18 E 10 18 a 10 21 Z 10 21 z 10 24 Y 10 24 y c = 2.998 10 8 [m/sec], Avogadro N A = 6.022 10 23 [mol 1 ], 1 9.46 10 15 [m], au = 1.50 10 11 [m], 6378.1[km], 2.818 10 15 [m], e = 1.602 10 19 [C], m e = 9.109 10 31 [kg], Cu 2.5nm, 10 80
RAM Random Access Memory 512MB 4GB HDD Hard Disk Drive 256GB 5TB SSD Solid State Drive 64GB 1TB 500GB 2TB CD 700MB DVD 4.7GB Blu-ray 25GB SD 1GB 64GB, USB 1GB 128GB iphone 16GB 64GB
4 32 DNA 800MB 10TB Gordon Bell 80 80 B 1 8GB 3 4GB YouTube 1 0.6GB(HD) 2GB(FHD) YouTube 60 /1 1 40 Google 20 B/1 1/2008 NSA 5 B 7/2013
2 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 10 [123] 10 = 1 10 2 + 2 10 1 + 3 10 0 2 0 1 2 2 [b n b n 1... b 1 b 0 ] 2, b i {0, 1} 10 [b n b n 1... b 1 b 0 ] 2 = [b n 2 n + b n 1 2 n 1 + + b 1 2 1 + b 0 2 0 ] 10 2 0 +) 0 0 0 +) 1 1 1 +) 0 1 1 +) 1 10 0 1 XOR 0 ) 0 0 0 ) 1 0 1 ) 0 0 1 ) 1 1
2 [0] 2 + [0] 2 = [0] 2 [0] 2 [0] 2 = [0] 2 [1] 2 + [0] 2 = [1] 2 [1] 2 [0] 2 = [0] 2 [0] 2 + [1] 2 = [1] 2 [0] 2 [1] 2 = [0] 2 [1] 2 + [1] 2 = [10] 2 [1] 2 [1] 2 = [1] 2 Table: 2 [11] 2 + [01] 2 = [100] 2 = [4] 10,[1001] 2 + [0110] 2 = [1111] 2 = [15] 10 1 1 ) 1 0 0 0 1 1 1 1 1 [11] 2 [10] 2 = [111] 2 = [6] 10
bit { 1 = 0 1bit: 1 [0] [1] 2 2 2 bits [00],[01],[10],[11] 4 n bits [ b n 1... b 1 b }{{} 0 ] 2 n n 0 1 Q1 A-Za-z 52 1 Q2 1 1
bit signal 2 0 1 1 T 0 T T Figure: 5 10010 δt T 5 5( T + δt)
d {0, 1,..., d 1} s s = s 1 s 2... s i..., s i {0, 1,... d 1} 2 n d > 2 n 1 n n 1 A Z,a z 52 1 64 = 2 6 > 52 > 2 5 = 32 6 A 000000 a 011011 B 000001 b 011100.. Z 011010 z 110100
bit Byte 8 bits=1 Byte 1 B 1KB = 2 10 = 1024B 0-1 8 1Byte 2 8 [b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ] 2, b i [0, 1} [00000000] 2 = [0] 10 [11111111] 2 = [255] 10 256 Shift_JIS 2Byte 2 16 = 65536 ASCII 128 7bit UTF IP 64KB (MTU) MTU IP IP
Figure:
CPU [sec] 1 Hz 1 CPU instruction IF ID EX WB 4 1 IPC=1
CPU Kernighan, p47-59 http://kernighan.com/toysim.html CPU Fetch( ) Decode Exec WiteBack( ) CPU accumulator
CPU 1CPU http://japan.intel.com/contents/museum/mpuworks/page_2.html CPU MIPS(Million Instructions Per Second)= IPC 10 6 FLOPS(Floating-point Operations Per Second) SPEC(Standard Performance Evaluation Corporation)
CPU vs CPU 8 intel Xeon E5 3GHz 1 1 3GHz = 0.33 10 9 [sec] 0.33 c 1 3 10 9 [sec] = 10 1 [m] 10cm Xeon E5 DDR3 ECC 200MHz 2 1, 866MHz 8B =64 15[GB/sec] 3 CPU 20 50 cache CPU CPU CPU CPU L1,L2,L3 Xeon E5 25MB L3
Moore 2 The complexity for minimum component costs has in- creased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least ten years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65000. I believe that such a large circuit can be built on a single wafer. Cramming More Components onto Integrated Circuits Moore? 22nm 7 5nm 2020