- - wada@ie.u-ryukyu.ac.jp http://bw-www.ie.u-ryukyu.ac.jp/~wada http://www.magnadesignnet.com LSI SRAM 3 Pentium Cache 3 LSI H/W Cache LSI
YMCA OUTLINE 1 2
2002 718 LSI
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Organization Chief Scientist Stock Holders Board Members President CEO Inspector Snap photo Hardware System Marketing Finance New HQ & Design Center Development Center Discussion in the garden Okinawa, Japan Magna Design Net, Inc. 1831-1 Oroku Naha-City, Okinawa, Japan Post No. 901-0152 Industrial Support Center 3F (Near the Naha International Airport)
President & CEO, Dynamite Matsuo Designed & managed a lot of memory LSIs. Worked in Silicon Valley (USA) for LSIs marketing and design-win. General Manager, Yasushi Wauke Designed many system on chip LSI. Managed consulting design group at EDA (USA) tool vendor. Chief Scientist, Fire Tom Wada Designed many memories & system LSIs. MS of Stanford Univ. (USA) Doctor of eng., Professor at Univ. of the Ryukyus. R&D Director, Shuji Murakami Designed many digital broadband LSIs. Doctor of eng., MS of UCLA(USA) under Prof. Samueli (Broadcom/USA) Hardware Sinea Manger, Kunio Morimoto Designed special system LSIs for big Net- Work Systems. Managed engineering group for broadband LSI at EDA(USA) tool vendor Hardware Manager, Hajime Touma Developed special software for space project. Engineering support of LSI design tool systems at EDA(USA) tool vender. Business Manager, Sada Sakaguchi Designed and produced memory LSIs. Worked for LSI marketing for network companies in Europe (EU). Hardware Manager, Hiro Mizutani Developed digital cable and satellite digital LSIs. Specialist of the design tools especially SPW and LSI design WS. Hardware Manager, Mitsuru Hori Developed digital cable and satellite digital LSIs and DSP. Worked with USA company for DIRECT TV`s LSI. Hardware Engineer, Hirokazu Asato Engineering support of LSI design tool systems and FPGA compiler at EDA(USA) tool vender. Univ. of the Ryukyus --- Already jointed Univ. of Kyusyu LSI research center Planning joint development near soon.
SPW SPW Design Design Brand New algorism for Broadband LSIs RTL RTL Design Design IP Core (RTL) Product 1 LSI LSI Making Making FPGA FPGA Prototype Prototype LSI Product 2 System System Product 3 LSI 13 OFDM 1 OFDM TV LSIOFDM LAN LSI IEEE802.11a, 5Ghz LANOFDM
ADC OFDM LSI TV TV ISDB-T HDTV 1ch / SDTV 2ch + Audio 1ch / etc. Mode1 Mode3 TMCC
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14 LSI Stanford R&D BroadComSamueli UCLA S/W
2000828 X - - - EDA PC DSP LSI
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Sleeping on the problem.
HAPPY HAPPY TV
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Fermi G.P.Yeh G.P.Yeh What is the most fun? FUN
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