UG431, XtremeDSP DSP48A for Spartan-3A DSP FPGAs
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- かおり あさま
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1 Spartan-3A DSP FPGA XtremeDSP DSPA (v12)
2 Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WAANTY OF ANY KIND XILINX MAKES NO OTHE WAANTIES, WHETHE EXPESS, IMPLIED, O STATUTOY, EGADING THE DOCUMENTATION, INCLUDING ANY WAANTIES OF MECHANTABILITY, FITNESS FO A PATICULA PUPOSE, O NONINFINGEMENT OF THID-PATY IGHTS IN NO EVENT WILL XILINX BE LIABLE FO ANY CONSEQUENTIAL, INDIECT, EXEMPLAY, SPECIAL, O INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA O LOST POFITS, AISING FOM YOU USE OF THE DOCUMENTATION 2007 Xilinx, Inc All rights reserved XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc All other trademarks are the property of their respective owners 2007/04/ /05/ /11/ : XC3SD00A DSPA 1-2 : XC3SD3400A DSPA 1-2 : B BCIN 1-5 : : B1 EN CEB 1-8 : / 1 DSP 1 : VHDL Verilog japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
3 : XtremeDSP Spartan-3A DSP DSPA 13 DSPA 16 OPMODE 19 DSPA 19 VHDL Verilog 20 DSPA 21 DSPE A B C D P 24 OPMODE X Z 27 / 30 / / FI 32 FI 32 FI 33 FI DSPA x x 38 x MACC Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 3
4 : DSPA 47 FI 47 FI japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
5 1 : XtremeDSP 1-1 : XC3SD00A FPGA DSPA : XC3SD3400A FPGA DSPA : DSPA : DSPA : DSPA : DSPA : A : B D : C : P : OPMODE : 2 MEG : / : x 35 x : FI : : DSPA FI : FI : DSPA 35x : DSPA 35 x : x : x MACC ( N ) : x MACC ( N+1 ) : x MACC ( ) : : 44 2 : DSPA 2-1 : DSPA : FI 2-3 : FI : FI : : : : : 52 Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 5
6 6 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
7 1 : XtremeDSP 1-1 : DSPA : DSPA : OPMODE : OPMODE X : OPMODE Z : OPMODE[7:4] : DSPA : 43 2 : DSPA 2-1 : DSPA : DSPA 47 Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 7
8 8 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
9 Spartan -3A DSP FPGA XtremeDSP DSPA 1 XtremeDSP DSPA 2 DSPA FI japanxilinxcom/literature japanxilinxcom/support Courier Courier ( ) speed grade: ngdbuild design_name ngdbuild design_name Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 9
10 : / [ ] { } bus[7:0] GUI 1 PA ngdbuild [option_name] design_name [File] [Open] lowpwr ={on off} lowpwr ={on off} IOB #1: Name = QOUT IOB #2: Name = CLKIN allow block block_name loc1 loc2 locn; (UL) 1 Virtex-II Platform FPGA japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
11 1 XtremeDSP XtremeDSP DSP ( ) DSPA DSPA Spartan -3A DSP FPGA XtremeDSP DSPA 1 DSP DSP Spartan-3A DSP DSPA (MACC) / DSPA FPGA DSP Spartan-3A DSP DSPA DSP FPGA DSP FPGA Spartan-3A DSP DSPA DSPA DSPE A B C D P FI DSPA DSPA FPGA DSP DSPA Virtex -4 DSP ( UG073 : Virtex -4 FPGA XtremeDSP ) Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 11
12 1 : XtremeDSP DSP FPGA DSPA x 2 / / DSP 1 XtremeDSP DSP 1 C D 2 XtremeDSP Spartan-3A DSP DSP DSP 1 DSP Spartan-3A DSP 4 DSPA / / / DSPA DSPA DSP 1 (B ) DSPA (P ) FI ( ) 34 DSPA 2 x / ( ) DSPA B P 2 C 12 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
13 Spartan-3A DSP DSPA I/O DSPA ISE DSPA XST DSPA COE Generator DSP System Generator AccelDSP Spartan-3A DSP DSPA DSP Spartan-3A DSP DSPA Spartan-3A DSP DSPA 1-1 Spartan-3A DSP DSPA Spartan-3A DSP DSPA 1-1 XC3SD00A FPGA DSPA 1-2 XC3SD3400A FPGA DSPA 1-1 : DSPA DSPA XC3SD00A 84 4 XC3SD3400A Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 13
14 1 : XtremeDSP X0Y25 X1Y25 X2Y25 X3Y25 X4Y25 X0Y24 X1Y24 X2Y24 X3Y24 X4Y24 X0Y14 X4Y14 X0Y13 X4Y13 X0Y12 X4Y12 X0Y11 X4Y11 X0Y1 X1Y1 X2Y1 X3Y1 X4Y1 X0Y0 X1Y0 X2Y0 X3Y0 X4Y0 Notes: 1 Gray positions are populated with DSPAs 2 Clear positions do not contain DSPAs DSPA carry chains are also broken in these positions There are continuous carry chains from X0Y0 to X0Y11, and then from X0Y14 to X0Y25 and from X4Y0 to X4Y11 and from X4Y14 to X4Y : XC3SD00A FPGA DSPA 14 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
15 Spartan-3A DSP DSPA X0Y25 X1Y25 X2Y25 X3Y25 X4Y25 X0Y24 X0Y14 X0Y13 X0Y12 X0Y11 X1Y24 X2Y24 X3Y24 X4Y24 X4Y14 X4Y13 X4Y12 X4Y11 X0Y1 X1Y1 X2Y1 X3Y1 X4Y1 X0Y0 X1Y0 X2Y0 X3Y0 X4Y0 Notes: 1 Gray positions are populated with DSPAs 2 Clear positions do not contain DSPAs DSPA carry chains are also broken in these positions There are continuous carry chains from X0Y0 to X0Y11, and then from X0Y14 to X0Y25 and from X4Y0 to X4Y11 and from X4Y14 to X4Y : XC3SD3400A FPGA DSPA ug431_ch1_02_ Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 15
16 1 : XtremeDSP DSPA 1-3 DSPA A[17:0] B[17:0] D[17:0] C[47:0] BCOUT[17:0] PCOUT[47:0] P[47:0] CLK CAYOUT CAYIN 8 OPMODE[7:0] STA STB STM STP STC STD STCAYIN STOPMODE DSPA CEA CEB CEM CEP CEC CED CECAYIN CEOPMODE PCIN[47:0] UG431_c1_01_ : DSPA 1-2 : DSPA 1-2 DSPA A / (OPMODE[3:0] ) B / / (OPMODE[4] ) DSPA UNISIM DSPA BCOUT BCOUT BCIN B_INPUT C / 16 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
17 Spartan-3A DSP DSPA 1-2 : DSPA ( ) D / CAYIN 1 / DSPA CAYOUT P 1 CAYOUT 1 / DSPA CAYIN CLK 1 DSPA OPMODE 8 DSPA ( 1-7 OPMODE ) / STA 1 A High : A0EG = 1 A1EG = 1 0 STTYPE STB 1 B High : B0EG = 1 B1EG = 1 0 STTYPE STC 1 C (CEG=1) High 0 STTYPE STD 1 D (DEG=1) High 0 STTYPE STM 1 (MEG=1) High 0 STTYPE STP 1 P (PEG=1) High 0 STTYPE STCAYIN 1 (CAYINEG =1) High 0 STTYPE STOPMODE 1 OPMODE (OPMODEEG=1) High 0 STTYPE CEA 1 A High : A0EG = 1 A1EG = 1 0 A0EG = 1 A1EG = 1 A0EG = 0 A1EG = 0 0 Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 17
18 1 : XtremeDSP 1-2 : DSPA ( ) CEB 1 B High : B0EG = 1 B1EG = 1 0 B0EG = 1 B1EG = 1 B0EG = 0 B1EG = 0 0 CEC 1 C (CEG=1) High CEG=1 1 CEG=0 0 CED 1 D (DEG=1) High DEG=1 1 DEG=0 0 CEM 1 (MEG=1) High MEG=1 1 MEG=0 0 CEP 1 (PEG=1) High PEG=1 1 PEG=0 0 CECAYIN 1 (CAYINEG=1) High CAYINEG=1 1 CAYINEG=0 0 CEOPMODE 1 OPMODE (OPMODEEG=1) High OPMODEEG=1 1 OPMODEEG=0 0 PCIN P DSPA PCOUT 0 BCIN B DSPA BCOUT 0 UNISIM BCOUT UNISIM B BCOUT BCIN B_INPUT PCOUT P DSPA PCIN BCOUT B DSPA B japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
19 Spartan-3A DSP DSPA OPMODE 1-3 : OPMODE 1-3 OPMODE / X OPMODE[1:0] 0 0 ( / ) 1 2 P ( ) 3 D B A Z OPMODE[3:2] OPMODE[4] OPMODE[5] OPMODE[6] OPMODE[7] 0 0 ( / P ) 1 PCIN 2 P ( ) 3 C / 0 B 1 B D CAYINSEL = OPMODE5 0 / 1 / 0 / 1 / / DSPA DSPA B_INPUT STTYPE CAYINSEL A0EG A1EG B0EG B1EG 0 A B A0EG 0 ( ) A1EG 1 ( ) B0EG 0 ( ) B1EG 1 ( ) A B C D P CEG DEG MEG PEG 0 1 (MEG 1-12 ) / (PEG 1-10 ) GEG C ( 1-9 ) CEG DEG MEG PEG 1 ( ) Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 19
20 1 : XtremeDSP CAYINEG OPMODEEG CAYINSEL OPMODEEG 1-13 CAYINEG CAYINEG OPMODEEG 1 ( ) CAYINSEL / CAYIN ( DSPA CAYOUT ) OPMODE[5] FPGA CAYIN OPMODE5 CAYINSEL CAYIN B_INPUT B ( : DIEDCT) ( : CASCADE) DSPA B B DSPA BCOUT CASCADE DIECT STTYPE DSPA ASYNC SYNC SYNC STTYPE SYNC VHDL Verilog DSPA VHDL Verilog ISE ISE [Edit] [Language Templates] [VHDL Verilog] [Device Primtive Instantiation] [Arithmetic Functions] [Spartan-3A DSP] [DSP BLock (DSPA)] 20 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
21 DSPA DSPA DSPA DSPA ( 1-1 ) DSPA 4 AM 1 DSPA Spartan-3A DSP (XC3SD00A) 4 Spartan-3A DSP (XC3SD3400A) 5 AM Virtex-II Virtex-II Pro Spartan-3A DSP DSPA AM DSPA Block AM Block AM DSPA DSPA ug431_ch1_03_ : DSPA 1-5 DSPA DSPA HDL UCF ( ) Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 21
22 1 : XtremeDSP BCOUT CAYOUT PCOUT D EG D:A:B Concatenated Carry Cascade D Pre-Adder B A B0 EG A0 EG +/- B1 EG + A1 EG M EG 36 0 X +/- + Post-Adder/ Subtracter P EG P C C EG Dedicated C-Port 0 Z opmode[6] opmode[4] opmode[5] opmode[1:0] opmode[3:2] opmode[7] BCIN PCIN CAYIN UG431_c1_03_ : DSPA : 1 A B D D[11:0] A[17:0] B[17:0] 2 X Z P Z X P P 5 6 C - C DSPA 1 C 2 DSP Virtex DSP C 7 SUBTACT / Z (X + CAYIN) 8 B / D 9 (B D) 2 22 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
23 DSPE DSPE DSPA x 2 (X Z ) 2 2 / DSPA 1 2 DSP A B MHz / 1-1 / X Z CAYIN CAYIN X Z =(Z±(X+CAYIN)) A B C X 36 / = C ± (A x B + CAYIN) B D / A C = C ± (A x (D ± B) + CAYIN) DSPA 8 OPMODE / 2 B OPMODE / / 36 / 36 ( ) OPMODE CAYINSEL CAYIN / 1-5 op- Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 23
24 1 : XtremeDSP CAYOUT C P PCIN Zero Z P D B A D:A:B concat P Zero X OPMODE, CAYIN Controls Behavior OPMODE Controls Behavior CAYIN ug431_ch1_04_ : DSPA A B C D P DSPA DSP DSPA 3 (A B D) (C) 1 DSPA (P) DSPA (B ) (P ) DSPA B DSPA B_INPUT DSPA CAYIN CAYOUT DSPA MACC PCIN DSPA Z MUX (OPMODE 3:2) FI MAC ( ) D B / / OPMODE[4] 1 A B x 2 D A B X C Z ( ) / M japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
25 A B C D P A B C P A A0 EG 0 1 A1 EG 0 A Input to Multiplier D Q D Q 1 EN EN CLK ST CLK ST CEA STA ug431_c1_06_ : A D D EG D Q CED EN STD ST Pre-adder/subtracter ± B BCIN B0 EG B1 EG D Q EN B Input to Multiplier D Q OPMODE[4] ST EN ST CEB STB ug431_c1_07_ : B D Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 25
26 1 : XtremeDSP C CEC C EG D Q EN To Z Multiplexer CLK ST STC ug431_c1_08_ : C From Post-Adder/ Subtracter Output P CEP P EG D Q EN DSPA Slice Output ST STP ug431_c1_09_ : P : OPMODE OPMODE OPMODE OPMODE ( ) ( ) OPMODE STO OPMODE CEO 1-11 OPMODE OPMODE 8 D Q 8 To the X and Z Multiplexers control for pre- and post-adder/subtracters and Carry Input Select Logic CEO EN STO ST 1-11 : OPMODE ug431_c1_10_ japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
27 A B C D P 2 DSPA / MACC MSB ( ) 0 36 / X 1-12 (MEG) 1 D B A ± 36 Optional MEG 36 To X mux input ug431_c1_11_ X Z 1-12 : 2 MEG OPMODE ( DSPA ) OPMODE ( 1-11 ) OPMODE 2 (X Y ) / 3 X / 1-6 OPMODE[7:4] Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 27
28 1 : XtremeDSP 1-4 : OPMODE X OPMODE Z OPMODE[3:2] X OPMODE[1:0] / X XX 00 0 ( ) XX 01 XX 10 P XX 11 B[17:0] A[17:0] D[11:0] 1-5 : OPMODE Z OPMODE Z OPMODE[3:2] X OPMODE[1:0] / Z 00 XX 0 ( ) 01 XX PCIN 10 XX P 11 XX C 1-6 : OPMODE[7:4] OPMODE OPMODE[7] OPMODE[6] OPMODE[5] OPMODE[4] / 1 = / 1 = CAYIN B 1 = / 2 / 0 (36 ) B D A C ( ) DSPA P ( ) P ( ) P : japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
29 A B C D P 1-7 : DSPA 1-7 DSPA OPMODE[7:0] OPMODE / / CAYIN / Z X CAYINSEL CAYIN 0 0/1 0/1 0/ CAYIN 0 CAYIN 1 0/1 0/1 0/ CAYIN 0 + OPMODE<5> 0 0/1 0/1 0/ OPMODE[5] 0 OPMODE<5> 1 0/1 0/1 0/ OPMODE[5] P 0/1 0/1 0/1 0/ /1 ±(P + CAYIN) D:A:B 0/1 0/1 0/ /1 ± (D:A:B + CAYIN) D:A:B ( ) 0/1 0/1 0/ /1 ± (D:A:(D ±B) + CAYIN) 0/1 0/1 0/ /1 ±(A B + CAYIN) - 0/1 0 0/ /1 ±(A (D + B) + CAYIN) - 0/1 1 0/ /1 ± (A (D B) + CAYIN) P 0/1 0/1 0/1 0/ /1 PCIN ±CIN P 0/1 0/1 0/1 0/ /1 PCIN ±(P + CAYIN) P 0/1 0/1 0/ /1 PCIN ±(D:A:B + CAYIN) P ( ) 0/1 0/1 0/ /1 PCIN ± (D:A:(D ± B) + CAYIN P 0/1 0/1 0/ /1 PCIN ±(A B + CAYIN) - 0/1 0 0/ /1 PCIN ± (A (D + B) + CAYIN) - 0/1 1 0/ /1 PCIN ± (A (D B) + CAYIN) 0/1 0/1 0/1 0/ /1 P ± CAYIN 0/1 0/1 0/1 0/ /1 P ± (P + CAYIN) 0/1 0/1 0/ /1 P ± (D:A:B + CAYIN) ( ) 0/1 0/1 0/ /1 P ± (D:A:(D ± B) + CAYIN) - 0/1 0/1 0/ /1 P ± (A B + CAYIN) - 0/1 0 0/ /1 P ± (A (D + B) + CAYIN) - 0/1 1 0/ /1 P ± (A (D B) + CAYIN) C 0/1 0/1 0/1 0/ /1 C ± CAYIN 0/1 0/1 0/1 0/ /1 C ± (P + CAYIN) 0/1 0/1 0/ /1 C ± (D:A:B + CAYIN) - 0/1 0/1 0/ /1 C ± (A B + CAYIN) C - 0/1 0 0/ /1 C ± (A (D + B) + CAYIN) C - 0/1 1 0/ /1 C ± (A (D B) + CAYIN) Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 29
30 1 : XtremeDSP 1-7 : DSPA ( ) OPMODE[7:0] OPMODE / / CAYIN / Z X CAYINSEL ( ) 0/1 0/1 0/ /1 C ± (D:A:(D ± B) + CAYIN) : 1 CAYIN = CAYIN CAY SEL DSPA OPMODE[5] / / OPMODE[6] B D OPMODE[6] (OPMODE[6] = 1 ) 3 / / / / OPMODE OPMODE[3:0] / X Z OPMODE ± OPMODE[7] (OPMODE[7] = 1 ) X CAYIN (CAYSELECT OPMODE[5]) Z CAYIN OPMODE[5] CAYIN 1-13 X Z X Z OPMODE CAYINSEL (CAYIN) 30 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
31 CAYIN OPMODE[5] D Q Carry Input (CIN) to Post-Adder/Subtracter STCAYIN CE CLK ST UG431_c1_12_ : / 1-13 CAYINSEL 2 CAYIN (CAYINSEL 0 ) DSPA 2 OPMODE[5] DSPA MEG CAYINEG 1-14 x 35 x 35 0,B[16:0] 17 B 0 2 AU = A[34:17] x BU = B[34:17] AL = 0,A[16:0] BL = 0,B[16:0] Sign Extend 36 Bits of '0' BL * AL = 34 bits [33:17] [16:0] Sign Extend Bits of A[34] Sign Extend Bits of B[34] BL * AU = 35 bits [34:17] [16:0] BU * AL = 35 bits [34:17] [16:0] 17-Bit Offset BU * AU = 36 bits [35:] [17:0] 34-Bit Offset P[69:52] P[51:34] P[33:17] P[16:0] UG431_c1_13_ : x 35 x 35 Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 31
32 1 : XtremeDSP x / DSPA C 70 DSPA FI FI FI DSP ECG ( ) GPS ( ) 1-4 FI k = N 1 yn ( ) = hk ( )xn ( k) k = x y ( ) n k y(n) n N x(n) x(n-1) x(n-2) x(n-n+1) N N y DSPA n DSPA 1-15 Z h0 h(n-1) OM AM Y(n) 32 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
33 FI x(n) Z -1 Z -1 Z -1 Z -1 Z -1 h(0) h(1) h(2) h(3) h(4) h(n-1) y(n) ug431_c1_14_ FI 1-15 : FI M(z) 2 1 x(n) = x I (n) + jx Q (n) 1-5 v(n) x l (n) M(z) I x Q (n) M(z) Q Direct Digital Synthesizer (DDS) ug431_c1_15_ : (GB) (YCrCb) OM FI P MACC X 0 P OPMODE Z Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 33
34 1 : XtremeDSP 0 1 MACC P MACC X Z / P OPMODE DSPA - X DSPA (PCIN) Z - OPMODE MACC FI FI UG073 : Virtex-4 FPGA XtremeDSP FI ( 1-17 ) 1 FPGA DSP DSPA DSP 34 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
35 h7(n) + X(n-4) h6(n) Z -2 + h5(n) + X(n-2) h4(n) Z -2 + y(n-6) h3(n) + h2(n) X(n) Z -2 + h1(n) + The entire implementation can reside within DSPA blocks, yielding high performance and low power h0(n) X(n) ug431_c1_16_ : DSPA FI Spartan-3A DSP 1-6 FI 10 FI Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 35
36 1 : XtremeDSP Slice 8 h7(n-7) + Y(n 10) Slice 7 h6(n-6) + Slice 6 h5(n-5) + Slice 5 h4(n-4) Slice 4 h3(n-3) + + The post adders are contained wholly in dedicated silicon for highest performance and lowest power Slice 3 h2(n-2) + Slice 2 h1(n-1) + Slice 1 h0(n) X(n) Zero Sign Extended from 36 Bits to Bits + ug431_c1_17_01 1- : FI : ( ) 36 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
37 DSPA DSPA 35 x x 35 x 35 4 OPMODE 1-19 : 1 A0 B0 A1 B1 Slice 4 Z -3 A[34:17] P[69:34] C port ight wire shift by 17 bits in fabric Slice 3 0,A[16:0] P[33:17] B[34:17] C port Slice 2 A[34:17] C port ight wire shift by 17 bits in fabric Slice 1 0,A[16:0] Z -3 P[16:0] 0,B[16:0] C port zero ug431_ch1_17_ : DSPA 35x35 35 x x x 35 Z -3 Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 37
38 1 : XtremeDSP SL16 Slice 4 Z -3 A[34:17] P[69:34] C port ight wire shift by 17 bits in fabric Slice 3 0,A[16:0] P[33:17] B[34:17] C port Slice 2 A[34:17] C port ight wire shift by 17 bits in fabric Slice 1 0,A[16:0] Z -3 P[16:0] 0,B[16:0] C port zero ug431_ch : DSPA 35 x 35 x DSP 2 A B (A_real x B_real) (A_imaginary x B_imaginary) = P_real 1-6 (A_real x B_imaginary) + (A_imaginary x B_real) = P_imaginary 1-7 / 1-21 x DSPA 38 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
39 DSPA Slice 4 The two input registers to the left align operands with the first output register below and avoid fabric The benefit is increased performance and lower power A_imag B_imag _ P_real Slice 3 A_real B_real + Slice 2 A_imag B_real + P_imag Slice 1 A_real B_imag + Zero Sign Extended from 36 Bits to Bits ug431_c1_22_ : x : x MACC DSPA MACC MACC N : Slice 1 = (A_real B_imaginary) accumulation Slice 2 = (A_imaginary B_real) accumulation Slice 3 = (A_real B_real) accumulation Slice 4 = (A_imaginary B_imaginary) accumulation : Slice 1 + Slice 2 = P_imaginary Slice 3 Slice 4 = P_real Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 39
40 1 : XtremeDSP Slice 4 A_imag B_imag + P_real Slice 3 A_real B_real + Slice 2 A_imag B_real + P_imag Slice 1 A_real B_imag + Sign Extended from 36 Bits to Bits ug431_c1_20_ : x MACC ( N ) 40 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
41 DSPA 1-23 N+1 1 Slice 4 + P_real Slice 3 A_real B_real Zero + Slice 2 + P_imag Slice 1 A_real B_imag + Zero Sign Extended from 36 Bits to Bits ug431_c1_21_ : x MACC ( N+1 ) Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 41
42 1 : XtremeDSP 1-24 X MUX P Slice 6 + P_real Slice 5 A_imag B_imag _ Slice 4 A_real B_real Zero Sign Extended from 36 Bits to Bits + Slice 3 + P_imag Slice 2 A_imag B_real + Slice 1 A_real B_imag + Zero Sign Extended from 36 Bits to Bits ug431_c1_22_ : x MACC ( ) 42 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
43 DSPA : OPMODE 2 DSP 1 DSP 36 n DSP n MUX 2n DSP n MUX 36 n DSP 1 DSP 1 DSP 0 1 DSP 24 2 AND 1 DSP 24 2 XO 1 DSP AND 1 DSP 2 DSPA DSPA 2 n N zeros N zeros Slice 1, P Carry Out PCOUT[000, A[17:1], 000] 17 bits of A N + 17 zeros Slice 2, P Carry In after 17 Bit ight Shift A[000, A[17:17 N 1]] N MSBs of A N zeros N MSBs of A Slice 2, P esult A[000, A[17 N:0], A[17:17 N 1]] N LSBs of A ug431_c1_23_ : Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 43
44 1 : XtremeDSP Slice 2 A[17:0] Slice 1 A[0,17:1] 2 n 1-26 DSPA 1 P MSB 0 A MSB 17 n 0 n 0 0 P MSB 0 A Zero A[17:0] PEG2 = right shifted by 17 PEG1+ n bit left shifted A[17:0] ight wire shift by 17 bits Note: The 17-bit shift must be done in fabric, as noted in Figure 1- PEG1 = [000, 000, A17:1, 000] n bit n zeros zeros A zeros 1-26 : ug431_c1_24_ n 0 ( ) 1 P 17 2 P A[17:1] LSB 0 1 P -17-n 0 n 0 A[17:1] 17 A n MSB P n n A[17:0] n LSB 0 2 P A[17:0] A[17 n:n, 17:17 n + 1] A[17:0] DSPA 2 n=17 1 B[17] MSB FF1 FF1 DSPA ( FF 2 FF1 FF2 FF2 DSPA ( FF ) 17 B[17] 1 2**17 2**17 FF -1-2**17 2**17 44 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
45 MACC FI UG073 : Virtex-4 FPGA XtreameDSP Spartan-3A HDL Spartan-3A Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 45
46 1 : XtremeDSP 46 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
47 2 DSPA DSPA FI d b a c p DS431_ch2_01_ : DSPA 2-1 : DSPA Fmax N FI FI 1 /DSPA 250MHz N FI FI 2 /DSPA 250MHz 1 /4 DSPA 250MHz 1 /3 DSPA 210MHz DSPA OPMODE ( 2-2) 2-2 : DSPA OPMODE[6] OPMODE[4] M = A * B 0 0 M = A * (D+B) 0 1 M = A * (D-B) 1 1 FI FI [c0,c1,c2,c3,c2,c1,c0] FI Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 47
48 2 : DSPA [c0,c1,c2,c2,c1,c0] FI DSPA 2-2 DSPA 5 FI 1 DSPA din Coef Coef Coef Coef 0 rounding constant dout UG431_ch2_02_ : FI (N) (M) FI N/M N/M 1 (FF) AM AM SL LUTAM AM 16 AM SL LUTAM FI N (N/2 +1) FI [c0 c1 c2 c1 c0] FI dout = dly[0]*c0 + dly[1]*c1 + dly[2]*c2 + dly[3]*c1 dly[4]*c0; dout = (dly[0]+dly[4])*c0 +(dly[1]+dly[3])*c1 + dly[2]*c2; japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
49 FI 2-3 FI din Coef Coef Coef Coef 0 rounding constant dout UG431_ch2_03_ : FI 2-4 din Coef Coef Coef Coef 0 ounding constant dout ug431_ch2_04_ : FI FI FI AM SLICE FF LUTAM SL Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 49
50 2 : DSPA 2-5 FI din z -1 z -1 z -1 z -1 Coef Coef Coef Coef rounding constant dout ug431_ch2_05_ : FI EAD FAST Kb AM 2 9Kb FI 1 AM DSPA 2-6 din Coef Coef Coef Coef 0 rounding constant dout ug431_ch2_06_ : 50 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
51 FI preal = areal * breal - aimg * bimg; pimg = areal * bimg + aimg * breal; 3 preal = (areal - aimg)* bimg + (breal - bimg)* areal; cpimg = (areal - aimg)* bimg + (breal + bimg)* aimg; areal breal preal aimg bimg areal bimg pimg aimg breal 2-7 : 4 ug431_ch2_07_ Spartan-3A DSP FPGA XtremeDSP DSPA japanxilinxcom 51
52 2 : DSPA areal aimg p pcout breal bimg m pcin p preal c m p pimg ug431_ch2_08_ : 3 DSPA PCIN DSPA C MEG DSPA DSPA 3 250MHz 200MHz 2-9 areal aimg m p breal bimg z -2 z -2 z -2 m c p preal c z -2 m p pimg ug431_ch2_09_ : 2ns 250MHz 52 japanxilinxcom Spartan-3A DSP FPGA XtremeDSP DSPA
デザインパフォーマンス向上のためのHDLコーディング法
WP231 (1.1) 2006 1 6 HDL FPGA TL TL 100MHz 400MHz HDL FPGA FPGA 2005 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
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内蔵ハードディスクユニット-20GB (PG-HD2E4H) 内蔵ハードディスクユニット-40GB (PG-HD4E4H)取扱説明書 HARD DISK DRIVE 20GB(PG-HD2E4H) HARD DISK DRIVE 40GB(PG-HD4E4H) USER'S GUIDE
B7FY-0351-02 J E J 1 J 1 2 3 2 4 J 3 4 Preface Thank you very much for purchasing the hard disk drive. This hard disk drive provides a IDE interface and can be installed in the 3.5-inch storage bay of
展開とプロビジョニングの概念
ADOBE CREATIVE SUITE 5 2010 Adobe Systems Incorporated and its licensors. All rights reserved. Adobe Creative Suite Deployment and Provisioning Concepts This guide is licensed for use under the terms of
19_22_26R9000操作編ブック.indb
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137. Tenancy specific information (a) Amount of deposit paid. (insert amount of deposit paid; in the case of a joint tenancy it should be the total am
13Fast Fair Secure PRESCRIBED INFORMATION RELATING TO TENANCY DEPOSITS* The Letting Protection Service Northern Ireland NOTE: The landlord must supply the tenant with the Prescribed Information regarding
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? FPGA FPGA FPGA : : : ? ( ) (FFT) ( ) (Localization) ? : 0. 1 2 3 0. 4 5 6 7 3 8 6 1 5 4 9 2 0. 0 5 6 0 8 8 ( ) ? : LU Ax = b LU : Ax = 211 410 221 x 1 x 2 x 3 = 1 0 0 21 1 2 1 0 0 1 2 x = LUx = b 1 31
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PX-1700F/PX-1600F
NPD4535-00 ...7... 7...10 Mac OS X...11 Mac OS X v10.5.x v10.6.x...11 Mac OS X v10.4.11...14...16...17...17...19 A4...22...23...24!EX...24 /...25 P.I.F. PRINT Image Framer...25...26...29...30...30...31...31...34
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H8000操作編
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License
第三者のソフトウェアについて お客様がご購入のキヤノン製品 ( 以下 本製品 ) には 第三者のソフトウェア モジュール ( その更新されたものを含み以下 第三者ソフトウェア ) が含まれており かかる 第三者ソフトウェア には 以下 1~8 の条件が適用されます 1. お客様が 第三者ソフトウェア の含まれる 本製品 を 輸出または海外に持ち出す場合は 日本国及び関連する諸外国の規制に基づく関連法規を遵守してください
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Unify NXJ Release 12 2002-2008 Unify Corporation All rights reserved. Sacramento California, USA No part of this tutorial may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated
Zinstall WinWin 日本語ユーザーズガイド
Zinstall WinWin User Guide Thank you for purchasing Zinstall WinWin. If you have any questions, issues or problems, please contact us: Toll-free phone: (877) 444-1588 International callers: +1-877-444-1588
2
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Copyright 2002-2003 SATO International All rights reserved. http://www.satoworldwide.com/ This software is based in part on the work of the Independen
SATO Label Gallery SATO International Pte Ltd Version : BSI-021227-01 Copyright 2002-2003 SATO International All rights reserved. http://www.satoworldwide.com/ This software is based in part on the work
MusicSoft Manager
MusicSoft Manager( ミュージックソフトマネージャー ) は 電子楽器で扱うファイル ( ソングやスタイルデータ ) を iphone/ipod touch/ipad 上で管理するアプリケーションです 本アプリケーションにより以下のことができます データのダウンロード購入 データをアプリと楽器 コンピューター オンラインストレージサービス Dropbox ( ドロップボックス ) 間で転送
Stratix IIIデバイスの外部メモリ・インタフェース
8. Stratix III SIII51008-1.1 Stratix III I/O R3 SRAM R2 SRAM R SRAM RII+ SRAM RII SRAM RLRAM II 400 MHz R Stratix III I/O On-Chip Termination OCT / HR 4 36 R ouble ata RateStratix III FPGA Stratix III
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インクジェットプリンター
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Appendix
Appendix Appendix-A PHP 392 Appendix-B -> cd ext/pgsql -> phpize ->./configure --with-pgsql -> make -> make EXTENSION_DIR=/usr/local/lib/php/extensions install extension_dir = "/usr/local/lib/php/extensions/"
操作ガイド（本体操作編）
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Adobe Acrobat DC 製品比較表
X X Adobe, the Adobe logo, Acrobat, the Adobe PDF logo, Creative Cloud, and Reader are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States and/or other countries.
DS-510
NPD4887-01 JA 2013 Seiko Epson Corporation. All rights reserved. EPSON EXCEED YOUR VISION Microsoft Windows Windows Vista SharePoint Microsoft Corporation Macintosh Mac OS OS X Apple Inc. Intel Intel Core
PSP-1000
PSP-1000 PSP PSP 3-097-555-01(1) 5 VCCI PSP-1000 2.4GHz2.400GHz 2.497GHz 2.4GHz 1. 2. 2.4GHz DS-SS 40m 2 PSP DNAS Dynamic Network Authentication System DNAS PSP PSP ID http://www.scei.co.jp/psp-eula 3
HardCopy IIIデバイスの外部メモリ・インタフェース
7. HardCopy III HIII51007-1.0 Stratix III I/O HardCopy III I/O R3 R2 R SRAM RII+ RII SRAM RLRAM II R HardCopy III Stratix III LL elay- Locked Loop PLL Phase-Locked Loop On-Chip Termination HR 4 36 HardCopy