HyperLynxを用いたUSB3.0 IBIS-AMI Compliance Test Simulation Kit
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1 The Application of Simulation Kit Using USB3.0 IBIS-AMI Model Motoaki Matsumura FUJITSU SEMICONDUCTOR LIMITED Asian IBIS Summit Yokohama, JAPAN November 16, 2012
2 Outline USB3.0 Compliance Simulation using IBIS-AMI Model Summary Expectation of IBIS-AMI 1
3 Outline USB3.0 Compliance Simulation using IBIS-AMI Model Summary Expectation of IBIS-AMI 2
4 Chip-PKG-PCB Co-Design of SerDes I/F 5Gbps SerDes I/F become prevalent, for example USB3.0. We want to bring a new product to market more quickly. Performance is improved. How we balance TAT with cost? Performance Target In addition to performance, TAT and cost are important. Performance is important. TAT Cost TAT (Turn Around Time) In this presentation, I will focus attention on USB3.0. Time to market Product cycle is short 3
![[Conclusion] : Only 0.5h for USB3.](/docs-images/62/48094549/images/5-2.jpg "0 Analysis Measurement vs Simulation Measurement Simulation is possible many times at the")
5 [Conclusion] : Only 0.5h for USB3.0 Analysis Measurement vs Simulation Measurement Simulation is possible many times at the initial designing stage. Spice Net Transient Analysis IBIS-AMI Channel Analysis Simulation time: 1000Bit 12h 1Mbit(Conversion), 120,000h match 1/240,000 Simulation time: 1Mbit, 0.5h IBIS-AMI enables a high accuracy and short TAT analysis. 4
6 USB3.0 Compliance Test Simulation Kit USB3.0 Compliance Test Simulation Kit on EDA Tool Semiconductor Vendor (1) Simulation Kit that reflected reference design. (4) The support of customer's difference analysis is easy. Customer (2) Customer can judge the quality of own design quantitatively. (3) Customer can execute differential analysis in a short TAT. (IBIS-AMI + EDA tool) EDA Vender (5) EDA tool support. Simulation Kit can prevent the troubles, for example mismatch between IBIS-AMI and EDA tool, the usage of EDA tool. 5
7 Contents of Simulation Kit A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP WireBonding 位置 3 段 Wire Signal/VDN/VDU:Wire 長 3.0mm VSU:Wire 長 2.0mm V/VSU:Wire 長 1.5mm SU SU Chip Size: mm DN USB_I USB_ USB_T CLK DU RX_P DN X_P USB_ USB_T SU DU RX_N DN X_N SU SU TopView Ball Pitch=1.0mm SU SU Signal/VDN/VDU VSU V/VSU Ball 数 V:15 VSU:7 VDN:3 VDU:2 CLK:1 DATA:2ペア計 :32Ball JEDEC.pin.M21のVDNについて USBマクロ以外の配線によって困難な場合に はVDNにしなくとも良い その代わりとして JEDEC.pin.L21にVDNをアサインする A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Simulation Kit Reference Design Stimulus Bit Pattern Ball Assign PCB Guide PCB Artwork Sim Result Eye Mask Tx Model PKG Model PCB Model Compliance Cable + Back Panel Rx Model IBIS-AMI S-Para S-Para S-Para S-Para IBIS-AMI Simulation Deck 6
8 Compliance Test Pattern (Stimulus) USB3.0 Tx Compliance Test Pattern & Transmitter Eye Universal Serial Bus 3.0 Specification Revision UI CP0 : 8B/10B pattern (PRBS is encoded) 100mV CP1 Repeat Pattern of 0, 1 Eye Height, Jitter(10-12 BER) Measurement CP0x10 6 UI + CP1x10 6 UI 2 million UI about 5000 days! Simulation time is too long in Spice Net Transient Analysis about 0.5 hours! Channel Analysis using IBIS-AMI 7
9 Speed up Simulation Time Channel Analysis 1. Analog Channel Impulse Response Process Impulse Response 2. Convolution Process TX EQ Interconnect (PKG+PCB+Connector+Cable ) RX EQ CDR Convolution Convolution Convolution We can execute the analysis of 1 million bits in 0.5 hours. 8
10 Characteristic of IBIS-AMI IBIS-AMI TX EQ AMI TX Analog Front-End Binary data [Algorithmic Model] AMI : Algorithmic Modeling Interface RX Analog Front-End IBIS Example Executable Windows_VisualC_32 TX_Wx32.dll TX.ami Executable Windows_VisualC_64 TX_Wx64.dll TX.ami Executable Linux_gcc4.4.2_32 TX_Lx32.so TX.ami Executable Linux_gcc4.4.2_64 TX_Lx64.so TX.ami [End Algorithmic Model] RX EQ AMI CDR Binary data Windows/Linux 64bit/32bit User can not correct IBIS-AMI, because AMI parts are black box. Model maker should verify the quality of own IBIS-AMI. (each OS, EDA tool) 9
11 Trouble Case of IBIS-AMI Analysis (1/2) Model dependence 0dB Spice Net Transient Analysis CTLE characteristic (Reference Equalizer) CTLE : Continuous Time Linear Equalizer CTLE S-para CDR IBIS-AMI Channel Analysis RX Analog Front-End AMI Some EDA tools are OK. Others are NG. CTLE CDR RX Analog Front-End All EDA tools are OK. AMI 10
12 Trouble Case of IBIS-AMI Analysis (2/2) Tool dependence Samples Per Bit Interval => Default Setting Samples Per Bit Interval => Recommended setting Voltage level is out of order! The setting value depends on modeling of IBIS-AMI. It is necessary to use the recommended value. It is important that IBIS-AMI model maker solve various problems of model and tool dependence, before model maker release it. 11
13 Reference Design (Differential Analysis) A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP WireBonding 位置 3 段 Wire Signal/VDN/VDU:Wire 長 3.0mm VSU:Wire 長 2.0mm V/VSU:Wire 長 1.5mm SU SU Chip Size: mm DN USB_I USB_ USB_T CLK DU RX_P DN X_P USB_ USB_T SU DU RX_N DN X_N SU SU SU SU TopView Ball Pitch=1.0mm Signal/VDN/VDU VSU V/VSU Ball 数 V:15 VSU:7 VDN:3 VDU:2 CLK:1 DATA:2ペア計 :32Ball JEDEC.pin.M21のVDNについて USBマクロ以外の配線によって困難な場合にはVDNにしなくとも良い その代わりとして JEDEC.pin.L21 に VDN をアサインする A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP WireBonding 位置 3 段 Wire Signal/VDN/VDU:Wire 長 3.0mm VSU:Wire 長 2.0mm V/VSU:Wire 長 1.5mm SU SU Chip Size: mm DN USB_I USB_ USB_T CLK DU RX_P DN X_P USB_ USB_T SU DU RX_N DN X_N SU SU SU SU TopView Ball Pitch=1.0mm Signal/VDN/VDU VSU V/VSU Ball 数 V:15 VSU:7 VDN:3 VDU:2 CLK:1 DATA:2ペア計 :32Ball JEDEC.pin.M21のVDNについて USBマクロ以外の配線によって困難な場合にはVDNにしなくとも良い その代わりとして JEDEC.pin.L21 に VDN をアサインする A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP At the environment building At the actual design Ball Assign PCB Guide PCB Artwork Ball Assign' PCB Artwork' Tx/Rx Model IBIS-AMI Reference Cable+BP S-Para Customer Design Sim Result PKG Model S-Para PCB Model S-Para PKG Model' S-Para PCB Model' S-Para Assign Compliance Test Simulation Kit Compliance Test Simulation Kit Compare Compare Differential Analysis 12
14 Measurement Correlation (1/2) Measurement environment Oscilloscope PCB 1.5m SMA Cable Sig Test 3m Cable + BP Equalizer CHIP PKG PCB PVT Item Comment USB3.0 Test Chip Wire Bond BGA 4layer 256ball 27mm-square 6layer Typical 13
15 Measurement Correlation (2/2) Measurement vs Simulation Models of Test Chip 14
16 Application:Cost Reduction Study PBGA 4layer PBGA 2layer LQFP Simulation time : 0.5h Simulation time : 0.5h Simulation time : 0.5h We can examine cost reduction of the product by using Simulation Kit in a short TAT. 15
17 Outline USB3.0 Compliance Simulation using IBIS-AMI Model Summary Expectation of IBIS-AMI 16
18 Summary USB3.0 Compliance Simulation using IBIS-AMI Model IBIS-AMI is a key technology of 5Gbps SerDes I/F analysis. High accuracy Short TAT It is important that IBIS-AMI model maker solve various problems between IBIS-AMI and EDA tool beforehand. Simulation Kit constructed on EDA tool is able to contribute to short TAT analysis and cost reduction of the product. 17
19 Outline USB3.0 Compliance Simulation using IBIS-AMI Model Summary Expectation of IBIS-AMI 18
20 Expectation of IBIS-AMI We expect more information about IBIS-AMI. Documents (IBIS-AMI Cookbook, Trouble shooting) Samples (IBIS-AMI, Simulation result) Visualization (EQ Characteristic) 19
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