G-PCI4
... 3 WINDOWSNT...3 WINDOWS2000/XP...3... 4...4 DLL WINDOWSNT/2000/XP...4...4... 5...5... 6...6...6...6...6...7...9...11... 11... 11... 11... 12... 12...12
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WindowsNT Windown NT(Ver 4.0) ENABLE.BAT DOS PC GPCI4 Windows2000/XP Gpci4 inf
WindowsNT NT_Driver GPCI4.SYS GPCI4.INI ENABLE.BAT REGINI.EXE Windows Windows2000/XP 2k_Driver GPCI4.SYS GPCI4.inf DLL WindowsNT/2000/XP DLL GPCI4DLL.LIB GPCI4.DLL GPCI4.H DLL GPCI4.LIB GPCI4API.DLL GPCI4API.H G4TestSaml G4TestSampl G4TESTSAMPLE.EXE project file
DLL Visual C++ / GPCI4DLL.LIB GPCI4API.LIB
HANDLE hvxd // hvxd=gpci4open( 0 ); // (0) // int ret; ret=gpci4close( hvxd ); Gpci4IoWrite( hvxd,offset,data ); // data=gpci4ioread( hvxd,offset,data ); // Gpci4SetRunMode(hVxD,QTARGMODE); Gpci4MemWrite( hvxd,offset,data ); // data=gpci4memread( hvxd,offset ); //
Gpci4SetRunMode hvxd,qmstmode ); Gpci4MasterDIR( hvxd,qdirin ); int ret; ret=gpci4memalloc( hvxd data_size //data_size //ret NULL char *buf; buf=(char*)malloc( data_size ); Gpci4DataLENG( hvxd,data_size ); // data_size int ret; ret=gpci4start( hvxd ); // ret= // BYTE status; status=gpci4statusread( hvxd ); // status 7="0" // // Gpci4ReadBuff( hvxd,buf,data_size ); free( buf ); // Gpci4MemFree( hvxd ) //
Gpci4MasterDIR( hvxd,qdirout ); int ret; ret=gpci4memalloc( hvxd data_size //data_size //ret NULL char *buf; buf=(char*)malloc(data_size); Gpci4DataLENG( hvxd,data_size ); // data_size buf) Gpci4WriteBuff( hvxd,buf,data_size ); int ret; ret=gpci4start( hvxd ); // ret= // BYTE status; status=gpci4statusread( hvxd ); // status 7="0" // free( buf ); // Gpci4MemFree( hvxd ) //
Gpci4INTEntry( hvxd,(dword)this->m_hwnd ); // this->m_hwnd LRESULT CGpci4sampView::WindowProc (UINT message, WPARAM wparam, LPARAM lparam) { if(message==wm_user_int){ // if((dword)lparam==(dword)hvxd){ // // if(message==wm_user_int){ if((dword)lparam==(dword)myhnd){ // if(wparam & 0x0001){ //End m_list.addstring("-----> Transfer Interrupt occured!"); } if(wparam & 0x0002){//INT 1 m_list.addstring("-----> INT 1 Interrupt occured!"); } if(wparam & 0x0004){//INT 2 m_list.addstring("-----> INT 2 Interrupt occured!"); } m_list.setcursel( m_list.getcount()-1) ;// } } } if(lparam==(dword)hvxd1){ // } } return CFormView::WindowProc(message, wparam, lparam); }
classwizard ID Gpci4sampView) WindowProc [ ] message WM_USER_INT wparam lparam WM_USER_INT) WM_USER+1
Gpci4Dll.h struct PPCI_CONFIG_DATA{ WORD DeviceID; WORD BenderID; WORD Status; WORD Command; DWORD ClassCode; BYTE RevisionID; BYTE Bist; BYTE HeaderType; BYTE LatencyTimer; BYTE CacheLineSize; DWORD BaseAddress1; // I/O DWORD BaseAddress2; // BYTE MaxLatency; BYTE MinGrant; BYTE IntPin; BYTE IntLine; }; Gpci4ConfigRead // #define ERROR_START1-1 // #define ERROR_START2-2 // #define ERROR_START3-3 // #define ERROR_START4-4 // // I/O address offset #define QMODEIO 0x00 // #define QMSTADRIO 0x04 // #define QMSTLENIO 0x08 // #define QMSTCTLIO 0x0C // #define QIODAIO 0x10 // #define QINTSETIO 0x14 // #define QINTSTSIO 0x18 // #define QMSTSTSIO 0x1C //
// Gpci4IoDADIR Gpci4MasterDIR #define QDIRIN 0 // #define QDIROUT 1 // // Gpci4AccessCnt #define QTRGMODE 0 // #define QMSTMODE 1 // #define QENDMASK 0x10 // #define QINT1MASK 0x20 // INT1 #define QINT2MASK 0x40 // INT2 #define QENDCLR 0x1 // #define QINT1CLR 0x2 // INT1 #define QINT2CLR 0x4 // INT2 #define QENDSTS 0x1 // #define QINT1STS 0x2 // INT1 #define QINT2STS 0x4 // INT2 Gpci4StatusRead "0" "1" Gpci4Start "0" PCI-FPGA SDRAM FPGA SDRAM FPGA PCI-FPGA PCI-FPGA SDRAM FPGA
Gpci4Dll.dll No. 1 Gpci4Open 2 Gpci4Close 3 Gpci4INTEntry 4 Gpci4INTClear 5 Gpci4INTMaskSet 6 Gpci4INTMaskClear 7 Gpci4SetRunMode 8 Gpci4MasterDIR 9 Gpci4SetDataLENG 10 Gpci4Start 11 Gpci4Stop 12 Gpci4MemAlloc 13 Gpci4MemFree 14 Gpci4ReadBuff 15 Gpci4WriteBuff 16 Gpci4INTStatusRead 2 17 Gpci4CNTStatusRead 18 Gpci4IoRead I/O PCI-FPGA 19 Gpci4IoWrite 20 Gpci4MemRead SDRAM FPGA 21 Gpci4MemWrite 22 Gpci4ConfigRead PCI
1 HANDLE Gpci4Open( BYTE p1 ) BYTE p1 2 HANDLE INVALID_HANDLE_VALUE
2 int Gpci4Close( HANDLE ph ) HANDLE ph int 0 0
3 voidgpci4intentry( HANDLE ph,dword p1 ) HANDLE ph DWORD p1 DWORD this->m_hwnd ph
4 void Gpci4INTClear( HANDLE ph,byte p1 ) HANDLE ph BYTE p1 QENDCLR 0x01 QINT1CLR INT1 (0x02 QINT2CLR INT2 (0x04
5 void Gpci4INTMaskSet( HANDLE ph,byte p1 ) HANDLE ph BYTE p1 QENDMASK 0x10 QINT1MASK INT1 (0x20 QINT2MASK INT2 (0x40 2
6 void Gpci4INTMaskClear( HANDLE ph,byte p1 ) HANDLE ph BYTE p1 QENDMASK 0x10 QINT1MASK INT1 0x20 QINT2MASK INT2 0x40 2
7 void Gpci4SetRunMode( HANDLE ph,byte p1 ) HANDLE ph BYTE p1 QMSTMODE QTRGMODE SDRAM FPGA Gpci4MMRead Gpci4MmemWrite SDRAM FPGA DAT0 31 Gpci4MemRead Gpci4MemWrite
8 void Gpci4MasterDIR( HANDLE ph,byte p1 ) HANDLE ph BYTE p1 QDIRIN QDIROUT PCI-FPGA SDRAM FPGA SDRAM FPGA PCI-FPGA
9 void Gpci4SetDataLENG( HANDLE ph,dword p1 ) HANDLE ph DWORD p1 Gpci4MemAlloc
10 int Gpci4Start( HANDLE ph ) HANDLE ph int ERROR_START1 ERROR_START2 ERROR_START3 ERROR_START4 SDRAM FPGA ERROR_START1 4
11 void Gpci4Stop( HANDLE ph ) HANDLE ph Gpci4Start PCI-FPGA SDRAM FPGA nack nvld_w nenb_r PCI-FPGA
12 BYTE Gpci4INTStatusRead( HANDLE ph ) HANDLE ph BYTE QENDSTS 0x1 QINT1STS INT1 0x2 QINT2STS INT2 0x4
13 BYTE Gpci4CNTStatusRead( HANDLE ph ) HANDLE ph BYTE QMSTBUSY 0x80 QACK ACK 0x20 QREQ REQ 0x10 QENBW ENB_W 0x08 QVLDW VLD_W 0x04 QENBR ENB_R 0x02 QVLDR VLD_R 0x01 QMSTBUSY
14 int Gpci4MemAlloc( HANDLE ph,dword p1 ) HANDLE ph DWORD p1 int NULL
15 void Gpci4MemFree( HANDLE ph ) HANDLE ph Gpci4MemAlloc
16 void Gpci4ReadBUFF( HANDLE ph,void *p1,dword p2, DWORD p3 ) HANDLE ph void *p1 DWORD p2 DWORD p3
17 void Gpci4WriteBUFF( HANDLE void *p1, DWORD p2,dword p3) HANDLE ph void *p1 DWORD p2 DWORD p3
18 DWORD Gpci4IoRead( HANDLE ph,dword p1 ) HANDLE ph DWORD p1 I/O DWORD PCI-FPGA PCI-FPGA SDRAM-FPGA
19 viod Gpci4IoWrite( HANDLE ph,dword p1,dword p2 ) HANDLE ph DWORD p1 I/O DWORD p2 DWORD PCI-FPGA PCI-FPGA SDRAM FPGA
20 DWORD Gpci4MemRead( HANDLE ph,dword p1 ) HANDLE ph DWORD p1 DWORD SDRAM FPGA PCI-FPGA SDRAM FPGA
21 void Gpci4MemWrite( HANDLE ph,dword p1, DWORD p2 ) HANDLE ph DWORD p1 DWORD p2 DWORD SDRAM FPGA PCI-FPGA SDRAM FPGA
22 void Gpci4ConfigRead( HANDLE ph, struct PPCI_CONFIG_DATA *p1 ) HANDLE ph PPCI_CONFIG_DATA *p1 PCI PCI PPCI_CONFIG_DATA