imai@eng.kagawa-u.ac.jp
No1
No2 OS Wintel Intel x86 CPU
No3
No4 8bit=2 8 =256(Byte) 16bit=2 16 =65,536(Byte)=64KB= 6 5 32bit=2 32 =4,294,967,296(Byte)=4GB= 43 64bit=2 64 =18,446,744,073,709,551,615(Byte)=16EB = 172 GB (KB) (MB) (GB) (TB) (PB) (EB)
No5 CPU CPU IF ID EX CPU CPU CPU CPU CPU Core i3 Core 2 Duo Pentium Dual-Core Celeron Dual-Core Pentium D Core Duo
No6 2007 CPU 3Ghz 2 2.6Ghz 4 CPU CPU Windows 7 CPU Core i7 Core i5 700 Core 2 Quad Phenom Phenom X4 http://homepage2.nifty.com/kamurai/cpu.htm
CISC RISC VLSI CPU LSI LSI CISC RISC
RISC CISC CISC Complex Instruction Set Computer architecture RISC RISC Reduced Instruction Set Computer architecture
Reduced Instruction Set Computer RISC 1975 John Cocke (IBM) D.Patterson Berkeley RISC Sun SPARC J.Hennessy Stanford RISC MIPS 1980 John Cocke, V. Markstein, The evolution of RISC technology at IBM, IBM Journal R&D, Vol.44, Num.1/2, pp.48-55, 2000.
RISC No2 IBM RISC 1974 12 MIPS 801 1 CPI 1977 15 MIPS IBM 3090 I/O IBM 9370 POWER
RISC No3 David A. Patterson and Carlo H. Sequin, RISC I: A Reduced Instruction Set VLSI Computer, Int l Symp. on Computer Architecture, pp.443-457, 1981. 1
CISC RISC 1. 2. CPU 3. VLIW 4. CISC RISC 5. CPU 6. CPU