「FPGAを用いたプロセッサ検証システムの製作」

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ゆみかみやまる
9 years ago
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1 FPGA

2 RISC Verilog-HDL FPGA (celoxica RC100 ) LSI LSI HDL CAD HDL 3 HDL FPGA MPU i

3 HDL FPGA FPGA Flash Memory Flash Memory MPU Flash Memory Flash Memory MPU MPU MPU MPU Flash RAM Module Sequencer Instruction Clock Counte r System Status Decoder FPGA MPU KUE-CHIPII KUE-CHIPII FPGA KUE-CHIPII ii

4 1 HDL 3 2 FPGA FPGA 6 5 Flash Memory 7 6 Flash Memory 7 7 MPU 8 8 Flash Memory 8 9 Flash Memory 9 10 MPU MPU Flash Memory Flash Memory Read/Write Flash RAM Module Sequencer KUE-CHIPII 25 1 MPU 22 2 MPU iii

5 LSI 1Chip SoC : System on Chip RTL(Register Transfer Level) 1 RTL 10 RTL LSI RTL HDL(Hardware Description Language) HDL Verilog-HDL VHDL 2 HDL HDL HDL HDL HDL HDL FPGA MPU 16bit RISC 2 MPU MPU ROM 8bit FPGA MPU 1

6 HDL HDL CAD LSI FPGA FPGA FPGA 5 KUE-CHIPII 2

7 HDL FPGA HDL 1 HDL RTL HDL NO NO YES YES FPGA or LSI NO YES 1 HDL HDL HDL RTL [7] RTL LSI FPGA HDL 3

8 FPGA FPGA Field Programmable Gate Array LSI CPLD CPLD Complex Programmable Logic Device FPGA FPGA FPGA 2 FPGA FPGA FPGA ASIC FPGA 2 FPGA FPGA FPGA FPGA 4

9 FPGA LSI LSI FPGA FPGA IP Intellectual Property FPGA FPGA FPGA IP CPU 2.2 MPU MPU MPU System Xilinx MPU Status Sequencer XCR3128XL PC Decoder CPLD Instruction Flash Intel Memory Clock RAM Strata Flash Counter Module Memory Xilinx SpartanII FPGA Celoxica RC100 Board 3 Xilinx SpartanII FPGA Xilinx CPLD Intel Strata Flash Memory Celoxica RC100 LSI FPGA MPU System Status Decoder Sequencer Memory Instruction Clock Counter Flash RAM Module HDL 5

10 MPU Sequencer System Status Decoder Sequencer Instruction Clock Counter MPU Memory MPU Flash RAM Module Flash Memory 2.3 MPU FPGA FPGA FPGA FPGA FPGA PC CPLD Sequencer ROM MPU System Status Decoder Sequencer CPLD PC Memory Instruction Clock Counter Flash RAM Module Flash Memory FPGA RC100 Board 4 FPGA Flash Memory Flash Memory FPGA Memory FPGA Sequencer Flash RAM Module System Status Decoder Sequencer Sequencer Flash RAM Module System Status Decoder Flash Memory Flash RAM Module Memory 6

11 MPU System Status Decoder Sequencer CPLD Memory Instruction Clock Counter Flash RAM Module Flash Memory FPGA RC100 Board 5 Flash Memory Flash Memory Flash Memory Memory MPU System Status Decoder Sequencer CPLD Memory Instruction Clock Counter FPGA Flash RAM Module Flash Memory RC100 Board 6 Flash Memory MPU MPU MPU Memory Sequencer MPU Instruction Clock Counter MPU 7

12 MPU System Status Decoder Sequencer CPLD Memory Instruction Clock Counter Flash RAM Module Flash Memory FPGA RC100 Board 7 MPU Flash Memory MPU Flash Memory Flash Memory Flash Memory Flash Memory Flash RAM Module System Status Decoder MPU System Status Decoder Sequencer CPLD Memory Instruction Clock Counter Flash RAM Module Flash Memory FPGA RC100 Board 8 Flash Memory Flash Memory Memory Instruction Clock Counter Flash Memory Flash RAM Module System Status Decoder Sequencer Flash RAM Module FPGA Memory Flash Memory Instruction Clock Counter Flash Memory Flash Memory PC 8

13 MPU System Status Decoder Sequencer CPLD Memory Instruction Clock Counter FPGA Flash RAM Module Flash Memory RC100 Board 9 Flash Memory 9

14 2.4 MPU MPU MPU 10 MPU INSTRUCTION DATA MEMORY PC SP MEMORY DECODER RF ALU 10 MPU MPU INSTRUCTION MEMORY DATA MEMORY MPU PC INSTRUCTION MEMORY SP DATA MEMORY DECODER RF ALU DATA MEMORY PC ALU [8] MPU 16bit RISC 16bit FPGA RISC 10

15 2.4.2 MPU MPU [1, 2, 3] R OP Rd Rs Rt Func I OP Rd Func Imm J OP Func Offset OP Rd Rs, Rt Func Imm Offset MPU ADD SUB ADC SBC AND OR XOR NOR SRL SLL SRA SLA SLT ADI SBI LIL LIH BRZ BNZ LD ST LR POP PUSH JR JMP JAL ITP NOP HLT MPU (4 ) MPU RISC Load/Store 11

16 MPU Verilog-HDL 360 4,988 39MHz CPI 4 10MIPS MPU MPU 11 PC DATA MEMORY SP INSTRUCTION MEMORY RF ALU <IF> <ID> <EX> <WB> Forwarding (Branch) Forwarding (ALU and Address) 11 MPU MPU IF ID EX WB 4 MPU Verilog-HDL 410 8,007 66MHz (1) IF IF PC INSTRUCTION MEMORY 12

17 PC ID ID ID PC INSTRUCTION MEMORY ID ID INSTRUCTION MEMORY ID PC 2 PC 2 (2) ID ID PC EX WB EX (3) EX EX DATA MEMORY ALU INSTRUCTION MEMORY DATA MEMORY DATA MEMORY ALU ID (4) WB WB ID EX ID EX (5) IF ID EX WB 13

18 ID IF EX ID EX WB ID WB EX 11 WB EX EX WB ID WB ID ID 2 WB 1 ALU ALU MPU IF ID ID EX WB WB MPU 4 14

19 3. FPGA 3 MPU 3.1 Flash RAM Module Flash RAM Module Celoxica RC100 Intel Strata Flash Memory Flash Memory 2 12 Wait Addr:X Data:X Start Read Operation Finish Read Operation Read Addr:PA Data:PD Finish Erase Operation Start Write Operation Start Erase Operation Write Addr:BA Write Addr:BA Data:20h Data:D0h Write Finish Write Operation Write Write Read Status Register If SRD[7] = 1 Read Addr:PA Addr:PA Addr:X Addr:X Data:40h Data:PD Data:70h Data:SRD If SRD[7] = 0 12 Flash Memory Flash Memory Read/Write 12 Read Read Read Flash Memory Erase 2 Write 2 Write 15

20 Write 4 Write Write 3 4 Write (X) Read 1 Write Flash Memory 8 1 Write Read/Write Flash Memory Flash Memory 80MHz CLK Flash Memory Flash RAM Module 40MHz(25ns) Read Waveform Address 125ns CE OE WE DATA 50n 25ns BYTE CLK 25n Write Waveform 75n Address CE OE WE 50n 50n DATA STS CLK 25n 500ns 13 Flash Memory Read/Write 16

21 Flash RAM Module Interface Interface Operation Control Read Operation Control Read/Write Control Operation Control Interface Read/Write Control Read/Write Read/Write Control Operation Control Flash Memory Read/Write Control Bus Flash RAM Module Read/Write Interface Operation Control Read/Write Control Read/Write Flash Memory 14 Flash RAM Module Flash RAM Module Verilog-HDL 210 1,118 40MHz 3.2 Sequencer Sequencer 8bit ROM 15 Sequencer 17

22 PROGRAM COUNTER ALU INSTRUCTION ROM REGISTER I/O PORT 15 Sequencer Sequencer INSTRUCTION ROM FPGA RAM FPGA PROGRAM COUNTER ROM ROM REGISTER 8bit ALU I/O PORT 8bit Sequencer 4 4 I/O PORT 32bit Sequencer ADD SUB ADC SBC AND OR XOR LDI CMP RIO WIO bit CHK JPC NOP HLT Sequencer REGISTER 1bit bit bit Sequencer Sequencer 1 4 Verilog-HDL ,552 53Mhz 18

23 3.3 Instruction Clock Counter Instruction Clock Counter Instruction Clock Counter MPU 3.4 System Status Decoder System Status Decoder Sequencer Sequencer Instruction Clock Counter System Status Decoder Sequencer 19

24 4. FPGA 2 MPU 3 FPGA 4.1 LSI DFT(Design For Test) FPGA FPGA 4.2 MPU Memory 2k Byte RC100 7 LED LED System Status Decoder Sequencer 7 LED 2.2 FPGA Sequencer 20

25 Reset Push System Instruction Xilinx Status MPU Clock Sequencer XCR3128XL PC Decoder Counter CPLD Memory 2k Byte 2k Byte Instruction Data Flash RAM Module FPGA Intel Strata Flash Memory RC100 Board ( 50) NOP HLT MPU 21

26 1 MPU 1 10 ( 50) ( 40) 1 2% 1 1% 1 1% 1 1% 2 0% 23 36% % 31 49% 34 52% % 15 24% % 5 10% 4 6% % 12 19% 99 24% 15 24% 15 23% % 1 2% 49 12% 3 5% 4 6% % 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 11 17% 49 12% 7 11% 8 12% 819 9% % % % % % MPU % C FOR FOR IF IF FOR 22

27 2 MPU 1 10 ( 50) ( 40) 3 5% 1 1% 2 3% 1 2% 2 0% 23 35% % 30 50% 32 50% % 15 23% % 6 10% 4 6% % 12 18% % 13 22% 15 23% % 1 2% 51 12% 3 5% 4 6% % 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 0 0% 11 17% 50 12% 6 10% 8 13% 819 9% % % % % % ( 50) ( 40) / 25.90% 25.59% 23.90% 24.33% 25.00%

28 CPI [1] FPGA 1 FPGA RC100 PC PC PC 24

29 5. KUE-CHIPII KUE-CHIPII(Kyoto University Education Chip2) FPGA [11] KUE-CHIPII FPGA KUE-CHIPII 5.1 KUE-CHIPII KUE-CHIPII 8 KUE-CHIPII 5.2 FPGA KUE-CHIPII KUE-CHIPII FPGA FPGA SpartanII KUE-CHIPII XSP-006 KUE-CHIPII KUE-CHIPII FPGA 17 KUE-CHIPII Connector Cable Connector Connector Cable Connector XSP KUE-CHIPII XSP-006 KUE-CHIPII KUE-CHIPII KUE-CHIPII 25

30 KUE-CHIPII KUE-CHIPII KUE-CHIPII KUE-CHIPII RC100 26

31 6 HDL FPGA MPU FPGA HDL HDL 5 27

32 28

33 [1] John L.Hennessy, David A.Patterson: ( )( ), BP,1999. [2] Andrew S. Tanenbaum:,,2000. [3] Jorgen Staunstrup,Wayne Wolf:Hardware/Software Co-Design,Principles and Practice, Kluwer Academic Pub.,1997. [4] FrancoisXavier Standaert, Gael Rouvroy, JeanJacques Quisquater, JeanDidier Legat: A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES RIJNDAEL, FPGA 03, February 23 25, pp , [5] Pablo Moisset, Pedro Diniz and Joonseok Park: Matching and Searching Analysis for Parallel Hardware Implementation on FPGAs, FPGA 2001, February 11-13, pp , [6] Dirk Koch, Jurgen Teich: Platform Independent Methodology for Partial Reconfiguration, CF 04, April 14 6, pp , [7] : VerilogHDL,CQ,2001. [8] : ASIC, Design Wave Magazine pp 20-47, [9] : CPU!, Design Wave Magazine , 2003 [10] : /,, [11] : FPGA,,

3 SIMPLE ver 3.2: SIMPLE (SIxteen-bit MicroProcessor for Laboratory Experiment) 1 16 SIMPLE SIMPLE 2 SIMPLE 2.1 SIMPLE (main memo

3 SIMPLE ver 3.2: SIMPLE (SIxteen-bit MicroProcessor for Laboratory Experiment) 1 16 SIMPLE SIMPLE 2 SIMPLE 2.1 SIMPLE (main memo 3 SIMPLE ver 3.2: 20190404 1 3 SIMPLE (SIxteen-bit MicroProcessor for Laboratory Experiment) 1 16 SIMPLE SIMPLE 2 SIMPLE 2.1 SIMPLE 1 16 16 (main memory) 16 64KW a (C )*(a) (register) 8 r[0], r[1],...,