White Paper SoC 2012 5 Author Gervais Fong Senior Product Marketing Manager, Synopsys, Inc. Eric Huang Senior Product Marketing Manager, Synopsys, Inc. USB Universal Serial Bus20 USB 10 480Mbps USB 2.0 HD HD Gbps USB SuperSpeed USB USB 2.0 10 10 2010 USB SoC IP HD Blu-ray/HD DVD 480Mbps USB 2.027GB USB 2.0 14 10 27GB 70
SSD Solid-State Drive PC USB 3.0 1 PC / PC 2012 2015 20 [1] 3 [2] 2009 NEC/ [3] 2010 PC 2011 PC AMD Fusion APU 2011 2 [4] PC CPU Ivy Bridge 72012 4 / PC Ultrabook [5] Windows PC 2012 Microsoft Linux 2011 Microsoft Windows 8 9Build[6] MCCI Windows 7 OS Linux Apple Mac [7] PC SoC 1 2 PC 2 1 1 IP IP USB 2.0480Mbps 10 5Gbps USB 2.0 USB 5 1 1 USB 2.0 USB 2.0 USB 2.0 2 2 USB 2.0 20 1 USB 2.0 USB USB 2.0 100mA 1.5 150mA USB 2.0 SoC 2
500mA1.8 900mA B1000mA USB 2.0 USB 2.0 PC USB 2.0 USB 2.0 PC PC USB 2.0 10 2 USB 2.0 USB 2.0 1SuperSpeed USB 2.0 3m USB 2.0 5m USB 2.0 2m 3m 13m IP IP IP IPSoC IP SoC USB PHY PHY PHY PHY PHY SoC SoC SoC PHY 1 SoC IP SoC 3
1 IP SoC SoC SoC 2 PHY IP100% 3 PVT PHY EMI/RFI IP 4 USB 2.0 USB-IF FPGA USB USB 2.0 USB 2.0 10 USB 2.0 USB 2.0 USB 2.0 MAC USB 2.0 MAC USB 2.0 1 USB SoC USB 2.0 USB IP SoC Time-to-Market PHY IP SoC IP 7 PHY IP 7 1. IP IP IP SoC 4
USB USB IP PC Blu-ray USB SuperSpeed High-Speed USB 2.0 Low-Speed USB 1.1 Full-Speed USB 1.1 DRD PC DRD DRD IP SoC AHB/AXI/ CPU DWC_usb3 PHY PIPE3 UTMI+ Tx FIFO RAM /2 Rx FIFO RAM /2 RAM /2 2PHYSoC USB 2.0 PHYUTMI+/ULPI PHYPIPE3 2 PHY 5Gbps AXI 3264 128 2 /PHY IP IP 5Gbps IP SPRAM DPRAM 5Gbps FIFO USB 2.0 USB 2.0 LPM Link Power Management IP xhci SoC 5
U0 U1 U2 U3 2. PHY IP 5Gbps PHY IP IP PVT SoC UTMI+/- HS DP0/DM0 / LS/FS PIPE3 PHY tx0_p, tx0_m; rx0_p, rx0_m 3 PHY 3 PHY 42 2 PIPE3 USB 2.0 480Mbps 5Gbps 1 SSC SSC EMI/RFI PHY 1 PHY SoC IP PHY IP cm 3m 5Gbps RX Electrical-Idle PIPE3LFPS Low-Frequency Periodic Signaling PHY PHY U0 U1 U2 U3 SuperSpeed Hi- Speed Full-Speed On-the-Go OTG PHY PHY JEDECESD ESD MM=HBM= CDM= SoC 6
ESD ESD PHY PHY130nm 28nm 3.3V I/O 2.5V I/O 1.8V I/O PHY DFM Design-for-Manufacturability 3. IP SoC SoC IP PHY IP BIST Built-In Self-Test JTAG IP IEEE 1149.1 JTAG TAP RAM PHY BIST PRBS Pseudo-Random Binary Sequence 4. IP PHY PHY USB IP IP 100% PHYPHY PHY 4 TX RX RX HSPICE 4 4 SoC 7
RX 5. FPGA FPGA SoC IPFPGA FPGA USB FPGA 5 FPGA 5 FPGA FPGA PHY FPGA CA FPGA USB-IF Implementers Forum 6. USB IP USB IP1 IP USB 2.0 USB 2.0 xhci IP SoC 8
7. USB-IF USB USB Implementers Forum USB-IF USB-IF PHY IP USB-IF USB USBUSB 12 USB-IF PIL Platform Integration LabUSB CRCU0/U1/U2/ U3 xhci USBUSBCV 9 / / /USB 2.0 USB-IF USB 2.0 150 3 IP PHY IP 7 SoC DesignWare IP DesignWare IPIP PHY IP IP HAPS FPGA IP IP OTG RAM SoC AXI AHB IP MIPS Million Instructions Per Second DesignWare IPU0 U1 U2 U3 SoC SoC RTL Power Compiler DesignWare IP 50% SoC 9
coreconsultant GUI USB-IF coreconsultant RTL RTL Synopsys Reuse Methodology Manual SoCcoreConsultantSTA DesignWare PHY SoC SSCSSC PHY PHY SSC PHY ESD Back-to-Back ESD DesignWare PHY IP 130nm 28nm 628nm DesignWare PHY IP 6 : 28nm DesignWare PHY DesignWare IP IP IP Verilog Vera VHDL SoC IP DesignWare PHY RX LOS RX I/O SoC PHY DesignWare IP IP IEEE 1149.1 JTAG RAM TAP ICE PHY BIST PRBS Pseudo-Random Binary Sequence PHY PHY SoC 10
DesignWare IP HAPS FPGA at-speed HAPS FPGA FPGA 1 Linux HID Human Interface Device USB-IF DesignWare IPUSB-IF USB PIL IP 200USB IP / SoC USB PCHD / USB 2.0 480Mbps 1 2012 USB USB 2.0 2 10 USB 2.0 USB SoC IPSoC IPTime-to-Market IP IP USB 2.0 / PHY PHY 1 SoC IP FPGA IP USB-IF DesignWare PHY IP SoC SoC 11
[1] Agam Shah. "High-Speed to Reach Smartphones, Tablets by Year End." PCWorld. 8 Jan 2012. 13 March 2012 http://www.pcworld.com/article/247507/highspeed_usb_30_to_reach_ smartphones_tablets_by_year_end.html [2] Steven Sinofsky. "Building robust support." Building Windows 8. 22 August 2011. 13 March 2012 http://blogs.msdn.com/b/b8/archive/2011/08/22/building-robust-usb-3-0-support.aspx [3] "NEC to begin sampling controller chip." Semiconportal. 19 May 2009. 13 March 2012 https://www.semiconportal.com/en/archive/new-product/device/090519-nec-electronics-usb-3- controller.html [4] Brooke Crothers. "AMD to back in its chips." CNET. 12 April 2011. 13 March 2012 http://news.cnet.com/8301-13924_3-20053123-64.html?tag=mncol;txt [5] Brooke Crothers. "Intel delivers in its chips, finally." CNET. 9 April 2012. 13 April 2012 http://news.cnet.com/8301-13924_3-57411494-64/intel-delivers-usb-3.0-in-its-chips-finally/ [6] Steven Sinofsky. "Building robust support." Building Windows 8. 22 August 2011. 13 March 2012 http://blogs.msdn.com/b/b8/archive/2011/08/22/building-robust-usb-3-0-support.aspx [7] Michael Lum. "Apple to introduce its own proprietary version of and DisplayPort?" VR-Zone. 7 April 2011. 13 March 2012 http://vr-zone.com/articles/apple-to-introduce-its-own-proprietaryversion-of-usb 3.0-and-displayport-/11819.html 158-0094 531-0072 2 21 1 3 19 3 13 TEL.03-6746-3500 FAX.03-6746-3535 TEL.06-6359-8139 FAX.06-6359-8149 Synopsys, Inc. All rights reserved.synopsyssynopsys, Inc. http://www.synopsys.com/company/pages/trademarks.aspx 05/12.AP.CS1573.