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2 : FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T)

3 LSI / PC clock accurate /

4 Artix-7 XC7A100T Kintex-7 XC7K325T

5 : CAD Hands-on: HDL (Verilog) CAD (Vivado HLx)

7 : 28y4 : b6uy

8 LSI: / OP

9 LSI ( ) : (Moore s law) :

10 EUV ( )

LSI 100 75 Yield Ramp-up Mask Cost Design Cost 13 12 Million USD 50 12 9 75 25 0 10 3 9 40 1 0.1 6 21 0.

11 LSI Yield Ramp-up Mask Cost Design Cost Million USD Process (nm) IC design costs at different process nodes Ilkka Tuomi, The Future of Semiconductor Intellectual Property Architectural Blocks in Europe, JRC European Commission, 2009

12 FPGA FPGA OK

13 Worldwide Wafer Capacity (8 eq, Million) mm 150mm 200mm 300mm 450mm mm Era: A New Opportunity for the Semiconductor Industry (4/25/2013) Future Fab Intl. Issue 45

14 : CPU/GPU Nintendo 3DS Nintendo DS Nintendo Wii U Nintendo Wii Xbox360 Sony Playstation Vita Sony PSP Sony Playstation 3 XBox360: IBM PowerPC (90, 65nm) Playstation 3: Cell BE (90, 65, 45nm) ARM / MIPS SoC LSI Million Units '08 '09 '10 '11 '12 '13 Annual Game Console Sales

PC 400 Notebook & Netbook Desktop 300 PC CPU LSI Million Units 200 168.7 201.2 209.

15 PC 400 Notebook & Netbook Desktop 300 PC CPU LSI Million Units Intel fab 14nm (Broadwell / Skylake) '09 '10 '11 '12 '13 '14 '15 '16 Annual PC Shipments Source: IDC Press Release & Trefis Estimate (2013)

16 MPU (CPU) Sales Intel Samsung / Apple Freescale MediaTek Spreadtrum Qualcomm AMD TI Nvidia Broadcom 60000! Million USD , ,247 1,210 2,831 3,605 4,552 4,249 4,850 2,614 4,152 5,322 6, ,435 36,892 36,325 0 '11 '12 '13 Leading MPU Suppliers Source: IC Insights

17 One-time programmable in-system program

18 IC 74 IC TC74HC00/04

19 Glue Logic LSI IC

20 Programmable? RAM ROM UVEPROM EEPROM ( ) ( )!

21 Floating gate MOS-FET MOS-FET Source Drain EEPROM MOS-FET Source Drain EEPROM

22 PROM AND Programmable ROM (AND ) Input OR Output OR * AND/OR PLD

23 PAL, PLA: Programmable Array Logic PROM AND + OR PAL: AND + OR PLA: AND + OR 22V

24 GAL: Generic Array Logic PAL, PLA FF CLK Q Q GAL CLK Q Q (GAL22V10 )

25 CMOS LSI: ( )

26 SRAM: EEPROM: MOS-FET Antifuse:

27 A B C Y A B C Y (LUT: look-up table) A B C LUT Y A 0 0 B 1 0 Y C 0

28 CPLD FPGA Coarse-grain

29 CPLD: Complex PLD Product term PLD block PAL, GAL PAL, GAL EPROM PLD Block Switch Matrix

30 Gate array ULA: uncommitted logic array LSI

31 FPGA: Field Programmable Gate Array LUT 4-LUT Island-style

32 PLD FPGA

33 NEC DRP (Renesas STP Engine) Mem Mem Mem Mem Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Control in Mem Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE State Transition Controller PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Mem 8bit x 2 data in 8bit DMU 8bit ALU 8bit data out Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Mem Mem Mem Mem Control out

34 Sea-of-gate CPLD

35 LSI PROM, PLD, FPGA

36 Web

37 FPGA Digilent Nexys 4 FPGA board (!) CAD: Vivado HLx Design Suite (Webpack edition)

38 CAD: Vivado HLx Design Suite (1) RHEL, SUSE, Cent OS 6.8, Ubuntu or Windows 7, 8.1, bit required

39 CAD: Vivado HLx Design Suite (2) WebPACK Design Edition System Edition IP SDK I/O IP System Generator for DSP

40 CAD: Vivado HLx Design Suite (3) Webpack: ( ) Design Edition: ($2,995-,1 year subscription) System Edition: ($4,795-, 1 year subscription) System Edition ( WebPack )

41 CAD: Vivado HLx Design Suite (4) Webpack OK

42 Vivado Xilinx University Program Nexys4 ( ) XUP

PLDとFPGA

PLDとFPGA PLDFPGA 2002/12 PLDFPGA PLD:Programmable Logic Device FPGA:Field Programmable Gate Array Field: Gate Array: LSI MPGA:Mask Programmable Gate Array» FPGA:»» 2 FPGA FPGALSI FPGA FPGA Altera, Xilinx FPGA DVD