LMC6022 Low Power CMOS Dual Operational Amplifier (jp)

Transcription

1 Low Power CMOS Dual Operational Amplifier Literature Number: JAJS754

2 CMOS CMOS (100k 5k ) 0.5mW CMOS CMOS LMC k 5k 120dB 2.5 V/ 40fA Low Power CMOS Dual Operational Amplifier V 5V 15V ds & Converted to nat2000 DTD Editted for 2001 Databook SGMLFIX:PR1.doc Fixed (mm) SGMLFIX:PR4.doc Fixed (mm) SGMLFIX:PR8.doc Fixed (mm) SGMLFIX:PR16.doc Fixed (mm) V/ s 0.5mW CMOS 8-Pin DIP/SO Top View Circuit Topology (Each Amplifier) National Semiconductor Corporation 1 Printed in Japan NSJ 6/2001

3 (Note 1) (V V ) 16V ( 10 ) ESD (Note 4) 1000V (V ) 0.3V (V ) 0.3V 18 ma 35 ma (Note 3) 5 ma V (Note 2) V (Note 12) 40 T J V 15.5V (Note 10) ( JA ) (Note 11) 8 DIP 101 /W 8 SO 165 /W DC V 5V V 0V V CM 1.5V V O 2.5V R L 1M T J 25 Symbol Parameter Conditions I Typical Limit (Note 5) (Note 6) Units V OS Input Offset Voltage 1 9 mv 11 max V OS / T Input Offset Voltage 2.5 V/ Average Drift I B Input Bias Current 0.04 pa 200 max I OS Input Offset Current 0.01 pa 100 max R IN Input Resistance 1 Tera CMRR Common Mode 0V V CM 12V db Rejection Ratio V 15V 61 min PSRR Positive Power Supply 5V V 15V db Rejection Ratio 61 min PSRR Negative Power Supply 0V V 10V db Rejection Ratio 73 min V CM Input Common-Mode V 5V & 15V V Voltage Range For CMRR 50 db 0 max V 1.9 V 2.3 V V 2.5 min A V Large Signal R L 100 k (Note 7) V/mV Voltage Gain Sourcing 100 min Sinking V/mV 40 min R L 5 k (Note 7) V/mV Sourcing 75 min Sinking V/mV 2

4 DC ( ) V 5V V 0V V CM 1.5V V O 2.5V R L 1M T J 25 I Symbol Parameter Conditions Typical Limit (Note 5) (Note 6) Units V O Output Voltage Swing V 5V V R L 100 k to 2.5V 4.43 min V 0.09 max V 5V V R L 5 k to 2.5V 4.00 min V 0.35 max V 15V V R L 100 k to 7.5V min V 0.09 max V 15V V R L 5 k to 7.5V min V 0.40 max I O Output Current V 5V ma Sourcing, V O 0V 9 min Sinking, V O 5V ma (Note 2) 9 min V 15V ma Sourcing, V O 0V 15 min Sinking, V O 13V ma (Note 12) 15 min I S Supply Current Both Amplifiers A V O 1.5V 165 max 3

5 AC V 5V V 0V V CM 1.5V V O 2.5V R L 1M T J 25 I Symbol Parameter Conditions Typical Limit (Note 5) (Note 6) Units SR Slew Rate (Note 8) V/ s 0.03 min GBW Gain-Bandwidth Product 0.35 MHz M Phase Margin 50 Deg G M Gain Margin 17 db Amp-to-Amp Isolation (Note 9) 130 db e n Input-Referred Voltage Noise F 1 khz 42 i n Input-Referred Current Noise F 1 khz Note 1: IC IC Note 2: mA Note 3: P D T J(max) JA T A P D P D (T J(max) T A )/ JA Note 4: 1.5k 100pF Note 5: Typ Note 6: Note 7: V 15V V CM 7.5V R L 7.5V 7.5V V O 11.5V 2.5V V O 7.5V Note 8: V 15V 10V Note 9: V 15V R L 100k 7.5V 1kHz V O 13V PP Note 10: JA P D (T J T A )/ JA Note 11: PC Note 12: 13V V 4

6 V S 7.5V T A 25 Supply Current vs Supply Voltage Input Bias Current vs Temperature Input Common-Mode Voltage Range vs Temperature Output Characteristics Current Sinking Output Characteristics Current Sourcing Input Voltage Noise vs Frequency 5

7 V S 7.5V T A 25 ( ) Crosstalk Rejection vs Frequency CMRR vs Frequency CMRR vs Temperature Power Supply Rejection Ratio vs Frequency Open-Loop Voltage Gain vs Temperature Open-Loop Frequency Response 6

8 V S 7.5V T A 25 ( ) Gain and Phase Responses vs Load Capacitance Gain and Phase Responses vs Temperature Gain Error (V OS vs V OUT ) Non-Inverting Slew Rate vs Temperature Inverting Slew Rate vs Temperature Large-Signal Pulse Non-Inverting Response (A V =+1) 7

9 V S 7.5V T A 25 ( ) Non-Inverting Small Signal Pulse Response (A V =+1) Inverting Large-Signal Pulse Response Inverting Small-Signal Pulse Response 8

10 V S 7.5V T A 25 ( ) Stability vs Capacitive Load Stability vs Capacitive Load Note: 500 (C f C ff ) LMC660 LMC662 ( ) 1 (5pF 10pF) 1 FIGURE 1. Circuit Topology (Each Amplifier) 5k CMOS 5k

11 ( ) FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance V (Figure 3 ) 50 A ( ) PC 1000pA PC Typical 0.04pA PC Figure 4 PC PC 2 PC V 5pA 100 5mV pA (1/2) Figure 5a Figure 5b Figure 5c Figure 5d FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor FIGURE 4. Example of Guard Ring in P.C. Board Layout (Using the LMC6024) 10

12 ( ) (b) Non-Inverting Amplifier (a) Inverting Amplifier (c) Follower FIGURE 5. Guard Ring Connections (d) Howland Current Pump PC PC Figure 6 ( PC PC ) FIGURE 6. Air Wiring Figure 7 S2 S2 (I ) FIGURE 7. Simple Input Bias Current Test Circuit C2 5pF 10pF NPO I S2 C2 S1 (S2 ) 11

13 ( ) C X (V 5.0V DC ) Photodiode Current-to-Voltage Converter Micropower Current Source Note: 5V C1 1/2 1/3 ( ) ( LM385 ) Low-Leakage Sample-and-Hold 12

14 (V 5.0V DC )( ) Instrumentation Amplifier If R1 R5, R3 R6, and R4 R7; Then A V 100( ) CMRR R3 R6 R4 R7 CMRR( ) R2 CMRR R7 Sine-Wave Oscillator 1 Hz Square-Wave Oscillator Power Amplifier R1 R2 C1 C2 f OSC 1/2 RC R R1 R2 C C1 C2 4.5V 2.0kHz 13

15 (V 5.0V DC )( ) 10 Hz Bandpass Filter 10 Hz High-Pass Filter (2 db Dip) f O 10 Hz Q 2.1 Gain Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) f c 10 Hz d Gain 1 High Gain Amplifier with Offset Voltage Reduction 46.8 V BIAS ( 1mV) Temperature Range NSC Transport Industrial Package Drawing Media 40 T J 85 IM 8-Pin M08A Rail IMX Small Outline Tape and Reel 14

16 inches (millimeters) CMOS 8-Pin Small Outline Molded Package (M) Order Number IM NS Package Number M08A 1. (a) (b) TEL.(03) /

17 IMPORTANT NOTICE