DS90LV047A

Transcription

1 3V LVDS 4 CMOS 4 CMOS Low Voltage Differential Signaling (LVDS) 400Mbps (200MHz) TLL/CMOS 350mV TRI-STATE 13mW ( ) PCB ENABLE ENABLE* AND TRI- STATE 4 DS90LV04 A (DS90LV048A ) ECL 1 1 Dual-In-Line 3V LVDS Quad CMOS Differential Line Driver Dana Kagiamoto ds added data rate vs cable length typ curve and test procedure Added TSSOP package modified sgml to fix typ curves into avo group add typ curves and update ESD fixed formats for graphics and changed nested div titles to all caps per National Spec- Will release to the web. Edited fail-safe text Converted to nat2000 DTD updated pid to reflect base and migrated to prod/ vee 400Mbps (200Mhz) 300ps ( ) 400ps ( ) 1.7ns ( ) 3.3V 350 mv (13mW 3.3V ) 5V LVDS OFF LVDS TIA/EIA-644 LVDS ( ) SOIC TSSOP 3V LVDS 4 CMOS Order Number TM, TMTC See NS Package Number M16A, MTC16 ENABLES INPUT OUTPUTS EN EN* D IN D OUT D OUT H L or Open L L H H H L All other combinations of ENABLE inputs X Z Z TRI-STATE National Semiconductor Corporation DS JP 1

2 (Note 1) (V CC ) (D IN ) (EN EN*) 0.3V 4V 0.3V (V CC 0.3V) 0.3V (V CC 0.3V) (D OUT D OUT ) 0.3V 3.9V (D OUT D OUT ) (P D )( 25 ) M MTC 1088 mw 866 mw 25 M 8.5mW/ MTC 6.9mW/ ( 4 ) ESD (Note 10) ( 1.5 k 100 pf) 10 kv (EIAJ pf) 1200 V (V CC ) V (T A ) Note Symbol Parameter Conditions Pin Min Typ Max Units mv V OD1 Differential Output Voltage R L 100 (Figure 1) D OUT V OD1 Change in Magnitude of V OD1 for Complementary Output States D OUT 1 35 mv V OS Offset Voltage V V OS Change in Magnitude of V OS for Complementary Output States 1 25 mv V OH Output High Voltage V V OL Output Low Voltage V V IH Input High Voltage D IN, EN, 2.0 V CC V V IL Input Low Voltage EN* GND 0.8 V I IH Input High Current V IN V CC or 2.5V A I IL Input Low Current V IN GND or 0.4V A V CL Input Clamp Voltage I CL 18 ma V I OS Output Short Circuit Current (Note 11) ENABLED, D IN V CC, D OUT 0V or D IN GND, D OUT 0V D OUT ma D OUT I OSD Differential Output Short Circuit ENABLED, V OD 0V ma Current (Note 11) I OFF Power-off Leakage V OUT 0V or 3.6V, V CC 0V A or Open I OZ Output TRI-STATE Current EN 0.8V and EN* 2.0V V OUT 0V or V CC A I CC I CCL I CCZ No Load Supply current Drivers Enabled Loaded Supply Current Drivers Enabled No Load Supply Current Drivers Disabled D IN V CC or GND V CC ma R L 100 All Channels, D IN V CC or GND (all inputs) ma D IN V CC or GND, EN GND, ma EN* V CC 2

3 V CC 3.3V 10 T A (Note ) Symbol Parameter Conditions Min Typ Max Units t PHLD Differential Propagation Delay High to Low R L 100, C L 15 pf ns t PLHD Differential Propagation Delay Low to High (Figure 2 and Figure 3 ) ns t SKD1 Differential Pulse Skew t PHLD t PLHD (Note 5) ns t SKD2 Channel-to-Channel Skew (Note 6) ns t SKD3 Differential Part to Part Skew (Note 7) ns t SKD4 Differential Part to Part Skew (Note 8) ns t TLH Rise Time ns t THL Fall Time ns t PHZ Disable Time High to Z R L 100, C L 15 pf 2 5 ns t PLZ Disable Time Low to Z (Figure 4 and Figure 5) 2 5 ns t PZH Enable Time Z to High 3 7 ns t PZL Enable Time Z to Low 3 7 ns f MAX Maximum Operating Frequency (Note 14) MHz Note 1: Note 2: V OD1 V OD1 Note 3: V CC 3.3V T A 25 Note 4: ( ) Note 5: t SKD1 t PHLD t PLHD Note 6: t SKD2 Note 7: t SKD3 V CC 5 Note 8: t SKD4 t SKD4 Max-Min Note 9: f 1MHz Z O 50 t r 1ns t f 1ns Note 10: ESD : (1.5 k 100 pf) 10 kv EIAJ (0 200 pf) 1200 V Note 11: (I OS ) Note 12: C L Note 13: 1 Note 14: f MAX t r t f 1 ns (0 100 ) V 45 /55 VOD 250mV Parameter Measurement Information FIGURE 1. Driver V OD and V OS Test Circuit 3

4 Parameter Measurement Information ( ) FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit FIGURE 3. Driver Propagation Delay and Transition Time Waveforms FIGURE 4. Driver TRI-STATE Delay Test Circuit 4

5 Parameter Measurement Information ( ) FIGURE 5. Driver TRI-STATE Delay Waveform FIGURE 6. Point-to-Point Application LVDS LVDS (# ) AN-808 AN-977 AN-971 AN-916 AN-805 AN-903 LVDS Figure ( ) PCB ( ) ( ) ( ) 3.1mA 2.5mA 4.5mA Figure 6 AC 3.1mA mV 210mV ( 310mV 100mV 210mV) Figure 7 1.2V( V OS ) V SS (V OD ) 2 620mV RS-422 RS MHz 50MHz ECL PECL LVDS ECL/PECL LVDS PECL 80 AC RS

6 ( ) TRI-STATE LVDS LVDS TTL 0.1 F F ( ) 10 F (35V) 4 LVDS TTL LVDS TTL LVDS TTL / TTL LVDS LVDS 10mm 1mm 3mm EMI ( v c/er c ( ) mm/ps in/ps) CAD 90 ( ) LVDS mm ( 12mm) LVDS LVDS (100k ) (2pF ) (FET ) 1GHz LVDS 100 ( ) ( ) EMI ( ) 50cm 50cm 10m CAT3 ( 3) LVDS DS90LV048A LVDS LVDS (20mV) CMOS / ("High" ) 6

7 ( ) 1. DS90LV048A 4 "High" "High" 2. OFF 100 "High" 10mV 3. 0V "High" (0 2.4V) ( ) 5k 15k 1.2V (1.75V ) FIGURE 7. Driver Output Levels 2, 3, 6, 7 D IN TTL/CMOS 10, 11, 14, 15 9, 12, 13, 16 D OUT D OUT LVDS LVDS 1 EN EN Low EN High EN* Low EN EN* 8 EN* EN* High EN* Low EN High EN EN* 4 V CC 3.3V 0.3V 5 GND Operating Package Type/ Order Number Temperature Number 40 to 85 SOP/M16A TM 40 to 85 TSSOP/MTC16 TMTC 7

8 Output High Voltage vs Output Low Voltage vs Output Short Circuit Current vs Output TRI-STATE Current vs Differential Output Voltage vs Differential Output Voltage vs Load Resistor 8

9 ( ) Offset Voltage vs Power Suppy Voltage Power Supply Current vs Frequency Power Supply Current vs Power Supply Current vs Ambient Temperature Differential Propagation Delay vs Differential Propagation Delay vs Ambient Temperature 9

10 ( ) Differential Skew vs Differential Skew vs Ambient Temperature Transition Time vs Transition Time vs Ambient Temperature 10

11 ( ) Data Rate vs Cable Length (PRBS) (Tektronix HFS9009) 50 SMB (Tektronix 11801B) (t tcs ) (t tui ) NRZ 0V LG UTP 4 24 CAT 5 DS90LV048A LVDS47/ 48EVK LVDS LVDS47/48PCB AN

12 inches (millimeters) 16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC Order Number TM NS Package Number M16A 12

13 inches (millimeters) ( ) 16-Lead (0.100 Wide) Molded Thin Shrink Small Outline Package, JEDEC Order Number TMTC NS Package Number MTC16 3V LVDS 4 CMOS 1. (a) (b) TEL.(03) /