Application Note 1194 Failsafe Biasing of LVDS Interfaces (jp)

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1 Application Note 1194 Failsafe Biasing of LVDS Interfaces Literature Number: JAJA274

2 LVDS LVDS 3 2 LVDS High Low 1. LVDS 2. LVDS (V CC 0V ) 3. LVDS ( ) 1. LVDS ( ) 2. LVDS 1. LVDS 2. LVDS High Low LVDS LVDS National Semiconductor Application Note 1194 John Goldie LVDS LVDS (800Mbps ) AC LVDS (V ID =0V) LVDS (ANSI/TIA/EIA-644-A) 100mV (Voltage Transfer Curve VTC) Figure 1 LVDS V ID 30mV V ID =0V High 25mV 55mV ( 25mV ( 30mV)) FIGURE 1. VTC Curve of a National Standard Speed LVDS Receiver 2.5V High LVDS AN-1194 National Semiconductor Corporation AN JP 1

3 AN ( ) (V OS ) EMI Figure 2 V CC 1.25V 3.3V 1.25V 3.3V 2V ESD 600ns ( 1 s) High 50mV ( ) 50mV 2 (6 ) 50mV ( ) High Low ( 60mV V ID ) Low 600ns High 1 s FIGURE 2. Single-Ended Waveforms Showing Common Mode Voltage between Driven and Un-Driven States vs Failsafe Implementation 1 2 LVDS LVDS ( 1) 3 (V OS ) ( k ) R1 R3 / ESD EOS ( ) 25mV (V fsb ) 25mV/ A 2

4 3mA 1 3.3V/250 A 13k RT 100 R3 R1 1.25V/3.3V= k R3 (4.99k ) R1 13k R3 8k 25mV RT (R2) R1 R3 AN-1194 FIGURE 3. External Failsafe Biasing of an LVDS Link ( ) LVDS 250mV 450mV LVDS 100mV V OD (250mV) 100mV (DNM) 150mV ( ) LVDS V OD 25mV V OD 25mV V OD 25mV Figure 5 150mV 125mV Figure 6 3 AC 30mV 40mV ( ) LVDS 225mV V OD 275mV V OD 50mV 600ns High ( 2) 50mV 50mV FIGURE 4. Differential Noise Margin Calculations FIGURE 5. Differential Noise Margin Calculations with External Failsafe Biasing 3

5 AN-1194 LVDS FIGURE 6. Differential Noise Margin for the Un-Driven Bus State vs Failsafe Implementation LVDS V ID =0V High Figure 1 25mV 100mV LVDS ATE ATE 3 ( DS92CK16 70mV) 25mV 50mV (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2007 National Semiconductor Corporation / LVDS 1. LVDS The active Fail-safe Feature of the SN65LVDS32B SLLA082A TEL.(03)

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