xi21-x.dvi
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1 (2) : 50, 67, 60 ( ),, ( ),, WWW ( ) (ID ) : WWW :, 1 11 ( ) MIPS x86 Mem[a,b], a b MIPS lw Rt,Imm(Rs) Rt = Mem[ Rs + sx(imm),4] sw Rt,Imm(Rs) Mem[ Rs + sx(imm),4] = Rt x86 movl (%Rb),%Rd Rd = Mem[Rb, 4] movl %Rs,(%Rb) Mem[Rb, 4] = Rs : IEEE , 127 ; , , +0, , m 0m , +, NaN
2 MIPS sx(f) f 32bit Mem[a,b] a b RF[k] k IR x:y IR x y c?a:b c 1 a, b x<<y x y x==y x y 1, 0 (1) add Rd,Rs,Rt Rd=Rs+Rt, PC=PC+4 addi Rt,Rs,Imm Rt=Rs+sx(Imm), PC=PC+4 lw Rt,Rs,Imm Rt=Mem[Rs+sx(Imm),4], PC=PC+4 sw Rt,Rs,Imm Mem[Rs+sx(Imm),4]=Rt, PC=PC+4 beq Rt,Rs,Imm PC=(Rt==Rs)? PC+4+sx(Imm)*4: PC+4 (2) opcode Rs Rt Rd func rrrrr rrrrr rrrrr opcode Rs Rt Imm oooooo rrrrr rrrrr iiii iiii iiii iiii IF ID EX MEM WB add Rd,Rs,Rt Y=A+B PC=NPC RF[IR 15:11]= 9 addi Rt,Rs,Imm IR = 1 A= 3 Y=A+I PC=NPC RF[IR 20:16]= 9 lw Rt,Rs,Imm NPC= 2 B= Y= 5 PC=NPC, M=Mem[Y,4] RF[IR 20:16]= 10 sw Rt,Rs,Imm I= 4 Y= 5 PC=NPC, 7 =B beq Rt,Rs,Imm Y= 6 PC=Y? 8 :NPC (3) IF ID EX MEM WB 4 + b mux a c RF r1# r1d r2# w# wd r2d d e f mux ALU g <<2 + h mux sx data bus address bus address data Mem
3 (1) check-in (2) interrupt (3) division (4) fast-in (5) (6) fault (7) cut-in (8) split-in 2 a, b, c a, b, CPU c, (1) b (2) b,c (3) a,c (4) a,b (5) a (6) c (7) a,b,c (8) 3 a, b, c, a b c (1) a (2) b (3) (4) c (5) a,c (6) a,b,c (7) b,c (8) a,b 4 a, b, c, a b c (1) a (2) b,c (3) (4) c (5) b (6) a,b (7) a,c (8) a,b,c 5 a, b, c, a b c (1) (2) b (3) c (4) a,b (5) a,c (6) b,c (7) a,b,c (8) a 6 a, b, c, a b c (1) c (2) b (3) a,c (4) b,c (5) a (6) a,b (7) a,b,c (8) 7 (1) OS (2) (3) (4) (5) (6) (7) 8 a, b, c a b c (1) a,b (2) b (3) a,b,c (4) (5) c (6) a (7) b,c (8) a,c 9 a, b, c a, b OS ( ) c ( ) (1) b (2) b,c (3) (4) a,b (5) a,c (6) a,b,c (7) a (8) c
4 NMI NM (1) no-machine (2) new miss (3) nano-mega (4) new machine (5) non-maskable (6) new miracle (7) no-message (8) neumann (9) non-multiple (0) 11 a d a b, c d (1) c a b d (2) b c d a (3) c b a d (4) (5) b c a d (6) b d c a (7) b a d c (8) c b d a (9) d b c a (0) d c b a 12 (1) < < (2) < < (3) < < (4) < < (5) < < (6) < < 13 (1) (2) RAM (3) (4) (5), DRAM 100 (6) 14 5 KB ( ) 20 ms 6000 rpm 10 MB (1) 125 ms (2) 255 ms (3) 156 ms (4) 237 ms (5) (6) 305 ms 15 (1) (2),, (3), (4), (5) (6) B, 16B, 88 (10 ) b f (1) b = 5, f = 8 (2) b = 10, f = 8 (3) b = 8, f = 8 (4) (5) b = 2, f = 24 (6) b = 5, f = 24 (7) b = 7, f = 8 (8) b = 1, f = 24
5 a, a d, a d a f CPU b b, c b d a b f (1) d - b - c - a (2) b - c - d - a (3) b - d - a - c (4) d - b - a - c (5) d - c - b - a (6) b - d - c - a (7) 18 a, b, c a, b,, c S-way, S = 1 (1) c (2) b (3) a (4) b, c (5) a, c (6) a, b (7) (8) a, b, c 19 4KB 32B, (1) 16 (2) (3) 64 (4) 32 (5) 512 (6) 256 (7) 1024 (8) MB, 32B, (1) 15bit (2) 12bit (3) 5bit (4) 9bit (5) (6) 16bit (7) 19bit (8) 24bit 21 64KB, 128B, (2 ) (2 ) (1) (2) (3) (4) (5) (6) (7) (8) KB, a d (2 ) 8KB, 32B, a: b: c: d: (1) a, b, d (2) a, c, d (3) a, b, c, d (4) a, b (5) a, d (6) a, c (7) a (8) a, b, c (9) 23 64KB, a d (2 ) 4KB, 32B, a: b: c: d: (1) a, c (2) a, b, c (3) a, b, c, d (4) (5) a, b, d (6) a, c, d (7) a, b (8) a (9) a, d
6 KB, a d (2 ) 8KB, 128B 2-way, FIFO a: b: c: d: (1) a, b, c (2) (3) a, b (4) a, b, c, d (5) a, b, d (6) a (7) a, c, d (8) a, c (9) a, d 25, 1GB, 16KB, (1) (2) 14bit (3) 22bit (4) 16bit (5) 18bit (6) 26bit (7) 20bit (8) 30bit 26 (1) (2), (3),, (4) 4KB, (5), 27 4, FIFO, ( ), (1) (2) 8 (3) 7 (4) 5 (5) 10 (6) 9 (7) 11 (8) , LRU, ( ), (1) (2) 8 (3) 9 (4) 11 (5) 7 (6) 5 (7) 10 (8) 6 29 a, b, c a ( ) b c CPU (1) c (2) b (3) a, b, c (4) b, c (5) a, b (6) a (7) (8) a, c 30 a, b, c a b c CPU (1) a, b (2) a (3) (4) c (5) b, c (6) a, c (7) a, b, c (8) b
7 (1),, (2), (3) (4) (5) (1) 7125 (2) 7625 (3) 725 (4) 7555 (5) 77 (6) 7111 (7) 7875 (8) (1) 3 8 (2) (3) (4) (5) (6) (7) 5 16 (8) (1) (2) (3) (4) (5) (6) (7) (8) (9) (0) , 2 (1) 0125 (2) 0375 (3) 075 (4) 0625 (5) 0875 (6) 02 (7) (8) 025 (9) , (1) (2) (3) (4) (5) IEEE754 (1) (3) (5) (7) (9) (2) (4) (6) (8) IEEE (1) b (2) b (3) b (4) (5) b (6) b (7) b (8) b (9) b (0) b IEEE754, (1) x7f (2) x (3) xffffffff (4) xff (5) x (6)
8 IEEE754, (1) (2) x (3) x7f (4) xffffffff (5) xff (6) x IEEE754 NaN (1) (2) (3) (5) (6) (7) (4) (8) 42 IEEE754 23, 10 (1) (2) 23 (3) 2 (4) (5) 43 round(x, k), 2 x k a, b, c a round(110011, 3) = 1101 b round(110010, 3) = 1101 c round(110110, 3) = 1110 (1) b (2) a, b (3) a, c (4) c (5) b, c (6) a, b, c (7) (8) a , 4, (1) (2) (3) (4) (5) (6) (7) (8) (9) , 4, (1) (2) (3) (4) (5) (6) (7) (8) (9) MFLOPS (1) mega floating point operations per second (2) meta floating long orientation per second (3) (4) mega flowchart octal per second (5) million flow long period series (6) memory flow large orthorization parallel series 47 P, p, N, n P: p: N: n: x (1) x < N (2) N < x < n (3) n < x < 0 (4) p < x < P (5) 0 < x < p (6) 48 P, p, N, n P: p: N: n: x (1) P < x (2) x < N (3) (4) p < x < P (5) N < x < n (6) n < x < 0
9 a, b, c a 10 10/20 2, b , 1 c k k, k=1 (1) a, b, c (2) (3) a, c (4) a, b (5) a (6) c (7) b (8) b, c 50 4 a, b, c a b c (1) a, b, c (2) a (3) b (4) a, b (5) (6) b, c (7) a, c (8) c 51 1 (1) (2) Mem[I,4] (3) Mem[Y,4] (4) Mem[A,4] (5) Mem[PC,4] (6) Mem[B,4] 52 2 (1) IR+I (2) PC+I (3) A+B (4) PC+4 (5) (6) A+I 53 3 (1) RF[IR 31:26 ] (2) RF[IR 5:0 ] (3) RF[IR 15:11 ] (4) (5) RF[IR 10:6 ] (6) RF[IR 25:21 ] 54 4 (1) RF[IR 5:0 ] (2) (3) sx(ir 15:0 ) (4) sx(ir 31:26 ) (5) IR 25:21 (6) IR 20: (1) A+NPC (2) A+PC (3) A+I (4) A+B (5) (6) A (1) RF[IR 15:0 ] (2) A+B (3) (A==B) (4) (5) A+PC (6) A+I 57 7 (1) RF[IR 20:16 ] (2) Mem[Y,4] (3) RF[IR 15:11 ] (4) Mem[B,4] (5) NPC+I<<2 (6) 58 8 (1) (2) I (3) Y<<2 (4) NPC+I<<2 (5) A+B+I (6) Mem[Y,4] 59 9 (1) I (2) RF[IR 20:16 ] (3) Mem[Y,4] (4) Y (5) PC (6) (1) A (2) RF[IR 15:11 ] (3) NPC (4) (5) M (6) PC 61, PC a h (1) c (2) h (3) g (4) f (5) (6) a (7) b (8) d (9) e
10 , IR a h (1) (2) d (3) b (4) e (5) g (6) c (7) f (8) h (9) a 63, Y a h (1) c (2) e (3) g (4) a (5) f (6) h (7) d (8) (9) b 64, A a h (1) a (2) g (3) e (4) b (5) d (6) f (7) (8) c (9) h 65, M a h (1) e (2) c (3) d (4) g (5) (6) b (7) f (8) h (9) a , 1, CPI (, ) (1) (2) 2 (3) 4 (4) 3 (5) 5 (6) 7 (7) 6 (8) 8 (9) 1 67 a, b, c a,, b,, c,, (1) (2) a, b (3) b (4) a, b, c (5) a (6) a, c (7) c (8) b, c 68 69, 68, 69 ( 1) ( ) 68 0, 69 6 ( 2) ( ) 68 1, 69 3 Nagisa ISHIURA
11 (2) : 50, 67, 60 ( ),, ( ),, WWW ( ) (ID ) : WWW :, 1 11 ( ) MIPS x86 Mem[a,b], a b MIPS lw Rt,Imm(Rs) Rt = Mem[ Rs + sx(imm),4] sw Rt,Imm(Rs) Mem[ Rs + sx(imm),4] = Rt x86 movl (%Rb),%Rd Rd = Mem[Rb, 4] movl %Rs,(%Rb) Mem[Rb, 4] = Rs : IEEE , 127 ; , , +0, , m 0m , +, NaN
12 MIPS sx(f) f 32bit Mem[a,b] a b RF[k] k IR x:y IR x y c?a:b c 1 a, b x<<y x y x==y x y 1, 0 (1) add Rd,Rs,Rt Rd=Rs+Rt, PC=PC+4 addi Rt,Rs,Imm Rt=Rs+sx(Imm), PC=PC+4 lw Rt,Rs,Imm Rt=Mem[Rs+sx(Imm),4], PC=PC+4 sw Rt,Rs,Imm Mem[Rs+sx(Imm),4]=Rt, PC=PC+4 beq Rt,Rs,Imm PC=(Rt==Rs)? PC+4+sx(Imm)*4: PC+4 (2) opcode Rs Rt Rd func rrrrr rrrrr rrrrr opcode Rs Rt Imm oooooo rrrrr rrrrr iiii iiii iiii iiii IF ID EX MEM WB add Rd,Rs,Rt Y=A+B PC=NPC RF[IR 15:11]= 9 addi Rt,Rs,Imm IR = 1 A= 3 Y=A+I PC=NPC RF[IR 20:16]= 9 lw Rt,Rs,Imm NPC= 2 B= Y= 5 PC=NPC, M=Mem[Y,4] RF[IR 20:16]= 10 sw Rt,Rs,Imm I= 4 Y= 5 PC=NPC, 7 =B beq Rt,Rs,Imm Y= 6 PC=Y? 8 :NPC (3) IF ID EX MEM WB 4 + b mux a c RF r1# r1d r2# w# wd r2d d e f mux ALU g <<2 + h mux sx data bus address bus address data Mem
13 (1) check-in (2) cut-in (3) fault (4) division (5) (6) split-in (7) interrupt (8) fast-in 2 a, b, c a, b, CPU c, (1) (2) a (3) b (4) c (5) a,b,c (6) a,b (7) a,c (8) b,c 3 a, b, c, a b c (1) b,c (2) a (3) c (4) a,b (5) (6) b (7) a,b,c (8) a,c 4 a, b, c, a b c (1) (2) a,b,c (3) a (4) c (5) b (6) a,c (7) b,c (8) a,b 5 a, b, c, a b c (1) b (2) a,b,c (3) a (4) a,b (5) c (6) a,c (7) b,c (8) 6 a, b, c, a b c (1) (2) a,b,c (3) b,c (4) b (5) a,b (6) a,c (7) c (8) a 7 (1) (2) (3) (4) (5) (6) OS (7) 8 a, b, c a b c (1) c (2) a (3) a,b (4) a,c (5) a,b,c (6) b (7) b,c (8) 9 a, b, c a, b OS ( ) c ( ) (1) a (2) a,b,c (3) b (4) b,c (5) c (6) a,b (7) a,c (8)
14 NMI NM (1) no-message (2) neumann (3) no-machine (4) nano-mega (5) new miss (6) (7) new miracle (8) non-multiple (9) non-maskable (0) new machine 11 a d a b, c d (1) b c a d (2) b a d c (3) (4) d c b a (5) c b d a (6) c a b d (7) b d c a (8) d b c a (9) c b a d (0) b c d a 12 (1) < < (2) < < (3) < < (4) < < (5) < < (6) < < 13 (1) RAM (2) (3) (4) (5), DRAM 100 (6) 14 5 KB ( ) 20 ms 6000 rpm 10 MB (1) 255 ms (2) 305 ms (3) 125 ms (4) 237 ms (5) (6) 156 ms 15 (1) (2), (3) (4) (5),, (6), B, 16B, 88 (10 ) b f (1) b = 10, f = 8 (2) b = 2, f = 24 (3) b = 8, f = 8 (4) (5) b = 7, f = 8 (6) b = 1, f = 24 (7) b = 5, f = 24 (8) b = 5, f = 8
15 a, a d, a d a f CPU b b, c b d a b f (1) d - c - b - a (2) (3) d - b - a - c (4) d - b - c - a (5) b - c - d - a (6) b - d - a - c (7) b - d - c - a 18 a, b, c a, b,, c S-way, S = 1 (1) a, b (2) (3) a (4) c (5) b, c (6) a, b, c (7) a, c (8) b 19 4KB 32B, (1) 32 (2) 64 (3) 128 (4) 16 (5) 1024 (6) 256 (7) 512 (8) 20 16MB, 32B, (1) (2) 19bit (3) 5bit (4) 15bit (5) 24bit (6) 16bit (7) 9bit (8) 12bit 21 64KB, 128B, (2 ) (2 ) (1) (2) (3) (4) (5) (6) (7) (8) KB, a d (2 ) 8KB, 32B, a: b: c: d: (1) a, c (2) a, b, d (3) a, c, d (4) a, b, c, d (5) a, b, c (6) a (7) a, b (8) a, d (9) 23 64KB, a d (2 ) 8KB, 32B, a: b: c: d: (1) a, c (2) a, b, c (3) a, b, c, d (4) a, b, d (5) (6) a (7) a, b (8) a, c, d (9) a, d
16 KB, a d (2 ) 8KB, 128B 2-way, FIFO a: b: c: d: (1) a, b, d (2) a, d (3) a, b, c, d (4) a (5) (6) a, b, c (7) a, c (8) a, c, d (9) a, b 25, 1GB, 16KB, (1) 26bit (2) 30bit (3) 16bit (4) 22bit (5) 18bit (6) (7) 14bit (8) 20bit 26 (1) 4KB, (2),, (3), (4) (5), 27 4, FIFO, ( ), (1) 5 (2) 9 (3) 6 (4) (5) 10 (6) 8 (7) 7 (8) , LRU, ( ), (1) 6 (2) (3) 9 (4) 11 (5) 5 (6) 7 (7) 8 (8) a, b, c a ( ) b c CPU (1) a, c (2) a, b (3) b, c (4) c (5) b (6) a (7) (8) a, b, c 30 a, b, c a b c CPU (1) c (2) a, c (3) a, b, c (4) b (5) (6) b, c (7) a, b (8) a
17 (1),, (2) (3), (4) (5) (1) 7875 (2) 725 (3) 7125 (4) 7625 (5) (6) 7111 (7) 7555 (8) (1) (2) (3) 3 8 (4) 5 16 (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) (9) (0) , 2 (1) 0375 (2) 025 (3) 0875 (4) 0625 (5) 05 (6) 02 (7) 0125 (8) (9) , (1) (2) (3) (4) (5) IEEE754 (1) (3) (5) (7) (9) (2) (4) (6) (8) IEEE (1) b (2) b (3) b (4) b (5) (6) b (7) b (8) b (9) b (0) b IEEE754, (1) xffffffff (2) (3) xff (4) x (5) x7f (6) x
18 IEEE754, (1) xff (2) xffffffff (3) x (4) x (5) x7f (6) 41 IEEE754 NaN (1) (2) (3) (4) (5) (6) (7) (8) 42 IEEE754 23, 10 (1) (2) 23 2 (3) 23 (4) 23 (5) 2 43 round(x, k), 2 x k a, b, c a round(110011, 3) = 1101 b round(110010, 3) = 1101 c round(110110, 3) = 1110 (1) (2) a, b (3) b, c (4) c (5) a, b, c (6) a, c (7) a (8) b , 4, (1) (2) (3) (4) (5) (6) (7) (8) (9) , 4, (1) (2) (3) (4) (5) (6) (7) (8) (9) MFLOPS (1) memory flow large orthorization parallel series (2) million flow long period series (3) mega floating point operations per second (4) (5) mega flowchart octal per second (6) meta floating long orientation per second 47 P, p, N, n P: p: N: n: x (1) 0 < x < p (2) N < x < n (3) p < x < P (4) (5) n < x < 0 (6) x < N 48 P, p, N, n P: p: N: n: x (1) P < x (2) x < N (3) (4) n < x < 0 (5) N < x < n (6) p < x < P
19 a, b, c a 10 10/20 2, b , 1 c k k, k=1 (1) a, b, c (2) b (3) a, b (4) a, c (5) a (6) (7) b, c (8) c 50 4 a, b, c a b c (1) a, c (2) c (3) b, c (4) a (5) b (6) (7) a, b (8) a, b, c 51 1 (1) Mem[B,4] (2) Mem[PC,4] (3) (4) Mem[Y,4] (5) Mem[A,4] (6) Mem[I,4] 52 2 (1) PC+I (2) A+B (3) PC+4 (4) A+I (5) IR+I (6) 53 3 (1) RF[IR 31:26 ] (2) RF[IR 5:0 ] (3) RF[IR 15:11 ] (4) RF[IR 25:21 ] (5) (6) RF[IR 10:6 ] 54 4 (1) IR 25:21 (2) sx(ir 15:0 ) (3) (4) RF[IR 5:0 ] (5) IR 20:16 (6) sx(ir 31:26 ) 55 5 (1) A+B (2) (3) A+NPC (4) A+4 (5) A+I (6) A+PC 56 6 (1) A+B (2) A+I (3) (4) A+PC (5) (A==B) (6) RF[IR 15:0 ] 57 7 (1) Mem[B,4] (2) RF[IR 20:16 ] (3) RF[IR 15:11 ] (4) NPC+I<<2 (5) (6) Mem[Y,4] 58 8 (1) A+B+I (2) I (3) (4) NPC+I<<2 (5) Mem[Y,4] (6) Y<< (1) (2) Mem[Y,4] (3) Y (4) PC (5) I (6) RF[IR 20:16 ] (1) PC (2) (3) M (4) NPC (5) RF[IR 15:11 ] (6) A 61, PC a h (1) b (2) f (3) c (4) e (5) g (6) h (7) d (8) (9) a
20 , IR a h (1) b (2) (3) c (4) a (5) e (6) h (7) g (8) f (9) d 63, Y a h (1) g (2) h (3) a (4) c (5) (6) e (7) b (8) d (9) f 64, A a h (1) c (2) e (3) (4) h (5) d (6) g (7) a (8) b (9) f 65, M a h (1) e (2) f (3) d (4) a (5) g (6) b (7) c (8) (9) h , 1, CPI (, ) (1) 6 (2) 8 (3) 4 (4) 1 (5) 5 (6) (7) 7 (8) 3 (9) 2 67 a, b, c a,, b,, c,, (1) a, b, c (2) (3) b (4) a, c (5) c (6) a (7) b, c (8) a, b 68 69, 68, 69 ( 1) ( ) 68 0, 69 6 ( 2) ( ) 68 1, 69 3 Nagisa ISHIURA
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