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1 I

2 ore ore 2

3 / Itanium Itanium 2 9 Itanium 2 Itanium ontvale** ichford* Tukwila** Poulson** 8870 ` l Xeon P 7000 Xeon P * Xeon 7000 * Xeon /850 Tigerton** aneland* Dunnington** larksboro* / Xeon DP 5000 * Xeon 7520 Xeon DP Xeon 5300 Xeon 500 * Xeon P/V Xeon UP 3000 * Pentium D Xeon UP Xeon 3200 Xeon 3000 UP /300 = Intel Neturst icroarchitecture = + ores 3

4 ore

5 5 / 2/ 2/ L2 L2 0.6G/ 0.6G/ FS FS L L D-TL TL ( ) 5 ore

6 inc store jne cmp load ecx [mem3], ebx targ eax,, [mem2] eax,, [mem] P dec0 dec dec2 dec3 2 inc ecx store [mem3], ebx jne targ cmp eax,, [mem2] load eax,, [mem] 6

7 inc store jne cmp load ecx [mem3], ebx targ eax,, [mem2] eax,, [mem] 5 P 2 dec0 dec dec2 dec3 inc ecx store [mem3], ebx cmpjne eax,, [mem2], targ load eax,, [mem] 7

8 / () 5 2/ L2 0.6G/ FS 28 dd + 28 ultiply + 28 Load + 28 Store + ( PJ ) L D-TL 2 8

9 9 2/ 2/ L2 L2 0.6G/ 0.6G/ FS FS / L L D-TL TL ( ) 5 / L L D-TL TL ( ) 5 2 L2 L2

10 2 2 L2 L2 L2 2 0

11 2 2 L2 FS H L2 L2 FS H L2 L 2

12 2 2/ 2/ L2 L2 0.6G/ 0.6G/ FS FS / L L D-TL TL ( ) 5 / L L D-TL TL ( ) 5 2/ 2/ L2 L2 0.6G/ 0.6G/ FS FS / L L D-TL TL ( ) 5 / L L D-TL TL ( ) 5

13 Pipeline Stages Threads per core L ache rg. Intel Neturst (2K uop Trace ache/6k Data) Intel ore icro architecture ** (32K I/32K Data) L2 ache rg. Instr. Decoders Integer Units SID Units SID Inst. Issued per lock 2 x 2 2 (2x core freq) 2 x 6-bits x (shared) 3 (x core freq) 3 x 28-bits 3 FP Units FP Inst. Issued per clock Power/Socket 3 (dd/ul/div) 35W 3 (dd/ul/div) Up to 2 (dd + ul or Div) 80W ++ edar ill/dempsey ** Intel ore icro rchitectuer = per core 3

14 2/ 33% (3 5 L2 ) ache 2 / 0.6G/ FS () 2 L D-TL ore

15 P Server Dual-ore Intel Xeon 700 processor ache 6 ache 6 ache 6 ache X X Truland Platform Intel 850/8500 X X 5

16 2007 P Server Quad-ore Tigerton processor on aneland 2 T 3 2 Intel ore T icroarchitecture 2 Quad-ore X ores ache 6 ache ache ache 6 ache ache ache 6 ache ache Shared L2 aches ache 6 ache ache Dedicated High Speed Interconnects >2X andwidth FD emory Truland educed Snoop Filter Platform System ache Traffic I/ Intel cceleration 850/8500 LKS (IT2) >2X emory apacity 6

17 Intel Xeon P Single-ore P front-side bus Large PU cache entralized emory FS 00 H SW GH DD-II, Dual-ore Dual-independent bus ache per core emory capacity DI 800 H Twinastle DD T/s FS (2002) Gallatin/ GH Total Theoretical Data andwidth (G/s) T/s DI (2005) Truland/ Twin astle T/s DI (2006) Truland/ Twin astle T/s DHSI (2007) aneland/ larksboro Quad-ore Dedicated buses Shared PU aches hipset Snoop Filter Next Gen emory FD Dedicated High Speed Interconnect Snoop Filter Northbridge Next Generation hipset 7

18 IS T /m / 8

19 : vonsolidate Java ysql* pache* vonsolidate Xen 3.0.3* ed Hat Linux update * : 2006 : Xeon 560 Xeon 5300 D pteron* 228 ISV IS, V 9.0 Xeon Xeon X % 68% Xeon % Xeon X5355

20 S 32 /6 V V 2-way I/ 6G 2G/s QuickData Gb 8 I/ 2 PU 0% 0% 2 F-DI 6 Linux6 Xeon 2 QuickData Xeon 20

21 2 pp pp S pp pp S Partitioned resources Partitioned resources pp pp S pp pp Partitioned resources Partitioned resources pp pp S Partitioned resources Partitioned resources pp pp, ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore ore

22 22

23 23

24 New New New 2

25 VTune ++ 25

26 26

27

28 / Intel s Terms and conditions of Sales Web ( IntelIntel IntelIntelIntel ore Intel Neturst Intel XScale Itanium Itanium Inside Xeon Xeon Inside Intel orporation 2006 Intel orporation 28

The 3 key challenges in programming for MC

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