デザインパフォーマンス向上のためのHDLコーディング法

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1 WP231 (1.1) HDL FPGA TL TL 100MHz 400MHz HDL FPGA FPGA Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. WP231 (1.1)

2 : HDL SL FPGA FPGA (SL) FPGA (LUT) OM/AM SL TL SL (SL) 1 1 FF D Address SLC16E Q D Q Synchronous Output CE (Write Enable) CLK Q15 WP231_01_ : ( Clock-to-Out ) ( ) SL SL Clock-to-Out SL 2 WP231 (1.1)

3 : HDL AM FPGA DSP AM FPGA FPGA AM OM LUT AM AM AM Virtex TM MHz 2 500MHz Virtex-4 AM AM AM LUT OM LUT 1 AM AM AM FPGA 2 ( 3 FDSE ) 1 : 5 2 LUT 2 WP231 (1.1)

4 : HDL VHDL process (CLK, ST) if (ST = '1') then Q <= '0'; elsif (rising_edge(clk)) then Q <= A or (B and C and D and E); Verilog CLK, posedge ST) if (ESET) Q <= 1'b0; else Q <= A (B & C & D & E); D E LUT4 A B C LUT4 CLK FDCE CL Q ST WP231_02_ : 2 : WP231 (1.1)

5 : HDL VHDL Verilog process (CLK) if (rising_edge(clk)) then if (ST = '1') then Q <= '0'; else Q <= A or (B and C and D and E); A CLK) if (ESET) Q <= 1'b0; else Q <= A (B & C & D & E); B LUT4 C D E CLK S FDSE Q ST WP231_03_ : 3 A High Q 1 (O ) FDSE 3 : 8 3 LUT 4 WP231 (1.1)

6 : HDL VHDL process (CLK, ST) if (ST = '1') then Q <= '0'; elsif (rising_edge(clk)) then Q <= (F or G or H) and (A or (B and C and D and E)); Verilog CLK, posedge ST) if (ESET) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E)); F LUT4 G H LUT4 A FDCE Q B C D LUT4 CLK CL E ST WP231_04_ : WP231 (1.1)

7 : HDL VHDL Verilog process (CLK) if (rising_edge(clk)) then if (ST = '1') then Q <= '0'; else Q <= (F or G or H) and (A or (B and C and D and E)); CLK) if (ESET) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E)); A B C D E LUT4 S FDSE Q ST F G H LUT4 CLK WP231_05_ : 5 LUT FPGA WP231 (1.1)

8 : HDL ( 6 ) FPGA Virtex-4 DSP 7 FPGA DSP DSP 500MHz 8 WP231 (1.1)

9 : HDL h7(n) X(n-4) h6(n) Z -2 h5(n) X(n-2) h4(n) Z -2 y(n-6) h3(n) h2(n) X(n) Z -2 The final stages of the post addition are implemented outside the dedicated blocks and are the performance bottleneck that consume more power. h1(n) h0(n) X(n) 6 : WP231_06_ WP231 (1.1)

10 : HDL Slice 8 h7(n-7) Y(n 10) Slice 7 h6(n-6) Slice 6 h5(n-5) Slice 5 h4(n-4) Slice 4 h3(n-3) The post adders are contained wholly in dedicated silicon for highest performance and lowest power. Slice 3 h2(n-2) Slice 2 h1(n-1) Slice 1 h0(n) X(n) Zero Sign Extended from 36 Bits to Bits 7 : WP231_07_ Virtex-4 UG073: FPGA XtremeDSP 10 WP231 (1.1)

11 : HDL ( ) Virtex-4 DSP 8 8 FPGA 1/8 Virtex-4 AM AM AM HDL HDL 2 Virtex Spartan TM 3 5 : 1 WP231 (1.1)

12 : HDL 1 : AM VHDL -- 'write first' or transparent mode process (clk) if (rising_edge(clk)) then if (we = '1') then mem(conv_integer(addr)) <= di ; do <= di; else do <= mem(conv_integer(addr)); -- 'read first' or read before write(slower) process (clk) if (rising_edge(clk)) then if (we = '1') then mem(conv_integer(addr)) <= di; do <= mem(conv_integer(addr)); -- 'no change' mode process (clk) if (rising_edge(clk)) then if (we = '1') then mem(conv_integer(addr)) <= di ; else do <= mem(conv_integer(addr)); Verilog // 'write first' or transparent mode clk) if(we) do <= data; mem[address] <= data; end else do <= mem[address]; end // 'read first' or read before write mode(slower) clk) if (we) mem[address] <= data; do <= mem[address]; end // 'no change' mode clk) if (we) mem[address] <= data; else do <= mem[address]; end AM (Synplicity Synplify ) AM TL AM ( 2 ) 12 WP231 (1.1)

13 : HDL 2 : VHDL Verilog type mem_type is array (127 downto 0) of std_logic_vector (7 downto 0); signal mem : mem_type; // disable conflict avoidance logic reg [7:0] mem [127:0] /* synthesis syn_ramstyle=no_rw_check*/; -- disable conflict avoidance logic attribute syn_ramstyle of mem : signal is "no_rw_check"; FPGA LUT 1 I/O DSP I/O Clock-to-Out FPGA DSP Clock-to-Out (MEG) (AEG BEG) Virtex-4 DSP ( ) 1.8ns Clock-to-Output 2.3ns MEG (PEG) 3ns Clock-to-Out 0.6ns 8 WP231 (1.1)

14 : HDL AEG MEG PEG BEG 8 : DSP WP231_08_ HDL ( ) I/O FPGA FPGA Clock-to-Out I/O FPGA I/O I/O FPGA Synplify I/O 1. ( ) I/O 2. IOB=TUE UCF HDL I/O ( IOB ) 3. ISE Project Navigator Map [Pack I/O egisters/latches into IOBs] ( -pr ) I/O WP231 (1.1)

: HDL WP231_09_110905 9 : I/O I/O FPGA FPGA FPGA HDL FPGA

15 : HDL WP231_09_ : I/O I/O FPGA FPGA FPGA HDL FPGA I/O FPGA I/O 3 64 HDL WP231 (1.1)

16 : HDL 3 : VHDL Verilog attribute EQUIVALENT_EGISTE_EMOVAL : string; attribute EQUIVALENT_EGISTE_EMOVAL of ce1 : signal is "NO"; attribute EQUIVALENT_EGISTE_EMOVAL of ce2 : signal is "NO"; -- Clock enable register with 64 fanout -- replicated once process (clk) if (rising_edge(clk)) then ce1 <= ce; ce2 <= ce; process (clk) if (rising_edge(clk)) then if (ce1='1') then res(31 downto 0) <= a_data(31 downto 0); if (ce2='1') then res(63 downto 32) <= a_data(63 downto 32); (*EQUIVALENT_EGISTE_EMOVAL="NO"*) reg ce1, ce2; // Clock enable register with 64 fanout // replicated once clk) ce1 = ce; ce2 = ce; end clk) if (ce1) res[31:0] <= a_data[31:0]; if (ce2) res[63:32] <= a_data[63:32]; end 6 : XST (EQUIVALENT_EGISTE_EMOVAL) FPGA 16 WP231 (1.1)

17 : HDL X 32 Virtex-4 DSP 4 : VHDL type regbank6x64 is array(pipe-1 downto 0) of std_logic_vector(63 downto 0); signal prod: regbank6x64; -- 32x32 multiplier with 4 DSP (PIPE=6) prod(0) <= a * b; regbank: for i in 1 to PIPE generate process (clk) if (rising_edge(clk)) then prod(i) <= prod(i-1); end generate; parameter PIPE = 6; Verilog reg signed [63:0] prod [PIPE-1:0]; // 32x32 multiplier with 4 DSP (PIPE=6) clk) prod[0] <= a * b; for (i=1; i<=pipe-1; i=i1) prod[i] <= prod[i-1]; end assign mult_out = prod[pipe-1]; mult_out <= prod(pipe); TL TL TL TL TL WP231 (1.1)

18 : HDL FPGA TL SL SL ( SL ) SL Clock-to-Out Clock-to-Out SL SL FPGA LUT LUT HDL (DD) 2 VHDL Virtex-4 I/O SerDes Virtex-4 FIFO DSP Verilog VHDL COEGenerator TM Architecture Wizard ISE CLB WP231 (1.1)

19 : HDL BUFGCE ( 10 ) CE BUFGCE I O 10 : WP231_10_ BUFGCE FPGA VHDL GATECLK <= (IN1 and IN2 and CLK); process (GATECLK) if (rising_edge(gateclk)) then if (LOAD = '1') then OUT1 <= DATA; Verilog assign GATECLK = (IN1 & IN2 & CLK); GATECLK) if (LOAD) OUT1 <= DATA; end DATA LOAD D DFF Q OUT1 IN1 IN2 GATECLK CE C CLK AND3 WP231_11_ : - WP231 (1.1)

20 : HDL VHDL ENABLE <= IN1 and IN2 and LOAD; process if (rising_edge(clock)) then if (ENABLE = '1') then DOUT <= DATA; Verilog assign ENABLE = (IN1 & IN2 & LOAD); CLOCK) if (ENABLE) DOUT <= DATA; end DATA IN1 IN2 LOAD CLOCK AND3 ENABLE DFF D Q CE C OUT1 WP231_12_ : - If-Then-Else Case For if case if if HDL for 1 for 20 WP231 (1.1)

21 : HDL HDL I/O DD SerDes I/O 1 3. FPGA Virtex-4 DSP TL WP231 (1.1)

22 : HDL TechXclusives XST Sunburst Design Verilog StateCAD XE /12/ /01/ WP231 (1.1)

if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

if clear = 1 then Q <= ; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we