MAX9257 EV.J
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1 9-76; Rev 0; 6/08 PART TYPE MAX957/MAX958EVKIT+ EV Kit DESIGNATN QTY DESCRIPTN C C6, C6 C9, C C5, C50 C55, C59 C65, C75 C80, C8 C0, C06 C, C, C5, C6 C7 C, C66 C7 C0, C, C8, C8 79 C, C8 C6 C9, C0 C05 C56, C57, C, C 8 ±0%, 6V X7R ceramic capacitors (00) TDK C005X7RC0K nf ±5%, 5V C0G ceramic capacitors (00) TDK C005C0GE0J 5pF ±5%, 50V C0G ceramic capacitors (00) TDK C005C0GH50J μf ±0%, 6V X7R ceramic capacitors (060) TDK C608X7RC05K 00μF ±0%, 6.V X5R ceramic capacitors (0) TDK C5X5R0J07M 0μF ±0%, 0V X5R ceramic capacitors (06) TDK C6X5RA06K D, D, D Green LEDs (060) DESIGNATN QTY DESCRIPTN D Red LED (060) FB FB0 0 70Ω at 00MHz ferrite beads, DC 000mA (060) Murata BLM8PG7SHB J, J6 x 0 header sockets J, J7 J LVDS connectors JAE Electronics MX900NQ USB type-b right-angle female receptacle J, J9 0 Not installed, dual-row ( x 5) headers J5, J0 x 6 header sockets J8 0 JU JU0, JU5, JU6, JU9 JU, JU0, JU JU, JU, JU7, JU8, JU JU9 Not installed, USB type-b rightangle female receptacle 9 -pin headers 0 -pin headers Q, Q n-channel MOSFETs (SOT) Fairchild N700 R, R, R6, R7 9.9Ω ±% resistors (00) Maxim Integrated Products
2 DESIGNATN QTY DESCRIPTN R, R, R5 R9, R8, R9, R6 R67 0kΩ ±5% resistors (00) R5, R, R kω ±5% resistors (00) R8, R68 00kΩ ±% resistors (00) R9, R69 00kΩ ±% resistors (00) R0, R, R, R5 R, R, R50, R5 R, R, R, R5, R5, R5 60Ω ±5% resistors (00) Ω ±5% resistors (00) 6 kω ±5% resistors (00) R0, R55, R56 00Ω ±5% resistors (00) R5 R, R70 0 Not installed, resistors (00) T, T Common-mode EMI chokes Würth 709 TP, TP, TP5 Test points (red) TP, TP, TP 6, 0 Not installed, test points U U Deserializer (8 LQFP) Maxim MAX958GCM+ Serializer ( 0 TQFN - E P *) M axi m M AX 957GTL+ DESIGNATN QTY DESCRIPTN U, U U, U U5, U 500mA LDOs (8 TQFN) Maxim MAX95ETA+.V, A LDOs ( 6 TS SOP - EP *) Maxim M AX8869E U E +.V, 00mA LDOs ( 6 S OT) M axi m M AX 888E U T+ U6, U Microcontrollers (6 QFN-EP*) U7, U5 U8, U6 Serial programmable clock generators (6 TSSOP) Cyclone II FPGAs ( TQFP) Altera EPC5TC6N U9, U7 FPGA serial-configuration devices (8 SO) Altera EPCSSI8N Y, Y 8MHz crystals (HCM9) -meter LVDS cable JAE Electronics MX9B-FF-L000 USB high-speed A-to-B cable, 6ft 5 Shunts PCB: MAX957/8 Evaluation Kit+ * FILE DESCRIPTN INSTALL.EXE Installs the EV kit files on your computer MAX957_8.EXE Application program ATUSBHID.DLL USB software library UNINST.INI Uninstalls the EV kit software SUPPLIER PHONE WEBSITE Altera Corp Digital Core Design JAE Electronics, Inc Murata Electronics North America, Inc TDK Corp w w w.com p onent.td k.com Würth Electronik GmbH & Co. KG
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11 JUMPER SETTING DESCRIPTN -* MAX958 PD pin is pulled up to V CC by a kω resistor JU MAX958 PD pin is internally pulled down to ground JU * MAX958 LVDS line probing connector JU * MAX958 LVDS line probing connector JU JU5 JU6 JU7 JU8 JU9 JU0 JU JU JU5 JU6 -* MAX958 ERROR pin is pulled up to V CC by a kω resistor MAX958 ERROR pin is open-drain output -* MAX958 LOCK pin is pulled up to V CC by a kω resistor MAX958 LOCK pin is open-drain output -* MAX958 V CC connected to on-board LDO.V output MAX958 V CC connected to an external power supply -* MAX958 V CC connected to on-board LDO.V output MAX958 V CC connected to an external power supply -* MAX958 V CCPLL connected to on-board LDO.V output MAX958 V CCPLL connected to an external power supply -* MAX958 V CCSPLL connected to on-board LDO.V output MAX958 V CCSPLL connected to an external power supply -* MAX958 V CCLVDS connected to on-board LDO.V output MAX958 V CCLVDS connected to an external power supply - MAX958 is powered by on-board LDO U5, whose V DD input range is.5v to V -* MAX958 is powered by on-board LDO U, whose input is 5V - MAX958 LVDS cable line- connected to VDD -* MAX958 LVDS cable line- connected to ground -* MAX958 RX pin is connected to the on-board emulated ECU RX line MAX958 RX pin is disconnected from the on-board emulated ECU RX line (an external ECU RX line can connect to J-7) -* MAX958 TX pin is connected to the on-board emulated ECU TX line MAX958 TX pin is disconnected from the on-board emulated ECU TX line (an external ECU TX line can connect to J-5)
12 JUMPER SETTING DESCRIPTN JU7 JU8 JU9 JU0 JU JU JU JU JU5 JU6 JU7 JU8 JU9 * - MAX957 SCL/TX pin is pulled up to V CC -* MAX957 SCL/TX pin is pulled up to V CC - MAX957 SDA/RX pin is pulled up to V CC -* MAX957 SDA/RX pin is pulled up to V CC -* MAX957 V CC connected to on-board LDO.V output MAX957 V CC connected to an external power supply -* MAX957 V CC connected to on-board LDO.V output MAX957 V CC connected to an external power supply -* MAX957 V CCFPLL connected to on-board LDO.V output MAX957 V CCFPLL connected to an external power supply -* MAX957 V CCSPLL connected to on-board LDO.V output MAX957 V CCSPLL connected to an external power supply -* MAX957 V CCLVDS connected to on-board LDO.V output MAX957 V CCLVDS connected to an external power supply - MAX957 J6 connector one side connected to V CC -* MAX957 J6 connector one side connected to ground -* MAX957 REM pin connected to V CC (ECU needs to remotely wake up MAX957) - MAX957 REM pin connected to ground -* MAX957 SCL/TX pin is connected to the on-board emulated camera RX line - MAX957 SCL/TX pin is connected to the on-board emulated camera SCL line MAX957 SCL/TX pin is disconnected from the on-board emulated camera (an external camera RX or SCL line might connect to J6-5) -* MAX957 SDA/RX pin is connected to the on-board emulated camera TX line - MAX957 SDA/RX pin is connected to the on-board emulated camera SDA line MAX957 SDA/RX pin is disconnected from the on-board emulated camera (an external camera TX or SDA line may connect to J6-7) - MAX957 is powered by on-board LDO U, whose V DD input range is.5v to V -* MAX957 is powered by on-board LDO U, whose input is +5V - LVDS cable line- connected to VDD -* LVDS cable line- connected to ground JU0 * LVDS line probing connector JU * LVDS line probing connector
13 JU N.C. 5 RX_ 6 TX_IN 7 LOCK 8 PCLK_ 9 VSYNC_ 0 HSYNC_ D5 N.C. C8 C9 C6 J-9 J-9 J-7 J-5 J- J-5 HSYNC_ PCLK_ D8 D9 VSYNC_ RX_ VDD- TX_IN J-7 J- J-0 J-0 J-8 J-6 J- J-6 J-8 J- J J- J- J- J- PD ERROR LOCK J5- J5- J5-5 J5-7 J5-9 J5- J5- J5- J5-6 J5-8 J5-0 J5- J5 J- J- J- J- J J-9 J-9 J-7 J-5 J- J-5 J-7 J- J-0 J-0 J-8 J-6 J- J-6 J-8 J- J- J- J- J- D6 D7 D D5 D D D0 D D D5 D D D0 D MAX958 U VDD- SDI+ SDI- 8 7 CCEN 6 D0 5 D D D D D5 0 D N.C. 5 D7 6 N.C. D9 D8 D D0 5 N.C. 6 SPLL 7 SPLL 8 D 9 D 0 D T R 0kΩ R 0kΩ C7 R 9.9Ω % R 9.9Ω % JU JU N.C. - PD 5 LVDS 6 SDI- 7 SDI+ 8 LVDS 9 PLL 0 PLL ERROR N.C. - PD CCEN - LOCK D GRN LVDS- PLL- RX_ TX_IN LOCK PCLK_ VSYNC_ HSYNC_ D5 -D ERROR SDI- SDI+ D7 D8 D9 D0 D D D D SPLL- CCEN D0 D D D D D5 D6 -C TP JU R5 kω R kω JU R kω JU5 R 60Ω R 60Ω D RED Q ERROR Q RX_FPGA- RX_ JU5 TX_FPGA- TX_IN JU6 -C C7 nf C -D C8 nf C - C9 nf C PLL- C0 nf C SPLL- C nf C5 LVDS- C nf C6
14 SS N.C. 0 JU6 PB7 PE PE5 RESET XTAL XTAL PD0 PD PD PD PD PD5 PD6 PD7 J J- J- J- J U6 AT90USB A AREF PF0 PF PF PF PF PF5 PF6 PF7 PE7 U D- 5 D+ 6 U 7 UCAP 8 VBUS 9 PE 0 PB0 PB PB PB PB 5 PB5 6 PB SHUTDOWN- SUSPEND- PA0 PA PA _ECU XTALIN XTAL INIT_DONE- _ECU CCEN CONFIG- _ECU PE6 INT_UART- TP _ECU XTAL C _ECU _ECU VDD- IN POK SCL_MCU- SDA_MCU- AD0- AD- AD- R Ω C μf R Ω C U7 CY9 6 CLKC SHUTDN/OE 5 VDD S/SUSPEND A AVDD XTALIN SCLK(S) 5 XTAL SDAT(S0) 6 XBUF 7 CLKD 0 CLKA 8 CLKE CLKB C0 5pF Y 8MHz C 5pF XTALIN SHUTDOWN- SUSPEND- C5 SCL_MCU- SDA_MCU- CLK_UART- C R kω R kω _ECU U +5V +5V 8 PA AD- C6 7 00μF PA AD- 6 PA5 AD5-5 PA6 AD6- PA7 AD7- PE ALE- TP PC7 PC6 CS_IC- 0 PC5 CS_UART- 9 PC FPGA_RESET- 8 PC STATUS- 7 PC CONF_DONE- C8 6 PC 00μF 5 R0 GRN PC0 60Ω D PE RD- PE0 WR- IN C50 IN POK SHDN N.C. IN C5 IN IN 5 IN 6 RST 7 SHDN MAX95 +.V SET U MAX8869 N.C. SET R8 00kΩ % R9 00kΩ % C7 00μF C9 00μF C5 _ECU C5 - FB - -C FB -D JU7 C56 C5 0μF U5 SHDN MAX888 FB JU8 FB PLL- PLL JU JU9 FB SPLL- SPLL C57 C55 0μF JU0 FB5 LVDS- LVDS A SINGLE 5V POWER SUPPLY IS CONNECTED THROUGH THE 5V AND THE PADS. THE MAX957 POWER SUPPLIES ARE OPTNALLY PROVIDED INDIVIDUALLY
15 _PLL D_PLL _PLL CLK CLK5 CLK6 CLK7 MSEL0 MSEL CONF_DONE STATUS CEO INIT_DONE A_PLL A_PLL INT INT ASDO ASDI- CSO CRC_ERROR CLKUSR _ECU _ECU _ECU TX_FPGA- RX_FPGA- _ECU _ECU _ECU _ECU FPGA_RESET- _ECU INT_UART- WR- RD- +.V +.V ALE- AD7- AD6- AD5- AD- _ECU AD- AD- AD- AD0- CLK_UART- _ECU CONF_DONE- INIT_DONE- STATUS- _ECU SYNC_ECU AD- AD- AD0- TDO TMS TCK TDI DATAO DCLK DATA- DCLK- CE CE- CLK0 CLK CONFIG CLK CLK R7 0kΩ R8 0kΩ R5 0kΩ R0 00Ω R6 0kΩ R9 0kΩ +.V +.V.V +.V _PLL O_PLL _PLL INT INT A_PLL A_PLL CS DATA CS- DATA- C DCLK ASDI DCLK- U9 J EPCS _ECU ASDI- C C C5 C6 C7 C8 C9 C0 C C C C C5 C 6 C7 C8 C9 C0 DCLK- J- J- J-5 J-7 J-9 J- J- J-6 J-8 J-0 CONFIG- DATA- ASDI- CONF_DONE- CE- CS- _ECU _ECU +.V CS- CONFIG- CS_UART- CS_C- EPC5T U8
16 6 JU9 DIN9/GP DIN0/GP 5 DIN/GP 6 DIN/GP 7 DIN/GP5 8 DIN/GP6 9 FPLL 0 FPLL 0 DIN0 7 SDO+ 8 LVDS 9 REM SDA/RX 6 SCL/TX 5 PCLK_IN VSYNC_IN HSYNC_IN DIN5/GP7 C77 C78 R7 C66 nf C75 C68 nf C6 C65 C7 nf J6- J6- J6- J6-5 J6-7 J6-5 DIN7 DIN8 PCLK_IN VDD DIN6 DIN DIN0 DIN DIN DIN5 DIN J6- J6-9 J6- J6- J6- J6-6 J6-8 J6-6 J6- J6-0 J6 J6-7 J6-9 J6-8 J6-0 DIN9 J0- J0- J0-7 J0-5 J0- J0-9 J0- J0- J0-8 J0-6 J0- J0-0 J0 J7- J7- J7- J7- J7 J6- J6- J6- J6-5 J6-7 J6-5 J6- J6-9 J6- J6- J6- J6-6 J6-8 J6-6 J6- J6-0 J6-7 J6-9 J6-8 J6-0 MAX957 U HSYNC_IN VSYNC_IN C59 C67 nf C60 0 DIN8/GP0 DIN8 DIN0 DIN DIN DIN VDD SDO+ SDO- DIN PCLK_IN DIN5 FPLL R R -A 9 DIN7 DIN7 R 8 DIN6 DIN6 R 7 DIN5 DIN5 R0 6 DIN DIN R9 5 DIN DIN R8 DIN DIN R6 R5 DIN SDO+ 6 SDO- 5 LVDS SPLL SPLL GP9 GP8 SDO- LVDS SPLL DIN DIN0 R R R70 R kω R5 kω R JU7 RX_FPGA SCL_FPGA JU6 -B C69 nf C6 JU8 TX_FPGA SDA_FPGA JU7 JU DIN5 R0 DIN DIN DIN DIN DIN0 R9 R8 R7 R6 R5 C7 nf C6 TP TP5 JU5 C70 nf C6 T R8 0kΩ R9 0kΩ C76 R6 9.9Ω % R7 9.9Ω % JU0 JU
17 PB7 PE PE5 RESET XTAL XTAL PD0 PD PD PD PD PD5 PD6 PD7 J8 J8- J8- J8- J8- _CAMERA C79 _CAMERA U +5V MAX95 SCL_MCU SDA_MCU SHUTDOWN SUSPEND A AREF PF0 PF PF PF PF PF5 PF6 PF7 PA0 PA PA SYNC_OE AD0 AD AD _CAMERA XTAL XTAL R5 Ω C8 μf +5V 8 INIT_DONE PE6 PA AD C0 7 00μF PE7 PA AD R50 Ω 6 U PA5 AD5 5 D- PA6 AD6 5 D+ PA7 AD7 6 U PE ALE _CAMERA 7 TP7 UCAP U PC7 8 VBUS AT90USB8 PC6 CS_IC 9 0 PE PC5 CS_UART 0 9 PB0 PC FPGA_RESET 8 PB PC STATUS 7 PB PC CONF_DONE 6 PB PC 5 R5 GRN PC0 PB 60Ω D 5 PE RD PB5 C0 6 PE0 WR CONFIG PB6 00μF INT_UART INT_IC R5 TP6 kω _CAMERA Y 8MHz XTAL C80 C8 C8 5pF 5pF R5 kω XTAL _CAMERA VDD U5 C 0μF CY9 6 CLKC SHUTDN/OE 5 VDD S/SUSPEND C A AVDD XTALIN SCLK(S) 5 XTAL SDAT(S0) 6 XBUF 7 0 CLKD CLKA 8 CLKE CLKB SHUTDOWN SUSPEND SCL_MCU SDA_MCU CLK_UART CLK_IC _CAMERA C5 IN C06 IN POK SET SHDN U MAX N.C. N.C. 5 IN C08 IN IN IN C0 C C 0μF 5 IN 6 RST SET 7 0 SHDN SS N.C. POK U SHDN MAX888 FB A SINGLE 5V POWER SUPPLY IS CONNECTED THROUGH THE 5V AND THE PADS. THE MAX957 POWER SUPPLIES ARE OPTNALLY PROVIDED INDIVIDUALLY. +.V C0 C07 R68 00μF 00kΩ % R69 00kΩ % _CAMERA C05 C09 00μF JU9 FB6 -A FB7 -B JU0 JU FB8 FPLL FPLL JU8 JU FB9 SPLL SPLL JU FB0 LVDS LVDS
18 EPC5T _PLL D_PLL _PLL CLK CLK5 CLK6 CLK7 MSEL0 MSEL CONF_DONE STATUS CEO INIT_DONE A_PLL A_PLL INT INT ASDO ASDI CSO CRC_ERROR CLKUSR _CAMERA _CAMERA _CAMERA TX_FPGA SCL_FPGA SDA_FPGA RX_FPGA _CAMERA _CAMERA _CAMERA _CAMERA _CAMERA FPGA_RESET _CAMERA INT_UART INT_C WR RD.V.V ALE AD7 AD6 AD5 AD _CAMERA AD AD AD AD0 CLK_UART CLK_C _CAMERA CONF_DONE INIT_DONE STATUS _CAMERA SYNC_OE VSYNC_IN HSYNC_IN PCLK_IN AD AD AD0 TDO TMS TCK TDI DATAO DCLK DATA DCLK CE CE CLK0 CLK CONFIG U6 CLK CLK R6 0kΩ R67 0kΩ R56 00Ω R55 00Ω R66 0kΩ R65 0kΩ.V.V.V.V _PLL O_PLL _PLL INT INT A_PLL A_PLL CS DATA CS DATA C6 DCLK ASDI DCLK U7 J9 EPCS _CAMERA ASDI C0 C96 C95 C9 C9 C9 C9 C90 C89 C88 C87 C86 C85 C8 C97 C98 C99 C00 DCLK J9- J9- J9-5 J9-7 J9-9 J9- J9- J9-6 J9-8 J9-0 CONFIG DATA ASDI CONF_DONE CE CS _CAMERA _CAMERA.V CS CONFIG CS_UART CS_C R6 0kΩ
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