R1LV1616H-I シリーズ

Transcription

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2 OA AV RoHS

3 Wide Temperature Range Version 16M SRAM (1-Mword 16-bit / 2-Mword 8-bit) RJJ03C Rev M 16 2-M 8 16M RAM CMOS 6 48 TSOPI 3.0V 2.7V 3.6V 45/55ns max 9mW/MHz typ 1.5µW typ 2 CS C BYTE# A-1 Byte 8 Rev.1.01, , page 1 of 19

4 Type No. Access time Package R1LV1616HSA-4LI 45 ns 48-pin plastic TSOPI (48P3R-B) R1LV1616HSA-4SI 45 ns R1LV1616HSA-5SI 55 ns Rev.1.01, , page 2 of 19

5 Rev.1.01, , page 3 of A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# CS2 NU UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE# V I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 V I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE# V CS1# A0 CC SS SS (Top view) 48-pin TSOP

6 A0 to A19 Pin name (TSOP) Address input (word mode) A-1 to A19 Address input (byte mode) I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 WE# (WE) OE# (OE) LB# (LB) UB# (UB) BYTE# (BYTE) V CC V SS NC NU* 1 Write enable Output enable Lower byte select Upper byte select Byte enable Power supply Ground No connection Not used (test mode pin) Function 1. Rev.1.01, , page 4 of 19

7 (TSOP) LSB MSB A15 A14 A13 A12 A11 A10 A9 A8 A18 A16 A19 A4 A5 Row decoder Memory matrix 8,192 x 128 x 16 8,192 x 256 x 8 V CC V SS I/O0 Column I/O Input data control Column decoder I/O15 MSBA17A7A6 A3 A2 A1A0 A-1 LSB BYTE# CS2 CS1# LB# UB# WE# Control logic OE# Rev.1.01, , page 5 of 19

8 (TSOP) Byte mode CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 I/O8 to I/O14 I/O15 Operation H L High-Z High-Z High-Z Standby L L High-Z High-Z High-Z Standby L H H L L Dout High-Z A-1 Read L H L L Din High-Z A-1 Write L H H H L High-Z High-Z High-Z Output disable H: V IH, L: V IL, : V IH or V IL Word mode CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 I/O8 to I/O14 I/O15 Operation H H High-Z High-Z High-Z Standby L H High-Z High-Z High-Z Standby H H H High-Z High-Z High-Z Standby L H H L L L H Dout Dout Dout Read L H H L H L H Dout High-Z High-Z Lower byte read L H H L L H H High-Z Dout Dout Upper byte read L H L L L H Din Din Din Write L H L H L H Din High-Z High-Z Lower byte write L H L L H H High-Z Din Din Upper byte write L H H H H High-Z High-Z High-Z Output disable H: V IH, L: V IL, : V IH or V IL Rev.1.01, , page 6 of 19

9 Parameter Symbol Value Unit Power supply voltage relative to V SS V CC 0.5 to +4.6 V Terminal voltage on any pin relative to V SS V T 0.5* 1 to V CC + 0.3* 2 V Power dissipation P T 1.0 W Storage temperature range Tstg 55 to +125 C Storage temperature range under bias Tbias 40 to +85 C 1. 10ns 2.0V(Min) V DC Parameter Symbol Min Typ Max Unit Note Supply voltage V CC V V SS V Input high voltage V IH 2.2 V CC V Input low voltage V IL V 1 Ambient temperature range Ta C 1. 10ns 2.0V(Min) Rev.1.01, , page 7 of 19

10 DC Parameter Symbol Min Typ Max Unit Test conditions* 2 Input leakage current I LI 1 µa Vin = V SS to V CC Output leakage current I LO 1 µa CS1# = V IH or CS2 = V IL or OE# = V IH or WE# = V IL or LB# = UB# = V IH, V I/O = V SS to V CC Operating current I CC 20 ma CS1# = V IL, CS2 = V IH, Others = V IH / V IL, I I/O = 0 ma Average operating current I CC1 (READ) 22* 1 35 ma Min. cycle, duty = 100%, I I/O = 0 ma, CS1# = V IL, CS2 = V IH, WE# = V IH, Others = V IH /V IL I CC1 30* 1 50 ma Min. cycle, duty = 100%, I I/O = 0 ma, CS1# = V IL, CS2 = V IH, Others = V IH /V IL I CC2 * 3 (READ) 3* 1 8 ma Cycle time = 70 ns, duty = 100%, I I/O = 0 ma, CS1# = V IL, CS2 = V IH, WE# = V IH, Others = V IH /V IL Address increment scan or decrement scan I CC2 * 3 20* 1 30 ma Cycle time = 70 ns, duty = 100%, I I/O = 0 ma, CS1# = V IL, CS2 = V IH, Others = V IH /V IL Address increment scan or decrement scan I CC3 3* 1 8 ma Cycle time = 1 µs, duty = 100%, I I/O = 0 ma, CS1# 0.2 V, CS2 V CC 0.2 V V IH V CC 0.2 V, V IL 0.2 V Standby current I SB 0.1* ma CS2 = V IL Standby current -4SI I SB1 0.5* 1 8 µa 0 V Vin -5SI -4LI I SB1 0.5* 1 25 µa (1) 0 V CS2 0.2 V or (2) CS1# V CC 0.2 V, CS2 V CC 0.2 V or (3) LB# = UB# V CC 0.2 V, CS2 V CC 0.2 V, CS1# 0.2 V Average value Output high voltage V OH 2.4 V I OH = 1 ma V OH V CC 0.2 V I OH = 100 µa Output low voltage V OL 0.4 V I OL = 2 ma V OL 0.2 V I OL = 100 µa Rev.1.01, , page 8 of 19

11 1. Typ V CC = 3.0V Ta = +25 C 2. BYTE# V CC 0.2 V or BYTE# 0.2 V 3. increment decrement Word mode: LSB (least singnificant bit) A0 Byte mode: LSB (least singnificant bit) A-1 Ta = +25 C f = 1MHz Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pf Vin = 0 V 1 Input/output capacitance C I/O 10 pf V I/O = 0 V 1 1. Rev.1.01, , page 9 of 19

12 AC V CC = 2.7V 3.6V Ta = C V IL = 0.4V, V IH = 2.4V 5ns 1.4V 1.4 V Dout RL=500 Ω 50pF Rev.1.01, , page 10 of 19

13 R1LV1616H-I -4SI, -4LI -5SI Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC ns Address access time t AA ns Chip select access time t ACS ns t ACS ns Output enable to output valid t OE ns Output hold from address change t OH ns LB#, UB# access time t BA ns Chip select to output in low-z t CLZ ns 2, 3 t CLZ ns 2, 3 LB#, UB# enable to low-z t BLZ 5 5 ns 2, 3 Output enable to output in low-z t OLZ 5 5 ns 2, 3 Chip deselect to output in high-z t CHZ ns 1, 2, 3 t CHZ ns 1, 2, 3 LB#, UB# disable to high-z t BHZ ns 1, 2, 3 Output disable to output in high-z t OHZ ns 1, 2, 3 Rev.1.01, , page 11 of 19

14 R1LV1616H-I -4SI, -4LI -5SI Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC ns Address valid to end of write t AW ns Chip selection to end of write t CW ns 5 Write pulse width t WP ns 4 LB#, UB# valid to end of write t BW ns Address setup time t AS 0 0 ns 6 Write recovery time t WR 0 0 ns 7 Data to write time overlap t DW ns Data hold from write time t DH 0 0 ns Output active from end of write t OW 5 5 ns 2 Output disable to output in high-z t OHZ ns 1, 2 Write to output in high-z t WHZ ns 1, 2-4SI, -4LI R1LV1616H-I Parameter Symbol Min Max Min Max Unit Notes BYTE# setup time t BS 5 5 ms BYTE# recovery time t BR 5 5 ms 1. t CHZ t OHZ t WHZ t BHZ t HZ max t LZ min 4. CS1# Low CS2 High WE# Low LB# UB# Low t WP CS1# Low CS2 High WE# Low LB# UB# Low CS1# High CS2 Low WE# High LB# UB# High t WP 5. t CW CS1# Low CS2 High 6. t AS 7. t WR WE# CS1# High CS2 Low -5SI Rev.1.01, , page 12 of 19

15 * 1 t RC Address* 2 Valid address t AA CS1# tacs1 t CLZ1 t CHZ1 CS2 t ACS2 t CLZ2 t CHZ2 t BHZ LB#, UB# t BA t BLZ t OHZ OE# t OE t OLZ t OH Dout* 3 High impedance Valid data Notes: 1. BYTE# > V CC 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.01, , page 13 of 19

16 (1) * 1 (WE# Clock) t WC Address* 2 Valid address t CW t WR CS1# t CW CS2 t BW LB#, UB# t AW WE# t AS t WP t DW t DH Din* 3 Dout* 3 t WHZ Valid data High impedance t OW Notes: 1. BYTE# > V CC 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.01, , page 14 of 19

17 (2) * 1 (CS1#, CS2 Clock, OE# = V IH ) t WC Address* 2 Valid address t AW t AS t CW t WR CS1# t AS t CW CS2 t BW LB#, UB# WE# t WP t DW t DH Din* 3 Valid data Dout* 3 High impedance Notes: 1. BYTE# > V CC 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.01, , page 15 of 19

18 (3) * 1 (LB#, UB# Clock, OE# = V IH ) t WC Address Valid address t AW t CW t WR CS1# t CW CS2 t AS t BW UB# (LB#) t BW LB# (UB#) WE# t WP t DW t DH Din-UB (Din-LB) Valid data t DW t DH Din-LB (Din-UB) Dout High impedance Valid data Note: 1. BYTE# > V CC 0.2 V Rev.1.01, , page 16 of 19

19 (TSOP) CS2 CS1# t BS t BR BYTE# Rev.1.01, , page 17 of 19

20 Ta = C Parameter Symbol Min Typ Max Unit Test conditions* 2, 3 V CC for data retention V DR V Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 V CC 0.2 V, CS1# V CC 0.2 V or (3) LB# = UB# V CC 0.2 V, CS2 V CC 0.2 V, CS1# 0.2 V Data retention current Chip deselect to data retention time -4SI -5SI I CCDR 0.5* 1 8 µa -4LI I CCDR 0.5* 1 25 µa V CC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 V CC 0.2 V, CS1# V CC 0.2 V or (3) LB# = UB# V CC 0.2 V, CS2 V CC 0.2 V, CS1# 0.2 V Average value t CDR 0 ns See retention waveforms Operation recovery time t R 5 ms 1. Typ V CC = 3.0 V Ta = +25 C 2. BYTE# V CC 0.2 V or BYTE# 0.2 V 3. CS2 WE# CS1# OE# LB# UB# Din CS2 Vin WE# CS1# OE# LB# UB# I/O High-Z CS1# CS2 CS2 V CC 0.2 V 0 V CS2 0.2 V WE# OE# LB# UB# I/O High-Z Rev.1.01, , page 18 of 19

21 (1) (CS1# Controlled) V CC 2.7 V t CDR Data retention mode t R 2.2 V V DR CS1# 0 V CS1# V CC 0.2 V (2) (CS2 Controlled) V CC 2.7 V CS2 tcdr Data retention mode t R V DR 0.6 V 0 V 0 V < CS2 < 0.2 V (3) (LB#, UB# Controlled) V CC 2.7 V t CDR Data retention mode t R 2.2 V V DR LB#, UB# 0 V LB#, UB# V CC 0.2 V Rev.1.01, , page 19 of 19

22 Rev M 8

23 ( ( ) (03) ( ) (044) ( 2F) (042) ( 5F) (011) ( 13F) (022) ( 3F) (0246) ( 1F) (029) ( 3F) (025) ( 7F) (0263) ( 4F) (052) F (053) ( ) (06) ( 8F) (076) ( 8F) (082) ( ) (0857) ( 5F) (092) ( ) (099) csc@renesas.com Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 3.0