Fig. 1 Relative delay coding.

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1 An Architecture of Small-scaled Neuro-hardware Using Probabilistically-coded Pulse Neurons Takeshi Kawashima, Non-member (DENSO CORPORATION), Akio Ishiguro, Member (Nagoya University), Shigeru Okuma, Member (Nagoya University, Nagoya Industrial Science Research Institute) In this paper, we present an architecture of a neuro-hardware that can be realized on by far a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probability properties into relative delay between two pulses. Proposed architecture enables to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to conventional architecture. 586 T. IEE Japan, Vol. 121-C, No. 3, 2001

2 Fig. 1 Relative delay coding.

3 Fig.2 Approximation of sigmoidal function by normal distribution function. Fig.3 Principle of the calculation of a sigmoidal function. 588 T. IEE Japan, Vol. 121-C, No.3, 2001

4 p(t)=min(t+xm+1,xm) -max(t-x M,-xM-1)+1 c c c c c c c (13) S' `ƒ s1+x2=s'fi(x1)f2(x2) c c c c c c c (14) Fig.4 The normal distribution and an example of normal random numbers.

5 Fig. 5 Circuit diagram of the proposed pulse neuron. Fig. 6 Detailed circuit diagram of the proposed pulse neuron. 590 T. IEE Japan, Vol. 121-C, No. 3, 2001

6 Fig. 7 Quantitative comparison of the resultant hardware-scale between the proposed and conventional methods.

7 Fig. 8 NN for the EX-OR problem. (2) T. Schoenauer, A. Jahnke, U. Roth, and H. Klar: Digital Neurohardware: Principles and Perspectives, Neuronal Networks in Applications -NN'98, pp pp. 106 (1998) (3) Hammerstorm. D.: A highly parallel digital architecture for neural network emulation. In: Delgado-Frias, J. G. and Moore, W. R., VLSI for Artificial Intelligence and Neural Networks, Plenum Press (1991) (4) M. Marchesi, G. Orlandi, F. Piazza, L. Pollonara, and A. Uncini: Multi-layer Perceptrons with Discrete Weights, proceedings of IJCNN'90, Vol. 2, pp (1990) Fig. 9 An output of NN for the EX-OR problem by numerical calculation. (6) Wolfgang Maass, Christofer M. Bishop: Pulsed Neural Networks, The MIT Press (1999) (7) M. Yasunaga, N. Masuda, M. Asai, M. Yamada, A. Masaki, and Y. Hirai: A wefer scale integration neural network utilizing completely digital circuits, proceedings of IJCNN'89, Vo1. 2, pp (1989) (8) H. Eguchi, T. Furuta, H. Horiguchi, S. Oteki, and T. Kitaguchi: Neural network LSI chip with on-chip learning, proceedings of IJCNN'91, Vol. 1, pp (1991) (9) M. S. Tomlinson Jr., D. J. Walker, and M. A. Sivilotti: A Digital Neural Network Archiecture for VLSI, proceedings of IJCNN'90, Vol. 2, pp (1990) (10) A. F. Murray, "Pulse-Stream D. Del Corso, and VLSI Neural Networks LTarassenko, Mixing Analog and Digital Techniques", IEEE Trans. on Neural Networks, Vol. 2, No. 2,, pp (1991) (11) M. Chiaberge, E. Miranda Sologuren, L. M. Reyneri, "A Pulse Stream System for Low Power Neuro-Fuzzy Computation", IEEE Trans. on Circuits and Systems -I, Fig. 10 An output of proposed NN for the EX-OR Vol. 42, No. 11, pp (1995) problem. 592 T. IEE Japan, Vol. 121-C, No. 3, 2001

8 (13) H.Fujii, H. Ito, KAihara, N. Ichinose, and M. Tsukada: Dynamical Cell Assembly Hypothesis -Theoretical Possibility of Spatio-temporal Coding in the Cortex -, Neural Networks, Vol. 9, No. 8, pp (1996)

EQUIVALENT TRANSFORMATION TECHNIQUE FOR ISLANDING DETECTION METHODS OF SYNCHRONOUS GENERATOR -REACTIVE POWER PERTURBATION METHODS USING AVR OR SVC- Ju

EQUIVALENT TRANSFORMATION TECHNIQUE FOR ISLANDING DETECTION METHODS OF SYNCHRONOUS GENERATOR -REACTIVE POWER PERTURBATION METHODS USING AVR OR SVC- Jun Motohashi, Member, Takashi Ichinose, Member (Tokyo