Schematic Protel 99 SE
Protel 99 SE Protel 99 SE 基本操作 回路図入力 ( ) ( / ) 応用操作 & ( ) 1
( ) ( ) ( ) (ERC) I/O ( ) PCB PCB UpDate PCB プリント / プロットアウト / 2
Protel 99 SE Protel 99 SE Protel 99 SE DDB() Protel 99 SE DDB DDB File>>New Design(>>) New Design Database Database Location DDB Browse Database File Name DDB OK DDB DDB() DDB DDB 3 Design Team 1 Recycle Bin Documents 3
DDB File>>New( >> ) DDB Schematic Document OK ( )(DDB) Browse sch Protel 99 SE 4
Protel 99 SE DDB DDB Close DDB Split Vertical Split Horizontal PCB Merge All 5
Protel 99 SE DDB Protel DDB (DDB) DDB 1. DDB 2. Export 3. Protel 99 SE Protel Protel 99 SE DDB Protel Protel 99 SE DDB DDB 1. File>>Import(>> ) 2. DDB (DDB) Protel 99 SE DDB (DDB) (DDB) DDB 1. DDB DDB 2. DDB DDB 3. 6
Protel 99 SE PAGE UP PAGE DOWN END HOME View( ) >> V - F >> V - D >> V - A Protel (V) V (V) D (D) ( ) / View( ) >> >> >> >> ( ) / / / / 7
Protel Miscellaneous Devices.ddb Place Filter R* ENTER R ( ) 90 X X ( ) Y Y ( ) () Tools>>Preferences( >>) Graphical Editing Auto Pan Speed ( ) Tab ( 1 ) 8
Protel 99 SE ( ) Tab Designator R1 PartType 1k RESPACK1 1 R1A, R1B, R1C (RESPACK3 REPACK1 1 ) Tools>>Preferences( >>) Multi-Part Suffix Numeric 9
Add/Remove Design>>Add/Remove Library(>> ) ddb Add Design Exproler 99 SE Library Sch Protel 99 SE Miscellaneous Devices.ddb ( ) Add Selected Files OK Find Tools>>Find Component( >>) By Library Reference Find Now 7400 *74*00* 7400 (74HC00 74LS00 ) 10
Protel 99 SE 2 Place( ) CPUCLK INT A[0..15] RD IORQ M1 RESET SIOSEL CPUCLK INT A[0..15] RD IORQ M1 RESET SIOSEL D[0..7] D[0..7] A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 VCC 20 7 6 5 34 33 32 36 8 21 35 40 1 39 2 38 3 37 4 Serial Baud Clock Serial Baud Clock.sch U6 CLK IEO IEI INT B/A C/D RD IORQ M1 RESET CE D0 D1 D2 D3 D4 D5 D6 D7 Z80ASIO0 BAUDCLK DCDB DTRB CTSB RTSB W/RDYB SYNCB TXDB RXTXCB RXDB DCDA DTRA CTSA RTSA W/RDYA SYNCA TXCA TXDA RXCA RXDA 22 25 23 24 30 29 26 27 28 19 16 18 17 10 11 14 15 13 12 1. Place>>Wire ( >>) 2. 3. 90 45 Backspace 11
( ) Delete 1. Place>>NetLabel( >>) 2. Tab 3. OK / CLK ( ) 1. Place>>Power Port( >> ) 2. Tab 3. OK / (Style) View>>ToolBars>>Power Objects( >> >> ) 12
Protel 99 SE 1. Place>>Bus( >> ) 2. Data0 Data7 Data[0..7] Data[7..0] ( ) Place>>Bus Entry( >> ) 1. Place>>Port( >> ) 2. Tab Name( ) Style( ) I/O Type( ) OK 3. 4. ( ) I/O Type( ) ERC( ) Style( ) I/O Type( ) 13
No-ERC No-ERC No-ERC ERC No ERC Place>>Directives>>No ERC( >> >>No ERC) PCB PCB (PCB Protel PCB ) PCB Place>>Directives>>PCB Layout( >> >>PCB ) Track width Via width Routing topology Routing priority Routing layer Track Width( ) Via width() (mm mil) PCB ( ) 14
Protel 99 SE Delete Edit>>Delete( >> ) Edit>>Clear( >> ) Ctrl Delete Edit>>DeSelect>>All( >> >> ) ( X - A ) X Y () Edit>>Move>>Drag( >> >>) ( M - D ) =>90 =>45 Edit>>Move>>Drag Selection( >> >> ) ( M - R ) 15
Tools>>Preferences( >>) ( ) ( ) & ( ) () 1. 2. Edit>>Copy( >> ) 3. Edit>>Paste( >>) 4. Edit>>DeSelect>>All( >>>> ) ( ) () 1. 2. Edit>>Paste Array( >> ) 3. Item Count Text Increment Horizontal Vertical X( ) Y( ) 4. OK 5. 6. Edit>>DeSelect>>All( >>>> ) 16
Protel 99 SE 2 Libraries Primitives Primitives Edit Jump Open All Protel Edit>>Export To Spread( >> ) Next> File>>Update(>> ) 17
Tools>>Annotate( >>) Annotate Options Annotate Options All Parts? Parts ( :R?, C?, U?) Reset Designators R?, C?, U? Update Sheet Number Only ( 19 ) Current sheet only Ignore selected parts Re-annotate Method Advanced Options Addvanced Options From To Suffix ( ) 18
Protel 99 SE Design>>Options(>> ) Sheet Options Document Options Sheet Options Document Option Sheet Options Standard Style 18 Standard Style Use Custom Style Standard Style ( 1=1/100 ) SnapOn Visible 1=1/100 Organization Organization Document Option Organization 19
Place>>Anotation( >>) Tab.ADDRESS1 1.ADDRESS2 2.ADDRESS3 3.ADDRESS4 4.DATE.DOC_FILE_NAME.DOC_FILE_NAME_NO_PATH ( ).DOCUMENTNUMBER.ORGANIZATION.REVISION.SHEETNUMBER.SHEETTOTAL.TIME.TITLE Microsoft Word ( ) Design>>Templates>>Set Template File(>>>> ) Protel 99 SE Design Explorer 99 SE System Templates.Ddb 20
D C B A D C B A 1 1 2 2 VDD RC1 RC2 VDD 10K 10K CLOAD1 OUT1 RC1 OUT2 RC2 10K 10K 5pF CLOAD1 RS1 1K 3 Q1 OUT1 Q2 OUT2 2 RS2 q2n2222 q2n2222 1K Input 5pF RS1 1K 3 Q1 Q2 RS2 5 2 RBIAS V1 q2n2222 q2n2222 1K 20K VSIN Input 1 5 RBIAS V1 Q4 20K VSIN q2n2222 Q3 q2n2222 1 Q4 q2n2222 V2 Q3 q2n2222 VDD VEE VSRC V2.SPICE V3 * PSPICE Simple Analog Example VDD VEE.tran 5ns 3us VSRC VEE.four 1Meg V([OUT2]).SPICE VSRC.TEMP 35 V3.OP * PSPICE Simple Analog Example.lib nom.lib.tran 5ns 3us VEE.probe.four 1Meg V([OUT2]) VSRC.TEMP 35.OP.lib nom.lib.probe Title Size Number Revision Title A Date: 2-Apr-1997 Sheet of File: SizeE:\TEMP\STEP7_1.SCH Number Drawn By: Revision 1 2 3 A 4 Date: 2-Apr-1997 Sheet of File: E:\TEMP\STEP7_1.SCH Drawn By: 1 2 3 4 3 3 4 4 D C B A D C B A Protel 99 SE 1 1 1 DDB File>>New Document(>> ) Schematic Library OK 21
Component_1 Tools>>Rename Component( >>) OK 2 SchLibDrawingTools Place>>Pin( >> ) Tab Pin Name Pin Number Dot Symbol Clk Symbol Electrial Type Hidden ERC( ) ()Name... IC Edit>>Move>>Send To Back( >> >> ) Bring To Front( ) 1 Tools>>New Part( >>) 2 Part 1/1 2/2 7400 NAND 22
Protel 99 SE 1 Protel Normal De-Morgan IEEE 3 1 3 Mode TI Databooks.ddb SN7400 1 4 Normal De-Morgan IEEE 3 Normal () Tab Graphical Attrs Mode Protel 1 1 Group Add 1 Tools>>Description( >>) Default Designator ( : U? IC? ) Sheet Part File Name Description FootPrint 1-4 PLD FPGA PCB ( ) 4 4 1 23
2 ( ) Protel 99 278 Copy Paste Copy Paste 1. 2. Update Schematic Tools>>Update Schematics( >>) Design>>Update Parts In Cache(>>) 24
Protel 99 SE 1 Protel 1. DDB File>>New Documents(>> ) 2. Design>>Create Symbol From Sheet(>>) 3. 4. No( ) 5. F5 Protel 3 ( ) PCB ERC Net Identifier Scope Only Ports Global ( ) PCB ERC Net Identifier Scope NetLabels and Ports Global ( ) 25
( ) PCB ERC Net Identifier Scope SheetSymbol / Ports Connection Report>>Add Port Reference (>> ) 2 Add Port References Flat ( ) Add Port References Hierarchical ( ) Report>>Remove Port Reference(>> ) Up Down Hirarchy 1. Tools>>Up Down Hirarchy( >>) 2. ( ) 26
Protel 99 SE (ERC) ERC Tools>>ERC( >> ) Setup Electrical Rule Check Setup Setup Electrical Rule Check Setup PCB ERC Net Identifier Scope Rule Matrix Rule Matrix () ( ) ( ) Input Pin Output Pin 27
PCB Update PCB PCB Design>>Update PCB(>>PCB ) Update Design Preview Changes Update Design PCB Only Show Errors Execute PCB Connectivity Only Show Errors Report Protel 99 SE PCB PCB Output Format Net Identifier Scope 30 PCB CAD 28
Protel 99 SE Reports>>Bill of Material(>> ) Protel 3 Protel CSV BOM Windows CSV Microsoft Excel Lotus 123 Client Spread Sheet Protel Microsoft Excel DDB ( 6 ) File>>Setup Printer(>> ) Batch Type Color Mode Margin Scale Scale To Fit Page Include on Printout 1% 400% Scale To Fit Page PCB No ERC Vector Font Options Print Left Right Top Bottom 0 Refresh 29
Protel Altium Limited 141-0031 1-23-9 7F TEL: 03-5436-2501 FAX: 03-5436-2505 ( : 10:00 12:00 13:00 17:00) Protel : protel.support@altium.co.jp Protel web : http://www.protel.co.jp/ : http://www.protel.com/ 2001/10/16 30
Schematic