スライド 1

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10 VHDL 10

11 VHDL 4 Decode cnt = "1010" High Low DOUT CLK 25MHz 50MHz clk_inst Cnt[3:0] RST

12 library ieee; library xp; use xp.components.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity top is port( ); end; architecture behavioral of top is RST,CLK : in std_logic; DOUT : out std_logic component pll_inst port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); end component; signal cnt : std_logic_vector(3 downto 0); signal clk_inst : std_logic; signal lock : std_logic; signal pll_rst : std_logic; begin VHDL pll_rst <= not RST; -- parameterized module component instance PLL_UUT : pll_inst port map (CLK => CLK, RESET => pll_rst, CLKOP => clk_inst, LOCK => lock); process(clk_inst,rst) begin if((rst = '0') or (lock = '0'))then cnt <= (others => '0'); elsif(clk_inst'event and clk_inst = '1')then cnt <= cnt + 1; end if; end process; DOUT <= '1' when cnt = "1010" else '0'; end behavioral; 12

13 ( ) 1. Place & Route Timing Checkpoint Start 2. [Start] ( ) ( ) ( ) 13

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16 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY tb_top IS END tb_top; ARCHITECTURE behavior OF tb_top IS BEGIN COMPONENT top PORT( RST : IN std_logic; CLK : IN std_logic; DOUT : OUT std_logic ); END COMPONENT; SIGNAL RST : std_logic; SIGNAL CLK : std_logic := '0'; SIGNAL DOUT : std_logic; uut: top PORT MAP( RST => RST, CLK => CLK, DOUT => DOUT ); CLK <= not (CLK) after 20 ns; 25MHz 10ns RST = 0 RST = 1 process begin end process; END; RST <= '0'; wait for 10 ns; RST <= '1'; wait; 16

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18 1.Project Navigator VHDL Functional Simulation With Aldec Active-HDL or VHDL Post-Route Functional Simulation With Aldec Active-HDL or VHDL Post-Route Timing Simulation With Aldec Active-HDL Active-HDL 2.Active-HDL 18

19 3. Undock wave wave view 19

20 RST 20

21 uut uut cnt0 cnt3 Cntl 21

22 [ ] [Merge Signals] + 22

23 restart Run restart 23

24 uut cnt cnt 24

25 General OK ( Binary ) cnt Properties Binary 25

26 Display OK Display Height Color Bold Shape Literal Logic High Low Analog 26

27 General Edit Aliases Signal Alias Editor Alias_name Value Mnemonic cnt Signal Alias Use Alias Signal Alias Editor 27

28 Waveform editor Zoom Mode 28

29 Measurement Mode 4.6ns 29

30 Active-HDL GUI Files Console Active-HDL do -tcl ( ).fado VHDL Functional Simulation do -tcl ( ).xado VHDL Post-Route Functional Simulation do -tcl ( ).xado VHDL Post-Route Timing Simulation do -tcl.vado Velirog Functional Simulation do -tcl. ado Velirog Post-Route Functional Simulation do -tcl.wado Velirog Post-Route Timing Simulation 30

31 Active-HDL Stimulators Typer Typer Display Paths Apply CLK Type Clock 10MH 31

32 Signal Breakpoints cnt_3 Simulation Breakpoints 32

33 -break always : -break when less : Hit count -break when equal : Hit count -break when grater : Hit count -break when multiple of: Hit count 33

34 run cnt3 = 1 Break run cnt3 = 1 Break 34

35 Active-HDL Active-HDL View Library_Manager Attach Library *.lib Attach as Global Library 35

36 VCD VCD Export File Export Waveforms VCD for Verilogdesign : Verilog VCD VCD for VHDL design : VDHL VCD VCD Lattice Power Calucrator VCD 36

37 JPG BMP GIF PNG File Export Grafics OK 37

38 FAE /FAX URL 38

39 Revision History 39

スライド 1

スライド 1 isplever CLASIC 1.2 Startup Manual for MACH4000 Rev.1.0 isplever_ CLASIC Startup_for_MACH4000_Rev01.ppt Page: 1 1. Page 3 2. Lattice isplever Design Flow Page 4 3. Page 5 3-1 Page 6 3-2 Page 7 3-3 Page