2018 (412837)
4.1 % 7.5 %
Abstract Recently, various methods for improving computial performance have been proposed. One of these various methods is Multi-core. Multi-core can execute processes in parallel by using multiple processors. However, it occurs many memory access simultaneously. As a result, cache miss rate is increased. Moreover, cache miss and memory access are occur at the same time. It is important to reduce memory access, because memory access has interfered with improving the computial performance. One of the methods of reducing cache miss rate is Cache-Partitioning. This method allocates ways to each core on demand. However, because of allocating ways to each cores, in spite of using only specific part of the way, other cores can t use regions which are not used. To solve this problem, our laboratory proposes Cell-Allocation cache. However, Cell-Allocation cache allocates cache capacity to the core which is the worst cache miss rate, hence it may interfere with improving the whole of cache miss rate. To solve this problem,this paper propose the method of allocating cache capacity to the core of lower cache miss rate by using the analysis of the tendency of accessing to cache. As a result, cache miss rate has increased 4.1 % on average and 7.5 % on maximum compared with the conventional Cell-Allocation cache. Therefore, this paper search the causes of increasing cache miss rate and propose the improvement plans.
1 1 2 3 2.1........................... 3 2.2.............. 5 2.3.............. 6 3 8 3.1........... 8 3.2............................. 11 4 13 4.1.................. 13 4.2.................. 15 4.3................. 17 5 21 5.1............................ 21 5.2............................ 21 5.3.............................. 23 6 27 29 29 i
2.1................... 3 2.2........... 5 2.3................... 6 2.4................ 7 3.5......... 8 4.6........................ 14 4.7................ 17 5.8............................ 22 5.9.................. 23 5.10............ 25 ii
5.1............................ 21 iii
1 [1] [2] 1
2
2 2.1 Cache Data : Address A : 33 B : 25 A B Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2.1: [2] 3
index address set mod (1) index = address mod set (1) 2.1 16 A 33 33 mod 16 = 1 B 25 25 mod 16 = 9 (1) 2.1 1 4
2.2 2.2 2.2: [3] 2.1 5
2.3 [1] 2 2.3 2.4 2.3: [3] 6
2.4: [3] 2.3 2.4 7
3 3.1 3.5 Block 0 Block 1 Core 0 Core 1... Core k Way 0 Way 1 Cell Cell Cell Cell... Cell Cell Way m Cell Cell Index 0... Set/n-1 Set/n... 2*Set/n-1... Cell Cell Cell Cell... Block n-1 Cell Cell Cell Cell (n-1)*set/n... Set-1 3.5: [2],. 2 4 8
4.1 2.1 (1) 2.1 (1) 9
10
3.2 11
12
4 4.1 4.6 4.6 13
ヒット率 キャッシュの容量 4.6: 14
4.2 4 1 1 4 15
16
4.3 4.7 main() If(Current Cycle > Interval){ assign Middle.MissRate; if(decided = False){ decide(); allocate; } } decide() foreach LowerMissRateCore{ if(middle.missrate Upper.MissRate) Upper = Middle; else if(middle.missrate > Upper.MissRate) Lower = Middle; Middle.Capacity = (Upper.Capacity + Lower.Capacity) / 2; set allocate_value; judge(); } judge() if(upper.capacity - Lower.Capacity = 1Cell){ Decided = True; if(middle.missrate > Upper.MissRate){ Middle = Upper; set allocate_value; } } 4.7: main decide 17
judge 3 0 4.7 main 4.7 decide 18
4.7 judge 19
LRU 20
5 5.1 [4] Splash2 [5] 2 5.1 5.1: 4 256KB 8 5.2 5.8 4.1 % 7.5 % 21
5.8: 22
5.3 5.8 5.9 Core0 Core1 Core2 Core3 Number of CacheAccess CacheMiss CacheHit 5.9: 23
5.9 0 30 % 1 3 % 2 33 % 3 3 % 1 3 0 30000 230000 1 10 300 2 300000 900000 3 10 300 29 % 24
CacheMissRate{%] 5.10 Execute Decided Time 5.10: 5.10 5.10 25
26
6 4.1 % 7.5 % 27
28
1 [1] G. E. Sue, L. Rudolph, and S. Devadas, Dynamic Partitioning of Shared Cache Memory, Journal of Supercomputing, vol.28, No.1, pp.7-26, January 2004. [2] March 2017 [3] March 2017 [4] <http://accc.riken.jp/supercom/himenobmt/> (2017 2 20 ) 29
[5] The Modified SPLASH-2 <http://www.capsl.udel.edu/splash/>(2017 3 2 ) 30