PC/104 SH-4 CPU BOARD ALPHA PROJECT co.,ltd http://www.apnet.co.jp
D-Sub (16mm) PC/104 40pin PC/104 64pin! HDL
SH7750 PC/104 Specification PC/104 Consortium URL http://www.renesas.com/jpn/ http://www.smsc.jp/ http://www.intel.co.jp/ http://www.altera.co.jp/ PC/104 Consortium http://www.pc104.org CompactFlash Association http://www.compactflash.org/ ecos Home Page http://sources.redhat.com/ecos/
1. 1.1 SH7750R 240MHz Linux 16Mbyte 10/100BASE-TX PC/104 HUDI/JTAG 1
2 2. 2.1 (J3,J4) (CN2) (J5) (CN1) (J1,J2) (J6) (LD1LD3) (J7) (J8) Fig 2.1-1
2.2 Fig 2.2-1 CPU SH7750R StrataFlash 235.9296MHz 16bit 128Mbit/256Mbit CASH 16Kbyte/32Kbyte MMU BSC Address Bus Data Bus 32bit Control Bus SDRAM 128Mbit/256Mbit CPLD EPM7128 4bit MODE SET MD0-MD6 SW Interrupt Controler CN1 DMAC 2CH TIMER 5CH 16bit Buffer Control CF-CARD SLOT (Type1) J1/J2 WDT Torelant PC/104 Connector RTC Buffer 16bit 16bit 10/100 EtherNet Controler LAN91C111 CN2 RJ-45 with Magnetics I/O 1bit I/O 4bit J5 I/O 16bit I/O 8bit VCC I/O Connector I/O 3bit Monitor LED3 HUDI I/O 4bit RTC R5C316A Back-up Cap J3 SN65C3232 COM1 Connector SCI 2CH J4 SN65C3232 COM2 Connector J6 HUDI/JTAG 19.6608MHz VCC(3.3V) SW REG 5V J7 POWER Connector 5V +12V 12V J8 POWER Connector 3
2.3 Fig 2.3-1 J1 J2 J3 J4 J5 J6 J7 J8 CN1 CN2 4
3. 3.1 CPU 3.1.1 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 1 SS1-2 Table3.1-1 3.1.2 RESET-SW SS1 1 2 Fig 3.1-2 SS1 SS1-2 CLK CPU (CKIO) 5
3.2 3.2.1 (P0) (P2) BSC H 00000000 H 00FFFFFF H A0000000 H A0FFFFFF FLASH MEMORY 28F128J3A 16Mbyte 16bit CS0 H 01000000 H A1000000 H 03FFFFFF H A3FFFFFF H 04000000 H 07FFFFFF H A4000000 H A7FFFFFF 8bit CS1 H 08000000 H 0800000F H A8000000 H A800000F EtherNet Controler LAN91C111 16bit CS2 H 08000010 H A8000010 H 0BFFFFFF H ABFFFFFF H 0C000000 H 0DFFFFFF H AC000000 H ADFFFFFF SDRAM 32Mbyte M12L128168AL1AM-7TG2L2 32bit SDRAM CS3 H 0E000000 H AE000000 2M 16bit H 0FFFFFFF H AFFFFFFF 4Bank H 10000000 H 10FFFFFF H B0000000 H B0FFFFFF PC/104 SH 8bit/16bit CS4 H 11000000 H B1000000 H 13FFFFFF H B3FFFFFF H 14000000 H 140007FF H B4000000 H B40007FF PCMCIA CompactFlash Type1 8bit/16bit PCMCIA CS5 H 14000800 H B4000800 H 17FFFFFF H B7FFFFFF H 18000000 H 18FFFFFF H B8000000 H B8FFFFFF PC/104 8bit/16bit PCMCIA CS6 MMU(TLB) H 19000000 H B9000000 H 1BFFFFFF H BBFFFFFF H 1C000000 H BC000000 H 1FFFFFFF H BFFFFFFF P0 = P0 P2 = P2 R/W Fig 3.2-1 6
3.2.1 SH7750 CS CKIO 58.9824MHz 29.4912MHz 0 1 2 3 4 5 6 WAIT WAIT WAIT CAS RAS CAS RAS RAS-CAS WAIT WAIT 1 PCMCIA OE/WE OE/WE WAIT PCMCIA OE/WE OE/WE 1 1 CF CIS Table 3.2-1 7
3.3 3.3.1 HUDI(JTAG) 3.4 SDRAM 8
3.5 CPLD QuartusVer3.0 WebEdition.quartus TOP.bdf Velilog MS104_SH4_XXX.V XXX ALTERA http://www.altera.co.jp/ 9
3.6 3.6.1 Table 3.6-1 3.6.2 SH7750R CPLD IRL3-0 CF PC/104 IRQ315 Fig 3.6-2 10
3.6.3 (H A4000000) = x0h Read / Write D7 D6 D5 D4 D3 D2 D1 D0 (H A4100000) = x0h Read /Write D7 D6 D5 D4 D3 D2 D1 D0 (H A4200000) = x0h Read /Write D7 D6 D5 D4 D3 D2 D1 D0 (H A4300000) = x0h Read /Write D7 D6 D5 D4 D3 D2 D1 D0 3.6.4 (H A4400000) Read D7 D6 D5 D4 D3 D2 D1 D0 (H A4500000) Read D7 D6 D5 D4 D3 D2 D1 D0 (H A4600000) Read D7 D6 D5 D4 D3 D2 D1 D0 (H A4700000) Read D7 D6 D5 D4 D3 D2 D1 D0 11
3.7 I/O Table 3.7-1 I/O 3.7.1 I/O VCC LED LED I/O LD1 LD2 LD3 Fig 3.7-2 LED 3.7.2 I/O No. No. 1 2 3 4 5 6 7 8 9 10 Fig 3.7-3 J5 Min Max VIH High 2.0V 3.6V VIL Low -0.3V 0.66V VOH High 2.4V - VOL Low - 0.55V Fig 3.7-4 I/O DC 12
3.8 Fig 3.8-1 SH7750R TxD RxD SN65C3232DBR Ti1 To1 Ro1 Ri1 COM1(J3) Header10pin COM1(J3) No. I/O No. I/O 1 2 3 4 5 6 7 8 9 10 SH7750R TxD2 RxD2 RTS2 CTS2 SN65C3232DBR Ti1 To1 Ro1 Ri1 Ti2 To2 Ro2 Ri2 COM2(J4) Header10pin COM2(J4) No. I/O No. I/O 1 2 3 4 5 6 7 8 9 10 Fig 3.8-2 D-Sub 10pin D-sub Male 9pin 1 1 2 6 3 2 4 7 5 3 6 8 7 4 8 9 9 5 10-13
3.9 EtherNet 3.9.1 LAN EtherNet SMSC LAN91C111 Fig 3.9-1 LED LAN CN2 1 8 LED No. 1 2 3 4 5 6 7 8 LED LED 3.9.2 LAN PC Fig 3.9-2 LAN 3.9.3 MAC ID 00-0C-7B 14
3.10 CF Table 3.10-1 CN1 PinNo. CF I/O PinNo. CF I/O 1 GND 26 CD1 2 D3 27 D11 3 D4 28 D12 4 D5 29 D13 5 D6 30 D14 6 D7 31 D15 7 CE1 32 CE2 8 A10 33 VS1 9 OE 34 IORD 10 A9 35 IOWR 11 A8 36 WE 12 A7 37 RDY/IREQ 13 VCC 38 VCC 14 A6 39 CSEL 15 A5 40 VS2 16 A4 41 RESET 17 A3 42 WAIT 18 A2 43 INPACK 19 A1 44 REG 20 A0 45 BVD2 21 D0 46 BVD1 22 D1 47 D8 23 D2 48 D9 24 IOIS16 49 D10 25 CD2 50 GND I=O= IO = P= I/O 15
3.10.1 CF CPLD CF (H A4800000) = x0h Write D7 D6 D5 D4 D3 D2 D1 D0 WAIT ( 1 )( 0 ) IOIS16 ( 1 )( 0 ) CF 3.10.2 CF IO (P8) CD1 CD2 CARD_CD(P8) Fig 3.10-2 CF 3.10.3 CF 3.3V IO (P10) Fig 3.10-3 CF CF IO (P10) CF 16
3.10.4 CF Fig 3.10-4 CF CPU CF IO (P11) 3.10.5 CF CF CPUCF CF CARD_CD(P8) CARD_PON(P9) CF_IRQ(RDY) CARD_ENABLE(P11) CARD_RESET(P10) Fig 3.10-5 CF 17
3.11 RTC 3.11.1 RTC VCC SH7750R CPLD P15 P14 P13 I/O RS5C316A CE VCC SCLK VSS SIO OSCIN INT OSCOUT 32.768KHz 0.33F BATT(J8) Fig 3.11-1 RTC P13 3.11.2 3.11.3 BATT RS5C316A 18
3.12 HUDI/JTAG 3.12.1 HUDI/JTAG SW2 HUDI / CPLD SW2 BitBlaster or ByteBlaster (J6) 1 TCK 1 TCK 2 GND 8 GND 3 TDO 3 TDO 4 VCC 11 VCC 5 TMS 5 TMS 9 TDI 6 TDI 10 GND 12 GND 19
3.13 PC/104 No. J1 LowA J1 LowB PC/104 PC/104 1 IOCHCHK* 0V 2 SD7 RESETDRV 3 SD6 +5V 4 SD5 IRQ9 5 SD4-5V 6 SD3 DRQ2 7 SD2-12V 8 SD1 ENDXFR* 9 SD0 +12V 10 IOCHRDY (KEY) 11 AEN SMEMW* 12 SA19 SMEMR* 13 SA18 IOW* 14 SA17 IOR* 15 SA16 DACK3* 16 SA15 DRQ3 17 SA14 DACK1* 18 SA13 DRQ1 19 SA12 REFRESH* 20 SA11 SYSCLK 21 SA10 IRQ7 22 SA9 IRQ6 23 SA8 IRQ5 24 SA7 IRQ4 25 SA6 IRQ3 26 SA5 DACK2* 27 SA4 TC 28 SA3 BALE 29 SA2 +5V 30 SA1 OSC 31 SA0 0V 32 0V 0V No. J2LowC J2 LowD PC/104 PC/104 0 0V 0V 1 SBHE* MEMCS16* CPLD() 2 LA23 IOCS16* 3 LA22 IRQ10 4 LA21 IRQ11 5 LA20 IRQ12 6 LA19 IRQ15 7 LA18 IRQ14 8 LA17 DACK0* CPLD(DACK0) 9 MEMR* DRQ0 CPLD(DREQ0) 10 MEMW* DACK5* 11 SD8 DRQ5 12 SD9 DACK6* 13 SD10 DRQ6 14 SD11 DACK7* 15 SD12 DRQ7 16 SD13 +5V 17 SD14 MASTER 18 SD15 0V 19 (KEY)2 0V I=O=I/O=TO=TI/O=OC= CPLD(XXXXX) = CPLD SH-4 Pull-up = Pull-up = Table 3.13-1 PC/104 20
PC/104 Table 3.13-2 PC/104 SD0SD15 I/O SA0SA19 O LA20LA23 O AEN O BALE O #IOR O #IOW O #SBHE O #MEMR O #MRMW O #SMEMR O #SMEMW O IRQn I IOCHRDY I #IOCS16 I #MEMCS16 I RESETDRV O SYSCLK O DRQn I #DACKn O TC O 21
OSC O #REFRESH O #ENDXFR I MASTER I +5V P -5V +12V -12V 0V P P KEY - 22
3.13.1 PC/104 SH7750R PC/104 BSC P0 P2 H 10000000 H B0000000 H 0000 H FFFF I/O 64Kbyte H 10FFFFFF H B0FFFFFF H 000000 16Mbyte H 18000000 H 18FFFFFF H B8000000 H B8FFFFFF MMU H FFFFFF Fig3.13-3 PC/104 CS6 (PAMCIA ) PC/104 PC/104 SA SH7750R CS4 () 23
3.13.2 SYSCLK RESET-SW SS1-1 PC/104 SYSCLK SS1 1 2 Fig 3.13-4 SS1 3.13.3 Fig 3.13-5 VCC 1 JP1 3 4.7K INT (CPLD) PC104 IRQn 1 3 JP1 3.13.4 PC/104 24
3.13.5 PC/104 IO Fig 3.13-6 PC/104 IO TCLK CKIO 1 TBALE TBALE BALE LA[23..17] SA[19..0] AEN #SBHE tiordf tiorw tiord #IOR trds trdh D[15..0] (READ) tiowdf tioww tiowd #IOW twdh D[15..0] (WRITE) IOCHRDY #IOCS16 1 CKIO R SYSCLK tclk SH7750R 58.9824MHz tbaled BALE 25ns tbale BALE 68ns tiordf IOR 118ns PCR [A6TED2:A6TED0]=100 (6clk) tiorw IOR 220ns WCR2 [A6W2:A6W0] = 110 (12clk) 25 PCR[A6PCW1:A6PCW0]=00 (0clk) tiord IOR 51ns PCR [A6TEH2:A6TEH0]=011 (3clk) trds 3.5ns trdh 1.5ns tiowdf IOW 110ns tioww IOW 220ns tiowd IOW 59ns twdh 59ns SH7750
3.13.6 PC/104 Fig 3.13-7 PC/104 TCLK CKIO 1 TBALE TBALE BALE LA[23..17] SA[19..0] AEN #SBHE tmrdf tmrw tmrd #SMEMR #MEMR trds trdh D[15..0] (READ) tmwdf tmww tmwd #SMEMW #MEMW twdh D[15..0] (WRITE) IOCHRDY 1 CKIO R SYSCLK tclk SH7750R 58.9824MHz tbaled BALE 25ns tbale BALE 68ns tmrdf MEMR 118ns PCR [A6TED2:A6TED0]=100 (6clk) tmrw MEMR 220ns WCR2 [A6W2:A6W0] = 110 (12clk) PCR[A6PCW1:A6PCW0]=00 (0clk) tmrd MEMR 51ns PCR [A6TEH2:A6TEH0]=011 (3clk) trds 3.5ns trdh 1.5ns tmwdf MEMW 110ns tmww MEMW 220ns tmwd MEMW 59ns twdh 59ns SH7750 26
3.13.7 PC/104 SH Fig 3.13-8 PC/104 SH tclk T1 TW T2 CKIO 1 tbaled tbaled BALE tad tad LA[23..17] SA[19..0] AEN #SBHE trd trd #MEMR #SMEMR trds trdh D[15..0] (READ) twd twd #MEMW #SMEMW twdd twdd D[15..0] (WRITE) IOCHRDY 1 CKIO R SYSCLK Min Max tclk 58.9824MHz SH7750R CKIO tw IOCHRDY A4W[2..0] ex) IOCHRDY = High A4W[2..0]=000(0wait) 0Tclk tbaled BALE 1.5ns 6ns SH7750R BS tad 1.5ns 6ns trd 1.5ns 6ns SH7750R RD trds 3.5ns trdh 1.5ns twd 1.5ns 6ns SH7750R WEn twdd 1.5ns 6ns SH7750 27
3.13.8 tclk1 CKIO (SS1-1 = OFF) tclk2 CKIO (SS1-1 = ON) tsysclk SYSCLK (7.3728MHz) tclk1 CKIO 1 58.9824MHz SS1-1 OFF tclk2 CKIO 2 29.4912MHz SS1-2 OFF tsysclk SYSCLK 7.3728MHz Fig 3.13-9 3.13.9 RESET +5V treset RESET RESET-SW RESET-SW ON treset RESET Min Typ Max treset RESET 60ms 100ms Fig 3.13-10 RESET 28
3.13.10 PC/104 DC Min Max SA[19..0] VIH High 1.7V 5.75V LA[23..20] VIL Low -0.5V 0.8V D[15..0] VOH High 2.4V VOL Low 0.45V SA[19..0] VIH High 2.0V 7.0V LA[23..20] VIL Low -0.5 0.8V D[15..0] VOH High 2.4V VOL Low 0.55V Table 3.13-11 DC 29
3.14 3.14.1 DC5V 1A2A 2 J7 1 1 2-5V -12V J8 +12V GND BATT Fig 3.14-1 3.14.2 +12V +12.6V +11.4V 1.0A +5V +5.25V +4.75V 2.0A -5V -4.75V -5.25V 0.2A -12V -11.4V -12.6V 0.3A Table 3.14-2 PC104 30
31 4. 4.1 Fig 4.1-1
4.2 HJ-LINK HJ-LINKFlashWriterEX FlashWriterEXHJ-LINK Linux-Kit-AXX(1) 1 Linux-Kit-AXX FlashWriterEX SH7750R XX PC HJ-LINK Fig 4.2-1 HJ-LINK AC100V AC D-SUB 25pin HJ-LINK J6 DC5V SS1 SW2 SH2/3 SH4 SH4 HUDI / CPLD HUDI FlashWriterEX CPU Auto(AutoTransfer) Tartget Write Start Fig 4.2-2 FlashWriterEX 32
4.3 CPLD HJ-LINKMax+Plus Quartus PC HJ-LINK CPLD JTAG HUDI Fig 4.3-1 HJ-LINK D-SUB 25pin HJ-LINK J6 DC5V SS1 SW2 SH2/3 SH4 HUDI / CPLD CPLD Max+PlusQuartusProgrammer HardwareType ByteBlaster Max+PlusQuartusALTERA Max+PLUSVer10.22 QuartusVer2.2SP2 33
4.4 PC/104 4.4.1 PC/104 Fig 4.4-1 PC/104 4.4.2 PC/104 PC/104 2.54mm 11mm(13.6mm) 15.24mm(16mm) Fig 4.4-2 PC/104 34
E-mail FD CD-ROM 35
36
3.2.1 2 3.13 PC/104 IRQ9DRQ2 3.13.8 SYSCLK 7.2738MHz 7.3728MHz 3.2.1 3 3.2.1 2 3.1.1 (SS1) 3.1.2 (SS1) 3.13.2 SYSCLK (SS1) RedBoot RS232C SN65C3232DBR 2.3 LAN PTL-TJ-N-D(JIROTECH) SDRAM M12L128168AL1AM-7TG2L 37
SH7750 PC/104 SpecificationPC/104 Consortium SuperH Max+plus Quartus Altera Corporation Linux, Linus Torvalds. ALPHA PROJECT Co.,LTD. 38