NCV5171/731.5 A 280 khz/560 khz 2.730 V SEPIC LT1372/1373 1.5 A 2.730 V 50 A LT1372/1373 NCV 40 C125 C Test SS 1 SOIC8 D SUFFIX CASE 751 MARKING DIAGRAM AND PIN CONNECTIONS FB 517xE ALYW A C 517xE = Specific Device Code x = 1 or 3 A = Assembly Location L = Wafer Lot Y = Year W = Work Week = PbFree Package 8 V SW P Device Package Shipping NCV5171EDR2G NCV5173EDR2G ORDERING INFORMATION SOIC8 (PbFree) SOIC8 (PbFree) 2500 Units / Box 2500 Units / Box For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 February, 2016 Rev. 6 1 Publication Order Number: NCV5171JP/D
C1 0.01 F SS R2 3.72 k 1 2 3 FB Test NCV5171/73 V SW P A 4 5 SS C 8 7 6 L1 22 H D1 MBRS120T3 V OUT 5 V C3 22 F 3.3 V R1 5 k R3 1.28 k C2 22 F Figure 1. Applications Diagram MAXIMUM RATINGS Rating Value Unit Junction Temperature Range, T J 40 to 150 C Storage Temperature Range, T STORAGE 65 to 150 C Package Thermal Resistance JunctiontoCase, R JC JunctiontoAmbient, R JA 45 165 C/W Lead Temperature Soldering: Reflow (Note 1) 260 Peak (Note 1) C ESD, Human Body Model 1.2 kv Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. () 1. 60180 seconds minimum above 237 C. MAXIMUM RATINGS Pin Name Pin Symbol V MAX V MIN I SOURCE I SINK IC Power Input C 35 V 0.3 V N/A 200 ma Shutdown/Sync SS 30 V 0.3 V 1.0 ma 1.0 ma Loop Compensation 6.0 V 0.3 V 10 ma 10 ma Voltage Feedback Input FB 10 V 0.3 V 1.0 ma 1.0 ma Test Pin Test 6.0 V 0.3 V 1.0 ma 1.0 ma Power Ground P 0.3 V 0.3 V 4 A 10 ma Analog Ground A 0 V 0 V N/A 10 ma Switch Input V SW 40 V 0.3 V 10 ma 3.0 A 2
ELECTRICAL CHARACTERISTICS (2.7 V< C < 30 V; 40 C < T J < 125 C unless otherwise stated) Characteristic Test Conditions Min Typ Max Unit Positive and Negative Error Amplifiers FB Reference Voltage tied to FB; measure at FB 1.246 1.276 1.300 V FB Input Current FB = V REF 1.0 0.1 1.0 A FB Reference Voltage Line Regulation = FB 0.01 0.03 %/V Positive Error Amp Transconductance I VC = ± 25 A 300 550 800 Mho Positive Error Amp Gain (Note 2) 200 V/V Source Current FB = 1.0 V, = 1.25 V 25 50 90 A Sink Current FB = 1.5 V, = 1.25 V 200 625 1500 A High Clamp Voltage FB = 1.0 V; sources 25 A 1.5 1.7 1.9 V Low Clamp Voltage FB = 1.5 V; sinks 25 A 0.25 0.50 0.65 V Threshold Reduce from 1.5 V until switching stops 0.6 1.05 1.30 V Oscillator Base Operating Frequency NCV5171, FB = 1 V 230 280 310 khz Base Operating Frequency NCV5173, FB = 1 V 460 560 620 khz Reduced Operating Frequency NCV5171, FB = 0 V 30 52 120 khz Reduced Operating Frequency NCV5173, FB = 0 V 60 104 160 khz Maximum Duty Cycle NCV5171 90 94 % Maximum Duty Cycle NCV5173 82 90 % FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V Sync/ Shutdown Sync Range NCV5171 320 500 khz Sync Range NCV5173 640 0 khz Sync Pulse Transition Threshold Rise time = 20 ns 2.5 V SS Bias Current SS = 0 V SS = 3.0 V 15 3.0 3.0 8.0 A Shutdown Threshold 0.40 0.85 1.20 V Shutdown Delay 2.7 V C 12 V 12 V < C 30 V 12 12 80 36 350 200 s Power Switch Switch Saturation Voltage I SWITCH = 1.5 A, (Note 2) 0.8 1.4 V I SWITCH = 1.0 A, 0 C T J 85 C I SWITCH = 1.0 A, 40 C T J 0 C I SWITCH = 10 ma 0.55 0.75 0.09 0.45 Switch Current Limit 50% duty cycle, (Note 2) 1.6 1.9 2.4 A 80% duty cycle, (Note 2) 1.5 1.7 2.2 Minimum Pulse Width FB = 0 V, I SW = 4.0 A, (Note 2) 200 250 300 ns I CC / IV SW 2.7 V C 12 V, 10 ma I SW 1.0 A 10 30 ma/a 12 V < C 30 V, 10 ma I SW 1.0 A 2.7 V C 12 V, 10 ma I SW 1.5 A, (Note 2) 12 V < C 30 V, 10 ma I SW 1.5 A, (Note 2) 17 30 Switch Leakage V SW = 40 V, C = 0V 2.0 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. () 2. Guaranteed by design, not % tested in production. 3
ELECTRICAL CHARACTERISTICS (2.7 V< C < 30 V; 40 C < T J < 125 C unless otherwise stated) (continued) Characteristic Test Conditions Min Typ General Operating Current I SW = 0 5.5 8.0 ma Shutdown Mode Current < 0.8 V, SS = 0 V, 2.7 V C 12 V < 0.8 V, SS = 0 V, 12 V C 30 V 12 60 A Minimum Operation Input Voltage V SW switching, maximum I SW = 10 ma 2.45 2.70 V Thermal Shutdown (Note 2) 150 180 210 C Thermal Hysteresis (Note 2) 25 C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. () 2. Guaranteed by design, not % tested in production. Max Unit PACKAGE PIN DESCRIPTION Package Pin # Pin Symbol Function 1 Loop compensation pin. The pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1. 2 FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency. 3 Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running. 4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation. 5 C Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to A. 6 A Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate. 7 P Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential. 8 V SW High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical. 4
C SS Shutdown Delay Timer 2.0 V Regulator Sync Thermal Shutdown Oscillator Frequency Shift 5:1 S PWM Latch R Q Driver Switch Slope Compensation 5 V SW 63 m Ramp Summer P PWM Comparator 0.4 V Detector FB 1.276 V Positive Error Amp A Figure 2. Block Diagram 5
TYPICAL PERFORMANCE CHARACTERISTICS Current (ma) 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 C = 30 V C = 12 V C = 2.7 V 0 50 (ma/a) 70 60 50 40 30 20 10 0 C = 30 V I SW = 1.5 A C = 12 V C = 2.7 V 0 50 Figure 3. I CC (No Switching) vs. Temperature Figure 4. I CC / IV SW vs. Temperature 1200 1.9 E(SAT) (mv) 0 800 600 400 200 40 C 85 C 25 C V IN (V) 1.8 1.7 1.6 0 500 0 I SW (ma) Figure 5. E(SAT) vs. I SW 1.5 Figure 6. Minimum Input Voltage vs. Temperature f OSC (khz) 285 280 275 270 265 260 255 Figure 7. Switching Frequency vs. Temperature (NCV5171) f OSC (khz) 570 565 560 555 550 545 540 535 530 525 520 Figure 8. Switching Frequency vs. Temperature (NCV5173) 75 50 25 f OSC (% of Typical) C = (12 V) 25 C 40 C 85 C 0 350 380 400 420 450 V FB (mv) Figure 9. Switching Frequency vs. V FB 6
TYPICAL PERFORMANCE CHARACTERISTICS 1.280 1.278 C = 12 V 0.20 0.18 Voltage (V) 1.276 1.274 1.272 C = 2.7 V C = 30 V I FB (A) 0.16 0.14 0.12 1.270 0.10 1.268 Figure 10. Reference Voltage vs. Temperature 0.08 Figure 11. I FB vs. Temperature Current (A) 2.60 2.50 2.40 2.30 2.20 C = 2.7 V C = 12 V C = 30 V Duty Cycle (%) 99 98 97 96 95 94 93 C = 30 V C = 12 V C = 2.7 V Figure 12. Current Limit vs. Temperature Figure 13. Maximum Duty Cycle vs. Temperature Voltage (V) 1.7 1.5 1.3 1.1 0.9 Threshold High Clamp Voltage Voltage (V) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.7 Figure 14. Threshold and High Clamp Voltage vs. Temperature 0.4 Figure 15. Shutdown Threshold vs. Temperature 7
TYPICAL PERFORMANCE CHARACTERISTICS Delay (s) 160 140 120 80 60 C = 2.7 V C = 12 V C = 30 V I SS (A) 40 30 20 10 0 25 C 85 C 40 C 40 Figure 16. Shutdown Delay vs. Temperature 10 1 3 5 7 9 V SS (V) Figure 17. I SS vs. V SS 40 40 C 600 I CC (A) 30 20 25 C 85 C g m (mho) 550 500 10 0 10 V IN (V) 450 Figure 18. I CC vs. V IN During Shutdown Figure 19. Error Amplifier Transconductance vs. Temperature 2.6 I OUT (A) 60 20 20 Current (A) 2.5 2.4 2.3 2.2 2.1 60 255 175 125 75 25 V REF V FB (mv) 0 25 2.0 Figure 20. Error Amplifier I OUT vs. V FB Figure 21. Switch Leakage vs. Temperature 8
Oscillator PWM Compar - ator SUMMER Slope Compensation S Q R X5 Power Switch In Out Driver 63 m V SW C L D1 Figure 22. Current Mode Control Scheme C O RLOAD NCV5171/73 PWM 1 2 50% NCV5171/73 Sync Current Ramp V SW Figure 23. Timing Diagram of Sync and Shutdown 18% Figure 22 280 khz (NCV5171)560 khz (NCV5173) PWM SSTTL 1.8 Figure 23 SS FB 20% PWM FB 1M 1.276 V NCV5171/73 positive erroramp 120 pf Voltage Clamp C1 0.01 F R1 5 k Figure 24. Error Amplifier Equivalent Circuit FB 1.276 V Figure 24 1 M 0.51.7 V / 9
(63 m)p PIC 1.5 A (V SW )40 V 1 V () 2 NCV5171/73 V SW FB 1 FB0.4 V () Fb 50 mv DC Figure 26 21 Figure 27 I L V OUT C NCV5171/73 R1 C1 C2 Figure 26. A Typical Compensation Network Figure 25. Startup Waveforms of Circuit Shown in the Application Diagram. Load = 400 ma. C SS NCV5171/73Figure 252 Application Diagram C V SW C 1.5 V Figure 27DC DC DC GainDC GM RO G M = R O = 1M f P1 C1 fp1 1 2C1RO 10
C1R1 fz1 1 2C1R1 45 fp 1 2CORLOAD C O = 120 pf; R LOAD = f P2 ESR 1/2 C2R1 fp2 1 2C2R1 1 1() 1020 db f Z1 f P2 Gain (db) DC Gain f P1 f Z1 Frequency (LOG) Figure 27. Bode Plot of the Compensation Network Shown in Figure 26 V SW V SW 0.5 V 0.8 V f P2 VSW(MAX) VOUT(MAX)VF V F = V SW VSW(MAX) VCC(MAX)(VOUTVF) N N1/2 V SW P V SW V SW EMI % (V OUT /C ) IRIPPLE C(VOUT VCC) (f)(l)(vout) f = 280 khz (NCV5171)560 khz (NCV5173) EMI Figure 29 Figure 28 Figure 28 (ESR) C 10 FESR 0.3 1.5 A 11
Figure 28. Boost Input Voltage and Current Ripple Waveforms C IIN CIN R ESR C ripple Figure 29. Boost Circuit Effective Input Filter 2 20 FESR C 1.0 F I L I IN Figure 30. Typical Output Voltage Ripple I L V OUT ripple I L Figure 30 2ESR I L V = I IN ESR I L I OUT I l I OUT I L I L I IN VOUT(RIPPLE) (I IN IOUT)(1 D) (COUT)(f) I OUTD (COUT)(f) I IN ESR C V OUT I OUT VOUT(RIPPLE) I OUT(VOUT VCC) (COUT)(f) 1 (COUT)(f) (I OUT)(VOUT)(ESR) VCC RMS IRIPPLE (IIN IOUT)2(1 D)(IOUT)2(D) IOUT VOUT VCC VCC 1.5 A VC ISWREAV R E = 0.063 A V = 5 V/V R E A V () 1.5 A 12
Figure 31 R3 V IN V IN R2 R3 D1 C Figure 31. Current Limiting using a Diode Clamp Figure 32 C1 R1 C2 V IN P A C R1 C1 Q1 R2 C2 C3 Output R SENSE Ground Figure 32. Current Limiting using a Current Sense Resistor ISWITCH(PEAK) V BE(Q1) RSENSE V BE(Q1) = Q1 0.65 V R SENSE R2C3 13
(SHM) 50% SHM SHMEM SHM NCV5171/73 180 ma/ SHM Figure 33 23 C1 C3 V SW R1 C2 R2 R3 Figure 33. Technique for Increasing Slope Compensation V SW R2 R3V SW V SW V SW V SW V SW C3 C3 R3 (1D) I T V SW R3 R3C3fSW R2R3 1 e fsw (1 D)REAV I/T = (A/s) V SW = (V) f SW = 280 khz (NCV5171)560 khz (NCV5173) D = R E = 0.063 A V = 5 V/V R2R3 ma/s R2 R2R3 V SW R3C3 1 D fsw NCV5171/73 14
Figure 34 SS V IN SS D1 SS D2 C3 C C1 Figure 34. Soft Start R1C1C2 D2 C3 1.05 V ( ) VC VF(D2)VC3 C3 C3 SSD1C3 D1V IN NCV5171/73 180 C ±30 C NCV5171/733 P BIAS P DRIVER P SAT R1 C2 I Q 5.5 ma IQV IN PBIAS VINIQ NPN V IN I CC /I SW PDRIVER VINISW I CC ISW D I SW = D = I SW D ISW(AVG) IL(AVG) D 1 Efficiency D V OUT VIN VOUT ISW(AVG) V OUTILOAD VIN 1 Efficiency 1 D D VOUT VOUT N S V NP IN V (CE)SAT V (CE)SAT NPN V (CE)SAT PSAT V(CE)SATISW D PD PBIASPDRIVERPSAT 15
JA JA TJ TA(PDJA) T J = FET( C) T A = ( C) P D = (W) JA = ( C/W) NCV5171/73 JA = 165 C/W T J NCV5171/73 T J 150 C NCV5171/73 T J 150 C T A AC AC 1 2 AC 16
22 H MBRS120T3 3.3 V IN 10 F 5.0 V O C (5) 3.6 k 22 F P (7) A (6) V SW (8) 0.1 F NCV5171/73 (1 ) FB (2) 1.3 k 5.0 k 200 pf Figure 35. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 ma Output Boost Converter MBRS140T3 C 22 F 1.0 F C (5) P (7) V SW (8) A (6) NCV5171/73 P6KE15A 1N4148 T1 1:2 MBRS140T3 47 F 47 F 12 V 12 V (1 ) FB (2) 4.7 nf 47 nf 2.0 k 1.28 k 10.72 k Figure 36. Additional Application Diagram, 2.7 to 13 V Input, 12 V/ 200 ma Output Flyback Converter (1 ) C (5) 2.2 F V IN 200 pf 5.0 k.01 F NCV5171/73 V SW (8) A (6) FB (2) 15 H 22 F Low ESR 1.1 k 5.0 V OUT P (7) 300 Figure 37. Additional Application Diagram, 9.0 V to 28 V Input, 5.0 V/700 ma Output Inverted Buck Converter 17
C 22 H 22 F C (5) 200 pf P (7) V SW (8) A (6) NCV5171/73 (1 ) FB (2).01 F 22 F 22 H 22 F Low ESR 37.24 k 5.0 V 5.0 k 12.76 k Figure 38. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter R1 1.245 k/0.1 W, 1% R2 99.755 k/0.1 W, 1% C1 C2 C3 C11.01 C10.1 R3 2.0 k 1 2 FB 3 Test 4 SS NCV5171/73 V SW 8 P 7 6 A V 5 CC C8 10 C9.1.1.1.1 50 V 50 V 50 V D1 D1 D1 D1 D1 D1 D1 1N4148 C7.1 50 V 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 C4 C5 C6.1.1.1 50 V 50 V 50 V V O 4.0 V Figure 39. Additional Application Diagram, 4.0 V Input, V/ 10 ma Output Boost Converter with Output Voltage Multiplier 200 pf SS C6 C1 R1 5.0 k 0.01 F 1 2 FB 3 Test NCV5171/73 V 8 SW 7 P A 6 4 SS 5 C L1 15 H D2 22 F D3 D1 C3 22 F 12 V 5.0 V R2 1.28 k C4 0.1 F R3 10.72 k C5 22 F 12 V Figure 40. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter 18
PACKAGE DIMENSIONS X B Y A S SOIC8 NB CASE 75107 ISSUE AK K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 75107. Z H G D C SEATING PLANE N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 19
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. () ON SemiconductorONSemiconductor Components Industries, LLC (SCILLC) SCILLC ()SCILLC www.onsemi.com/site/pdf/patent-marking.pdfscillcscillc SCILLC SCILLCSCILLC SCILLC SCILLCSCILLC SCILLC SCILLC PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 3036752175 or 8003443860 Toll Free USA/Canada Fax: 3036752176 or 8003443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8002829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81358171050 20 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCV5171JP/D