DS90LV V or 5V LVDS Driver/Receiver (jp)

Transcription

1 DS90LV019 DS90LV V or 5V LVDS Driver/Receiver Literature Number: JAJS563

2 DS90LV019 LVDS 1 / DS90LV019 Low Voltage Differential Signaling (LVDS) 1 CMOS / DS90LV019 EIA-644 IEEE (SCI LVDS) Mbps (50MHz) 3.3V 5.0V (350mV) (3.5mA) / (EMI) ( ) TTL LVDS DE L TRI-STATE 100mV 1V LVDS CMOS RE H TRI-STATE CMOS 3.3V or 5V LVDS Driver/Receiver 019 LV DS90 Bruce Motavaf ds LVDS 3.3V 5.0V ON/OFF 100Mbps (50MHz) : Converted to nat2000 DTD added max power dissipation for TSSOP pkg, and derate value added tssop pkg to features, inserted graphic, added order numbers migrate to prod.doc base and fixed base pid composed on 6/15/98 Started a new datasheet in sgml for RRD to key in, fixed typos reedited for composition changes on graphics, clean up typos 1V : 100mV : 350mV(100 ) : 3.5mA( ) : DS90LV DS90LV019 LVDS1 / Order Number DS90LV019TM or DS90LV019TMTC See NS Package Number M14A or MTC14 TRI-STATE National Semiconductor Corporation 1 Printed in Japan NSJ 7/2001

3 DS90LV019 (Note 1) (V CC ) 6.0V (DE RE) 0.3V (V CC 0.3V) (D IN ) 0.3V (V CC 0.3V) (R OUT ) 0.3V (V CC 0.3V) (DOUT DOUT ) 0.3V (V CC 0.3V) (Rin Rin ) 0.3V (V CC 0.3V) (DOUT DOUT ) (ESD) (Note 4) HBM 1.5k 100pF 2000V EIAJ 0 200pF 200V (PD) ( 25 ) SOIC M 960mW SOIC M ( 25 ) 7.7mW/ TSSOP 790mW TSSOP ( 25 ) 6.3mW/ (TSTG) ( 4 ) 260 (V CC ) V V V DC (Note 2 3) V CC 3.3V 0.3V T A (Note 2 3) Symbol Parameter Conditions Pin Min Typ Max Units DIFFERENTIAL DRIVER CHARACTERISTICS V OD Output Differential Voltage R L 100 (Figure 1 ) DO, mv V OD V OD Magnitude Change DO 6 60 mv V OS Offset Voltage V V OS Offset Magnitude Change 5 60 mv I OZD TRI-STATE Leakage V OUT V CC or GND, DE 0V A I OXD Power-Off Leakage V OUT 3.6V or GND, V CC 0V A I OSD Output Short Circuit Current V OUT 0V, DE V CC ma DIFFERENTIAL RECEIVER CHARACTERISTICS V OH Voltage Output High VID 100 mv I OH 400 A R OUT V Inputs Open V V OL Voltage Output Low I OL 2.0 ma, VID 100 mv V I OS Output Short Circuit Current V OUT 0V ma V TH Input Threshold High RI, 100 mv V TH Input Threshold Low RI 100 mv I IN Input Current V IN 2.4V or 0V, V CC 3.6V or 0V A DEVICE CHARACTERISTICS V IH Minimum Input High Voltage D IN, 2.0 V CC V V IL Maximum Input Low Voltage DE, RE GND 0.8 V I IH Input High Current V IN V CC or 2.4V 1 10 A I IL Input Low Current V IN GND or 0.4V 1 10 A V CL Input Diode Clamp Voltage I CLAMP 18 ma V I CCD Power Supply Current DE RE V CC V CC ma I CCR DE RE 0V ma I CCZ DE 0V, RE VCC ma I CC DE VCC, RE 0V ma C D output Capacitance DO, 5 pf DO C R input Capacitance RI, RI 5 pf 2

4 DC (Note 2 3) V CC V T A Symbol Parameter Conditions Pin Min Typ Max Units DIFFERENTIAL DRIVER CHARACTERISTICS V OD Output Differential Voltage R L 100 (Figure 1 ) DO, mv V OD V OD Magnitude Change DO 6 60 mv V OS Offset Voltage V V OS Offset Magnitude Change 5 60 mv I OZD TRI-STATE Leakage V OUT V CC or GND, DE 0V A I OXD Power-Off Leakage V OUT 5.5V or GND, V CC 0V A I OSD Output Short Circuit Current V OUT 0V, DE V CC ma DIFFERENTIAL RECEIVER CHARACTERISTICS V OH Voltage High VID 100 mv I OH 400 A R OUT V Inputs Open V V OL Voltage Output Low I OL 2.0 ma, VID 100 mv V I OS Output Short Circuit Current V OUT 0V ma V TH Input Threshold High RI, 100 mv V TH Input Threshold Low RI 100 mv I IN Input Current V IN 2.4V or 0V, V CC 5.5V or 0V A DEVICE CHARACTERISTICS V IH Minimum Input High Voltage D IN, DE, 2.0 V CC V V IL Maximum Input Low Voltage RE GND 0.8 V I IH Input High Current V IN V CC or 2.4 V 1 10 A I IL Input Low Current V IN GND or 0.4V 1 10 A V CL Input Diode Clamp Voltage I CLAMP 18 ma V I CCD Power Supply Current DE RE V CC V CC ma I CCR DE RE 0V ma I CCZ DE 0V, RE VCC ma I CC DE VCC, RE 0V ma C D output Capacitance DO, 5 pf DO C R input Capacitance RI, RI 5 pf DS90LV019 Note 1: Note 2: V OD1 V OD1 Note 3: V CC 3.3V 5.0V T A 25 Note 4: ESD : HBM(1.5k 100pF) 2000V EIAJ(0 200pF) 200V Note 5: C L Note 6: f 1 MHz Z O 50 t r t f 6ns( : ) AC (Note 6) V CC 3.3V 0.3V T A Symbol Parameter Conditions Min Typ Max Units DRIVER TIMING REQUIREMENTS t PHLD Differential Propagation Delay High to Low R L 100, ns t PLHD Differential Propagation Delay Low to High C L 10 pf ns t SKD Differential Skew t PHLD t PLHD (Figure 2 and Figure 3 ) ns t TLH Transition Time Low to High ns t THL Transition Time High to Low ns 3

5 DS90LV019 AC (Note 6) ( ) V CC 3.3V 0.3V T A Symbol Parameter Conditions Min Typ Max Units DRIVER TIMING REQUIREMENTS t PHZ Disable Time High to Z R L 100, ns t PLZ Disable Time Low to Z C L 10 pf ns t PZH Enable Time Z to High (Figure 4 and Figure 5 ) ns t PZL Enable Time Z to Low ns RECEIVER TIMING REQUIREMENTS t PHLD Differential Propagation Delay High to Low C L 10 pf, ns t PLHD Differential Propagation Delay Low to High VID 200 mv ns t SKD Differential Skew t PHLD t PLHD (Figure 6 and Figure 7 ) ns t r Rise Time ns t f Fall Time ns t PHZ Disable Time High to Z R L 500, ns t PLZ Disable Time Low to Z C L 10 pf ns t PZH Enable Time Z to High (Figure 8 and Figure 9 ) ns t PZL Enable Time Z to Low ns AC (Note 6) V CC 5.0V 0.5V T A Symbol Parameter Conditions Min Typ Max Units DRIVER TIMING REQUIREMENTS t PHLD Differential Propagation Delay High to Low R L 100, ns t PLHD Differential Propagation Delay Low to High C L 10 pf ns t SKD Differential Skew t PHLD t PLHD (Figure 2 and Figure 3 ) ns t TLH Transition Time Low to High ns t THL Transition Time High to Low ns t PHZ Disable Time High to Z R L 100, ns t PLZ Disable Time Low to Z C L 10 pf ns t PZH Enable Time Z to High (Figure 4 and Figure 5 ) ns t PZL Enable Time Z to Low ns RECEIVER TIMING REQUIREMENTS t PHLD Differential Propagation Delay High to Low C L 10 pf, ns t PLHD Differential Propagation Delay Low to High VID 200 mv ns t SKD Differential Skew t PHLD t PLHD (Figure 6 and Figure 7 ) ns t r Rise Time ns t f Fall Time ns t PHZ Disable Time High to Z R L 500, ns t PLZ Disable Time Low to Z C L 10 pf ns t PZH Enable Time Z to High (Figure 8 and Figure 9 ) ns t PZL Enable Time Z to Low ns 4

6 Test Circuits and Timing Waveforms DS90LV019 FIGURE 1. Differential Driver DC Test Circuit FIGURE 2. Differential Driver Propagation Delay and Transition Test Circuit FIGURE 3. Differential Driver Propagation and Transition Time Waveforms FIGURE 4. Driver TRI-STATE Delay Test Circuit 5

7 DS90LV019 Test Circuits and Timing Waveforms ( ) FIGURE 5. Driver TRI-STATE Delay Waveforms FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms FIGURE 8. Receiver TRI-STATE Delay Test Circuit 6

8 Test Circuits and Timing Waveforms ( ) DS90LV019 FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms Typical Application Diagram FIGURE 10. Terminated Input Fail-Safe Circuit DS90LV019 4 LVDS TTL LVDS / TTL ( ) 0.1 F 0.01 F F 3 10 F(35V) 7

9 DS90LV019 ( ) 10mm 1mm 3mm ( v c/er c( ) mm/ps in/ps) DS90LV019 (7mm 12mm ) 1 2 LVDS LVDS (100k ) (2pF ) (FET ) 3GHz LVDS 100 ( ) EMI( ) 50cm 50cm 10m CAT3(category3) 10m CAT5 TABLE 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H FULL DUPLEX MODE H L X High or Low logic state Z High impedance state L Low state H High state TABLE 2. Transmitter Mode INPUTS OUTPUTS DE DI DO DO H L L H H H H L H 2 & 0.8 X X L X Z Z X High or Low logic state Z High impedance state L Low state H High state TABLE 3. Receiver Mode INPUTS RE (RI ) (RI ) OUTPUT L L ( 100 mv) L L H ( 100 mv) H L 100 mv & 100 mv X H X Z TABLE 4. Device Pin Description Pin Name Pin # Input/Output Description D IN 2 I TTL Driver Input DO 11, 12 O LVDS Driver Outputs RI 9, 10 I LVDS Receiver Inputs R OUT 4 O TTL Receiver Output RE 8 I Receiver Enable TTL Input (Active Low) DE 1 I Driver Enable TTL Input (Active High) GND 7 NA Ground V CC 14 NA Power Supply (3.3V 0.3V or 5.0V 0.5V) 8

10 inches (millimeters) DS90LV019 Order Number DS90LV019TM NS Package Number M14A 9

11 DS90LV019 LVDS1 / millimeters ( ) Order Number DS90LV019TMTC NS Package Number MTC14 1. (a) (b) TEL.(03) /

12 IMPORTANT NOTICE