DM-24 SM

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1 MAIN PCB CPU BLOCK DIAGRAM (part ) TASCAM DM- CARD CARD MOTHER PCB TC IN MIDI PCB J0 MIDI IN J0 MIDI OUT J0 J0 U0 U0 J J P 0 0 U0 U U U U U U LRCK Fs LRCK_CHECK (FS/0) VCC D D BT SRAM(U) R MAIN CPU (U) 0 PE MCK.MHz AN0 PE 0 IR IR IR 0 IR TIOCB 0 IR TIOCB IR TIOCA IR TIOC0D IR TIOC0C C 0 TIOCA TIOC0B TIOC0A RXD TXD RXD0 TXD0 0 EXTAL RD RESET WRL U MPG0 MPG MPG MPG MPG U MPH0 MPH MPH MPH MPH #INT DSP U0 U 0 FLAG FLAG0 RESET FLAG0 RESET FLAG0 DSP (U) RESET DSP (U) DSP (U) DSP (U) MIDI THRU /MTC OUT P0 0 TDIF REMOTE U Dual Port RAM (U) INT L OE L R/*W L 0 RESET DSP (U) FLAG0 RESET DSP (U) DIG I/O PCB P0 RS- C.ROOM PCB SOLO VR P P U INT R OE R R/*W R 0 U0 0 FLAG0 RESET FLAG0 RESET DSP (U0) DSP (RESERVE) FADER PCB ch ch ch ch ch ch ch 0ch ch ch ch ch ch ch ch ch ch MF0 MF MF0 MF MF0 MF MF0 MF MF0 MF MF0 MF MF0 MF MF0 MF MF0 VR+ P, 0 U 0 U 0 U 0 PANEL CPU (U) 00 AVCC PA AN PA AN PB AN PB AN PE AN PE AN0 PE AVSS PE IR IR RXD TXD RXD0 TXD0 0 EXTAL RD RESET WRL U-, U0-, U-, U- U-, U0-, U- X U 0kHz RESET #RESET MAIN U-, U-, U-, U-, etc. U VCC -V -0V U U0 U U FLAG0 RESET P P P0 P

2 MAIN PCB CLOCK CIRCUIT BLOCK DIAGRAM TASCAM DM- (MAIN PCB CIRCUIT DIAGRAM page ) U XCXL (PLD for CLK) (page ) WORD IN (P-pin) SLOT- LRCK (P-pin) (page ) SLOT- LRCK (P-pin) ADAT IN LRCK (U0-pin) 0 / U / U-0pin (page ) D.IN LRCK (U-pin) D.IN LRCK (U-pin) TDIF-A LRCK (P-0pin) U 0 X 0kHz MPN0 MPN MPN / or /0 PLL CMP U U PLL U LPF U VCO U BUFFER (page ) TDIF-B LRCK (P-0pin) MPH U0 (page ) ONLY MAIN PCB Ver. MPL MPL MPL MPL MPN 0 0 U-pin, U-pin U-pin (page ) P-pin U-pin U-pin (page ) U-pin Fs U U Fs U-pin / (page ) / / Fs Fs U U-pin, U-pin, U-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin (page ) U-pin, U-pin, U0-pin, U-pin (page ) P-pin W.SYNK R0 / / Fs U-pin (page ) U-pin, U-pin, U-pin, U-pin (page ) U-pin, U-pin, U0-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin (page ) Fs P-pin Fs R0 / CLK D-FF DATA W.SYNK U U-pin (page ) U-pin (page ) Fs U-pin Fs P-pin / U-0pin, U-0pin (page ) U-0pin, U-0pin (page ) U-0pin, U-0pin (page ) Fs P-pin (Fs) (Fs) / / Fs(D=%) Fs U0-0pin, U-0pin (page,0) U-pin U-pin (page ) (Fs) U-pin U-pin (page ) (Fs) Fs(D=%) U-pin Fs U-pin Fs U-pin Fs P-pin WORD U-pin Note: port N bit = H bit = L bit = L bit = L / CLK D-FF DATA Fs WORD 0 PLL SIG 0 U U MPN MPN MPN MPN (page ) MPG MPL0 U0 0 U 0 P-pin U-pin, U-pin, U0-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin, U-pin (page ) U-pin (page ) P-pin (page ) U-pin, U-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin U-pin, U-pin, U-pin (page ) U-pin, U-pin, U-pin, U-pin

3 MAIN PCB IOX BLOCK DIAGRAM TASCAM DM- MOTHER PCB J P0 PAGE IN IN IN IN IN IN IN IN IN IN 0 IN IN IN IN SLOT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 0 OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN 0 IN IN IN IN SLOT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 0 OUT OUT OUT OUT TDIF (P0) P IN IN IN IN OUT OUT OUT OUT TDIF (P0) IN IN IN IN OUT OUT OUT OUT TDIF (P0) P IN IN IN IN OUT OUT OUT OUT OPT IN (U0) P OPT OUT (U0) TDIF PCB MIC AMP ch P0 MIC AMP ch MIC AMP ch MIC AMP ch MIC AMP ch P0 MIC AMP ch MIC AMP ch MIC AMP ch MIC AMP ch P0 MIC AMP 0ch MIC AMP ch MIC AMP ch MIC AMP ch P0 MIC AMP ch MIC AMP ch MIC AMP ch INPUT PCB P P P P P P P J P LV0 (U) PAGE PAGE IOX OUT LV IOX OUT (U) IOX OUT IOX OUT IOX OUT IOX OUT IOX OUT IOX OUT IOX OUT LV IOX OUT (U) IOX OUT IOX OUT IOX OUT IOX OUT IOX OUT LVC0 IOX OUT (U) IOX OUT IOX OUT IOX OUT LVC0 IOX OUT (U) IOX OUT IOX OUT IOX OUT LVC0 IOX OUT (U) IOX OUT IOX OUT 0 ADAT Receive (U0) IOX OUT ADAT IOX OUT Transmitter IOX OUT (U) IOX OUT, ADC (U),, ADC (U),, ADC (U0),, ADC (U),, ADC (U),, ADC (U),, ADC (U),, ADC (U), HC0 (U) TDIF IN TDIF IN TDIF IN TDIF IN LV (U) SLOT IN SLOT IN SLOT IN SLOT IN LV (U) SLOT IN SLOT IN SLOT IN SLOT IN HC0 (U) TDIF IN TDIF IN TDIF IN TDIF IN LV (U) SLOT IN SLOT IN SLOT IN SLOT IN LV (U) SLOT IN SLOT IN SLOT IN SLOT IN HC0 (U0) TDIF IN TDIF IN TDIF IN TDIF IN LV (U) SLOT IN SLOT IN 0 SLOT IN SLOT IN LV (U) SLOT IN SLOT IN 0 SLOT IN SLOT IN LV (U) ADAT IN ADAT IN ADAT IN ADAT IN LV (U) SLOT IN SLOT IN SLOT IN SLOT IN MPJ PAGE LV 0 (U /) MPJ0 MPJ LV (U /) MPJ MPJ LV 0 (U /) MPJ MPJ Contents of the circuit schema PAGE MAIN CPU PAGE PANEL CPU PAGE BUFFER for the SLOT PAGE INPUT SELECTOR for IOXs PAGE IOXs PAGE DSP & DSP PAGE DSP & DSP 0 VHC (U) DRB DSP (U) PAGE PAGE LV (U) ADC IN ADC IN ADC IN ADC IN ADC IN ADC 0 IN ADC IN ADC IN OUT OUT OUT OUT 0 IOX (U) IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT IOX (U) IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT IOX (U) OUT OUT OUT OUT 0, ADC, CODEC (U) DAC DAC DAC ADC CODEC (U) DAC DAC DAC ADC CODEC (U) DAC DAC DAC PAGE DSP, DSP & SDRAMs PAGE DSP (for EFFECTOR) PAGE 0 DSP (RESERVE) PAGE PLL & DIGITAL I/O PAGE ADCs for - inputs PAGE CODECs & ADC for TBM PD0 PD PA0 PA PCS* PCS PWR* PD0 PD PA0 PA PD0 PD PA0 PA 0 PCS* 0 PCS PWR* PCS* PCS PWR* 0 0,, 0 IOX DATA BUSS DSP ADRESS BUSS PAGE P,,, 0, P P P P (reserve) LV (U) LV (U) LV (U) PLD for IOX (U0) ADRESS DECODE RD/WR TIMING Fs MAIN PCB DSP DATA BUSS DATA0 - ADDR0- DSP (U) PAGE 0 P0 STUDIO PCB P0 P0 ADDR ADDR RD* WR* STUDIO OUT L STUDIO OUT R A.RTN (H&C) A.RTN (H&C) A.RTN (H&C) A.RTN (H&C) A.SEND A.SEND A.SEND A.SEND P STEREO OUT L STEREO OUT R MASTER PCB P0 C.ROOM OUT L C.ROOM OUT R METER IN L METER IN R C.ROOM PCB

4 MAIN PCB DSP BLOCK DIAGRAM TASCAM DM-

5 MAIN PCB DSP Architecture / (Overview) TASCAM DM- U- MTR MTR MTR AK AK IOX * MTR MTR MTR AK CS0 CS0 DRA DRB U DTA DTB CS SDRAM K * * SRAM K * U, U, U HOST CPU DSP# A A A A A DSP# DSP# U DSP# DSP# DRA DRB DTA DT DRA DRB DTA DT A DRA DRB DTA DT DRA DRB DTA DT U U DSP# U U AK AK DRA DRB DTA DT CS CASCA A DSP# DR0 DR Audio serial port U0 DSP# DR Data/Address buss IF-CS/DM (option)

6 MAIN PCB DSP Architecture / (DSP # & ) TASCAM DM- U U U PCS* PCS PWR ADDRESS0- MS0 U- U U U U SRAM IOX IOX IOX DATA0- DATA0- U- U U- R LRCK INT_DSP(#) INT_DSP(#) CALL DSP# CALL DSP# DSP_MUTE CPU U0 A AUX out, EFF out BUSS output DSP # Performance check IOX data inout STEREO MASTER CROOM, STUDIO R R00 R0 R0 U FLAG IR IR FLAG0 FLAG MS0 MS RD WR Addr0- DATA0- A R R R R0 IOX input data () IOX input data () IR IR FLAG0 FLAG MS0 MS RD WR Addr0- DATA0- FLAG A Performance check U R R R R DSP # INPUT SELECT TRIM NOISE GATE CH-/- Post GATE MON-, RTN, Digital OUT U U TFS DTA DT Post FADER () Digital in, Insert out R R0 R R RFS RCLK DRA DRB TFS DTA DT R R R R IOX input data () Eff RTN, Digital OUT RFS RCLK DRA DRB TFS DTA DT R R R R CH-/- Post GATE MON-, RTN, Digital OUT U

7 MAIN PCB DSP Architecture / (DSP # & ) TASCAM DM- U A R R R R CH-/- Post GATE MON-, RTN, Digital OUT A R R R R CH-/- Pre FADER MON-, RTN, Digital IN U U DIR U DIR U R U R R R DSP # Performance check LRCK_DIO BCLK_DIO DIGITAL in DIGITAL in COMP -/- E -/- U RFS TFS RCLK DRA DTA R0 DRB DT PWM_EVENT R DATA0- Addr0- MS0 RD WR FLAG FLAG0 IR FLAG IR U DIT DIGITAL out FADER TOUCH SENSE CLOCK U0- ADDRESS0- MS0 U0 U0 U- DATA0- U U SRAM U R LRCK_DSP U TFS DTA DT R R R R Performance check DSP # U COMP -/- E -/- CH-/- Post GATE MON-, RTN, Digital OUT FLAG IR IR FLAG0 FLAG MS0 RD WR Addr0- DATA0- R R A R R CH-/- Pre FADER MON-, RTN, Digital IN CALL DSP# CALL DSP# INT_DSP(#) INT_DSP(#) DSP_MUTE U RFS RCLK DRA DRB CPU R R TB MIC in METER data RFS RCLK DRA DRB TFS DTA DT R U DIT DIGITAL out

8 MAIN PCB DSP Architecture / (DSP # & ) TASCAM DM- U SDRAM U BA CLK RAS CAS WE LD CKE A0 ADDRESS0- ADDRESS DATA0- ADDRESS0- MS0 DATA0- U-00 U0 U0 U0-0 U U SRAM U R LRCK INT_DSP(#) INT_DSP(#) CALL DSP# CALL DSP# DSP_MUTE CPU DSP # CH FADER CH DELAY AUX sssign Performance check U FLAG IR IR FLAG0 FLAG SDCLK RAS CAS SDW DM SDCK SDA IR IR FLAG FLAG SDCLK RAS CAS SDW DM SDCK SDA FLAG Performance check U BUSS assign DSP # MASTER COMP MASTER FADER MS RD WR MS0 RD WR U A R R R R CH-/- Pre FADER MON-, RTN, Digital IN Addr0- DATA0- A R R R R POST DELAY () POST DELAY () Addr0- DATA0- A R0 R R R AUX OUT, STEREO PRE BUSS OUT U0 U A R R R R CH-/- Pre FADER MON-, RTN, Digital IN RFS RCLK DRA DRB TFS DTA DT R R R R Post FADER () SUM data, Insert out RFS RCLK DRA DRB TFS DTA DT R R0 R R Post FADER () Digital IN, Insert out U RFS RCLK DRA

9 MAIN PCB DSP Architecture / (DSP #) TASCAM DM- U0 U0 U U ADDRESS0- ADDRESS0- U0 CE* OE* WE DATA0- DATA0- U0 SRAM SRAM SRAM SRAM U R LRCK Performance check DSP # U0 FLAG IR IR FLAG HBR HBG DSP_MUTE U0 CPU U0 A AUX out, STEREO Pre BUSS output Effect patching PLUG-in Effect R R R R RFS RCLK DRA DRB MS RD WR Addr0- DATA0- A TFS DTA DT R0 R R R AUX out, EFF out BUSS output U

10 MAIN PCB DSP Architecture / (DSP # IF-CS/DM) TASCAM DM- IF-CS/DM MAIN PCB U R LRCK IR FLAG0 FLAG HBG INT_DSP(#) ADDRESS0- U U MAIN PCB +V Performance check R R D D FLAG FLAG DATA0- U CPU DSP # U MASTER FADER FLAG FLAG HBR CALL DSP # U0 U A R R R R MASTER COMP CASCADE SUB in (AUX, ST) SUB in (BUSS) CS RD WR A R R R R U AUX out, STEREO Pre BUSS output U0 U R R R R CASC in (AUX, ST) CASC in (BUSS) RFS RCLK DRA DRB TFS DTA DT R0 R R R CASC out (AUX, ST) CASC out (BUSS) U 0

11 MASTER SECTION TASCAM DM- MAIN PCB MASTER PCB U U AK -0DO -DO DAC DAC P STEREO L STEREO R P0 U0B U0 J0 J0 STEREO INST L -DO -DO U AK DAC DAC P CROOM L CROOM R P0 CROOM PCB U0A J0 OUT L INST R U ADC AK METER L METER R P U0 CR U0 P0 U0 J0 OUT R U CR L U0 J0 IOX DRB DSP P0 P0 J0 CR R DRA P P P P0 TR IN U0 J BUSS PCB STUDIO PCB U0 STUDIO ADC P TB MIC P U0B U0 J -DO -DO U AK DAC DAC STUDIO L STUDIO R T/B U0 PHONES

12 MTR IN/OUT SECTION (TDIF/ADAT/SLOT) TASCAM DM- TDIF PCB [ INPUT ] [ OUTPUT ] TDIF PCB TDIF- P0 P0 TDIF- P P U P P U -DI -DO P0 IOX P0 U -DI -DO P0 U P0 P P U0 U -DI -DO P P ADAT IN U0 P P U0 AL0 IOX U AL0 P P U0 ADAT OUT P0- U SLOT U U SLOT J MAIN PCB J J U J SLOT U U SLOT J- MOTHER PCB P0- J- MOTHER PCB

13 MIC SECTION TASCAM DM- V PHANTOM - INPUT JACK PCB MIC AMP PCB MAIN PCB U S MIC LINE TRIM P P UA P0 + U - M/L ( H,C,G) P U AK IOX -DI INST UB + - U M/L ( H,C,G) U AK -DI S PHANTOM - S PHANTOM - S PHANTOM - 0 P P P P P P P P P P P P P P P0 P0 P0 M/L ( H,C,G) M/L (H,C,G) M/L ( H,C,G) M/L (H,C,G) M/L ( H,C,G) M/L (H,C,G) M/L ( H,C,G) M/L0(H,C,G) M/L( H,C,G) M/L(H,C,G) M/L( H,C,G) M/L(H,C,G) M/L( H,C,G) M/L(H,C,G) P P P U0 AK U AK U AK U AK U AK U AK -DI -DI -0DI -DI -DI -DI

14 ASSIGNABLE SEND/RETURN & DIGITAL IN/OUT SECTION TASCAM DM- J0 J0 J0 J0 P0 P ADC ADC U AK U -DI -DO IOX -DI -DO U DAC DAC P MASTER PCB P0 U0 U0 J0 J0 J0 J0 AK ASSINABLE RETURNS ASSINABLE SENDS J0 J0 U CS0 SFC DIR DTA DRA DIT U U P DIO PCB J0 J0 DIGITAL INPUTS DSP U J0 J0 SFC DIR DR U DIGITAL OUTPUTS P0 P U CS0 J0 MAIN PCB DSP DTA U DIT U J0 P0

15 POWER SUPPLY SECTION TASCAM DM- P0 POWER SW PCB P0 POWER CN -00 SW POWER UNIT CN CN0 CN To PCBA,MOTHER To PCBA,MOTHER To PCBA,MAIN ~IN SW0 P0 JP mounted: DM T/C JP NO mounted: EUR CN CN To PCBA,FADER To PCBA,LCD SUB&PANEL&TDIF EUR (0V) W0 W0 W0 TR P P P To PCBA,INPUT To PCBA,INPUT To PCBA,MASTER CN T/C (0V) P P P To PCBA,MAIN To PCBA,MOTHER W0 W0 W0 CN DM(00V) W0 W0 W0 CN POWER TRANS POWER PCB TRANS PCB TRANS PCB

16 PARTS LIST SECTION TASCAM DM- NOTES º PC boards shown are viewed from parts side. º Parts marked with require longer delivery time. º The parts with no reference number or no parts number in the exploded views are not supplied. º As regards the resistors and capacitors, refer to the circuit diagrams contained in the manual. º Parts marked with this sign are safety critical components. They must be replaced with identical components - refer to the appropriate parts list and ensure exact replacement. º Parts of [ ] mark can be used only with the version designated. [ J ] : JAPAN [ K ] : KOREA [ A ] : AUSTRALIA [ US/C ] : U.S.A./CANADA [ E ] : EUROPE [ UK ] : U.K. º º º º º º [ J ] : JAPAN [ K ] : KOREA [ A ] : AUSTRALIA [ US/C ] : U.S.A./CANADA [ E ] : EUROPE [ UK ] : U.K.

17 . EXPLODED VIEWS AND PARTS LIST EXPLODED VIEW- TASCAM DM- 0 q q w e Z F r t t y P u i o p D S a a a a s d d f g g h h h j g k l ; z x ) x c v b n ( m,,.. # $ % ^ & * W W E E R A R R R R T Y Y Y U U I To Side Panel, R To Rear Panel To Side Panel, L O X C V B N

18 EXPLODED VIEW- TASCAM DM-

19 EXPLODED VIEW- TASCAM DM-

20 EXPLODED VIEW- TASCAM DM- 0 q w e r r t y u u i o p a s d f g h j k l ; z # # # ^ ^ & * ( * ) W E R To Top Panel To Top Panel T A S D F G HJ K L : 0

1. SPECIFICATIONS Specifications Analog I/O Mic input 1-8 (Balanced) Connector: 3-pin XLR jack x 8 (1: GND, 2: Hot, 3: Cold) Input impedance: 2.2k ohm

1. SPECIFICATIONS Specifications Analog I/O Mic input 1-8 (Balanced) Connector: 3-pin XLR jack x 8 (1: GND, 2: Hot, 3: Cold) Input impedance: 2.2k ohm SERVICE MANUAL FW-1884 Professional Control Surface/FireWire Audio-MIDI Interface CONTENTS 1. SPECIFICATIONS 2 2. BLOCK DIAGRAM 6 3. LEVEL DIAGRAM 7 4. EXPLODED VIEW AND PARTS LIST 8 5. PC BOARDS AND PARTS