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1 1
2 ( ) ispvm system I/O... 7 USB ( ) ( ) Dual Boot Primary Image file USERCODE/UES I/O ATE SVF SVF SVF VME VME C CPU Universal File Writer Application Specific BSDL File Generator Model ()
3 SVF
4 ( ) isplever Lattice isplever HP (1) isp (2) (3) (4) / (5) /UES (6) (7) I/O (8) VME /VME-Processor (9) ATE HP, Genrad, Teradyne Marconi ATE AET (10) SVF (11) SVF (12) IEEE1532(ISC) (13) FPGA (14) (15) XML (.XCF ) TDI TDO JEDEC BYPASS ( 1 ) SVF /ispen /ENABLE /TRST /BSCAN /EPEN BSCAN ( I/O HiZ) 4
5 ispvm system Windows [] [ ] [Lattice Semiconductor] [] isplever Project Navigator isplever Project Navigator 1-1 ispvm isplever 5
6 Lattice PC USB 25pin 1-3 Vantis PC USB 6
7 PC 3 [isptools] [Device Scan] F2 ISP JTAG ISP Mix Scan 1-4 SCAN SCAN 1-4 JTAG-NOP I/O SCAN [Options] [Cable and I/O Setup] 7
8 I/O 1-5 I/O I/O Cable Type Lattice Vantis Vantis USB USB Port Setting Auto Detect ( Vantis ) Custom Port 0x TRST/Reset Pin Connected Done Pin Connected ispen/bscan Pin Connected Prog Pin Connected INIT Pin Connected TRST DONE ispen/bscan Prog INIT ON Set High Active High Set Low Active Low OFF: ON OFF: ON Set High Active High Set Low Active Low OFF: ON OFF: ON OFF: Windows XP USB 8
9 USB Admin ispvmsystem 1-6 USB 1-6 USB USB USB PC Wizard Wizard 1-8 9
10 1-9 C: WINDOWS Sysytem Lattice USB ISP Programmer Lattice USB ISP Programmer ispvmsystem
11 Windows USB Lattice USB ISP Programmer 1-12 USB 11
12 1-4 SCAN Data File Browse EC/ECP/ECP2/SC bit rbf XP/XO isc jed 1-2 Fast Program Erase,Programming,Verify Erase,Programming,Verify,Secure Verify Only Verify ID Erase Only Display ID Bypass Calculate Checksum Verify USERCODE Display USERCODE Read and Save JEDEC Read DONE bit 1-2 (*1) DONE bit *1 Verify,Checksum 12
13 Device Access Options Device Access Options (EC/ECP/ECP2 ) JTAG 1532 Mode Static RAM Cell Background SPI Flash Programming Advanced SPI Flash Programming Serial Mode JTAG JTAG SPI FPGA SPI 1-4 Device Access Options (SC ) JTAG Mode Serial Mode JTAG 1-5 Device Access Options (XP/XO ) Flash Programing Mode Flash Background Mode Static RAM Cell Mode Static RAM Cell Backgournd Mode SRAM SRAM 13
14 ( ) GO () ( ) 1-14 PASS DONE Operation FAIL PASS DONE ( ) FAIL ispvm( ) LOG [Edit] [Clear Log File] 14
15 JTAG u [File] [Save] Save 1-15 xcf spvm Systemu [File] [Save] ( ) ( ) 15
16 ( ) ispvm Dual Boot Lattice ECP2/ECP2M SPI Flash Dual Boot ispvm SCAN 2-1 ECP2/M Device List
17 2-2 Device Access Options Dual Boot SPI Flash Programming SPI Flash Options 17
18 2-3 SPI Flash 6 Flash Device Select SPI Flash Data File Browse Operation SPI Flash Erase,Program,Verify Golden Boot File Primary Boot File Golden Boot File Primary boot file Primary Boot File Generate OK 18
19 Primary Image file ispvm Primary Image File Dual Boot Log Primary Image Golden Image 2-4 LOG ispvm LOG Golden Primary Start Enc Primary Primary 2.2 SPI Flash 19
20 2-6 SPI Flash 6 Flash Device Select SPI Flash Data File Browse Operation SPI Flash Erase,Program,Verify Staring Address Ending Address OK 20
21 USERCODE/UES FPGA USERCODE USERCODE [Option] [Dsiplay USERCODE/UES Options] 2. Device Information [Advanced] [Advanced Device Information] 3. [USERCODE/UES Field]UES [Apply UES] 4. [Auto-Increment After Program by] USERCODE/UES USECODE USERCODE/UES Field in 2-8 Advanced Device Information 21
22 I/O I/O 1. [Device Information] 2. [Expand] 3. [Device Information][I/O Status] I/O I/O 2-9 Device Information I/O 2-1 CustomDynamic IO BSDL Edit 2-1 Device Access Options (EC/ECP/ECP2 ) High-Z(Default) All 1 s All 0 s Leave Alone Custom Dynamic IO Caputure Hi-Z High Low I/O ( High-Z ) Leave Alone Custom Leave Alone Edit I/O Dynamic 22
23 I/O CustomDynamic IOBSDL BSDL HP () BSDL EDIT [IO Vector Editor] 2-10 I/O Vector Editor [IO Vector Editor] I/O ( ) [Apply] [Save As] I/O (*.iov) 23
24 [Project] [Project Setting] Sequential Program Turbo Program Entire Chain Selected Device Operation Override Disable Board Setup Checking Avoid Test Logic Reset State Continue Download Even on Error Starting/Ending TAP State (JTAG ) (Lattice /) JTAG Test Logic Reset JTAG 24
25 [Advance] 2-12 () 2-3 () TCK Low Pulse Width Delay Comment TCK 25
26 ATE (ATE : Automatic Test Equipment) ATE Gen Rad HP 3070 HP 3065 Teradyne 1800 Teradyne L200/300 SVF(Serial Vector Format) ATE SVF ATE SVF : isptools ispvmsystem documents svf_standard.pdf ATE Project Generate ATE Vector ATE 2-13 ATE 26
27 Tester Type 2-14 ATE 2-14 ATE Tester Type Header File Advanced More 2-15 ATE Advanced Options 27
28 2-4 Split File Maximum number of vectors per file Split File without initialization Program Vectors Only Erase Vectors Only Vector Signal Order HP-PFC Data ATE ispen,mode SCLK ATE More OK ATE Advanced Options ATE Generate ATE 28
29 SVF SVF Project Generate SVF File SVF SVF 2-16 SVF SVF 2-17 SVF Options Build SVF File For Single Device Generate SVF 2-17 SVF () 29
30 SVF SVF 2-18 SVF Options Build Sequential Chain SVF File Generate SVF 2-18 SVF () 30
31 VME VME VME VME VME Project Generate SVF File VME 2-19 VME VME VME12 VME11 VME** ** VME 2-20 VME 31
32 Programing Mode Continue If Fail Turbo VME File Compress VME File Loop VME FIle Commnet VME Program Setting.. Turbo VME VME VME Generate VME 32
33 C 2-20 VME VME2HEX 2-21 VME HEX 2-21 VME HEX Generate 2-22 ( c) ( h) 2-22 C 33
34 ispvm CPU ispvmsystem ispvmembedded SoureCode readme.txt CPU FPGA CPU CPU Project Generate SVF File CPU 2-23 CPU CPU 2-24 CPU
35 2-6 Format Comment Output File Advanced Configuration Mode Byte Wide Bit Mirror Binary C-CODE Intel-HEX HEX Text( ) ON Browse CFG HEX MSB LSB Generate CPU 35
36 isvvm System : ispvm ispvm.exe infile <> /-processtype< >/-cabletype< >/-portaddress< >/-processmode< > 2-7 () ( ) ( ) ( ) ( ) USB ( ) xcf dld (turbo) (sequetial) (lattice) (vantis) USB (usb) LPT1(0x0378) LPT2(0x0278) LPT3(0x03BC) (0xXXXX)LPT1(0x0378) Ezusb-15 Ezusb-0 (-h)(-o) (-w) C: isptools ispvmsystem ispvm.exe -infile C: demo demo.xcf -processtype turbo -cabletype lattice -portaddress 0x
37 Universal File Writer Universal File Writer( UFW) UFW isptools Universal File Writer UFW 2-25 VME UFW 2-26 Universal File Writer(UFW) UFW 37
38 EC/ECP/ECP2 UFW UFW Bitstream Bitstream Settings [Compression] ON
39 Application Specific BSDL File Generator Application Specific BSDL File Generator BSDL(Boundary Scan Description Language) VREF LVDS I/O BSDL VREF LVDS BSDL JEDEC ISC BSDL WEB Application Specific BSDL File Generator s isptools Application Specifig BSDL File Generator BSDL BSDL 2-28 Application Specific BSDL File Generator BSDL BLDL Generate 39
40 Model300 Model300 Lattice ISP/JTAG Model300 Model300 Vcc 1.8V,2.5V,3.3V 5.0V ispvm Model300 AC Web 2-29 Model300 40
41 Model300 Model300 Programmer isptools Model300 Programmer ( M300 ) 2-30 Model300 Programmer Model300 Programmer Auto-Detect ( ) LED ( Model300 ) Go Status ( ) 41
42 () JTAG / IDCODE JTAG isptools Board Diagonostics 3-1 JTAG / 3-1 IDCODE IDCODE JTAG IDCODE 1 0 TCK TMS 42
43 isptools Repetitive Download 3-2 (Number of) (Stop on Error Number) OK Options Cable and I/O Port Setup Cable and I/O Setting Debug Mode
44 3-4 Loop ESC Power Check Test Setting Toggle Hold High Hold Low 0 Read(TDO Only) TDO Apply Loop View Log Cable Signal Test operations Power Check 44
45 SVF SVF SVF ISP/JTAG JEDEC SVF SVF SVF CPLD SVF 16 SVF SVF SVF isptools SVF Interpreter SVF 3-5 SVF SVF SVF Advanced Debug SVF 45
46 SVF 3-6 Configuration SVF Options ( SVF Options ) SVF Options 3-6 SVF SVF Options 3-7 JTAG 3-7 SVF Options 46
47 Configuration SVF Output JTAG TAP 3-9 SVF Output () 47
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