インテル(R) アーキテクチャ (IA) 浮動小数点ユニット (FPU)、ストリーミング SIMD 拡張命令 (SSE)、ストリーミング SIMD 拡張命令2 (SSE2) を使用した浮動小数点算術演算
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- ふじきみ りゅうとう
- 6 years ago
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1 (IA) (FPU) SIMD (SSE) SIMD 2(SSE2) : J /12/06 1
2 Fax: * Copyright Intel Corporation 1999, /12/06 2
3 IA FPU FPU FPU NaN FPU SIMD SIMD SIMD / NaN SIMD SSE SIMD SIMD SIMD / NaN SSE SSE /12/06 3
4 2.0 Pentium [1] IEEE Standard for Binary Floating-Point Arithmetic ANSI/IEEE Std [2] 1999 [3] Visual C On-Line Manual Microsoft Corporation 1999 (FPU) (x87 ) SIMD (SSE) SIMD 2(SSE2) x87 2 IEEE 01/12/06 4
5 1. (IA) Pentium III IA 3D / SSE SSE2 SIMD(Single Instruction, Multiple Data) SSE 3D SSE MMX SSE SSE 64 SIMD SSE2 SIMD SIMD IA-32 SIMD SSE2 128 SIMD 64 MMX x87 SSE SSE2 2 IA (FPU) NaN FPU ( ) IA-32 FPU IEEE [1] FPU IA FPU / SSE SSE2 ( ) ( ) FPU 3 SSE / NaN SSE 2 4 SSE2 3 5 FPU SSE SSE2 SSE SSE2 FPU 01/12/06 5
6 2. IA FPU 0( ) 1( ) [E min, E max ] [1, 2] 2 ( J = 1 ) ( ) f = (-1) 2 ulp(unit-in-the-last-place) ulp 1 ulp = = 2 N + 1 N IA FPU 3 ( ) ( 2 IEEE [1]) 1 FPU IA FPU 1: IA-32 FP IA-32 FP ( ( IA-32 IA-32 ) ) (40 80( ) 0) ( ) E min E max ( ) ( ) ( ) ( ) ( ) ( ) ( ) 01/12/06 6
7 ( ) : 0( E min ) 0 : : NaN(Not a Number): ( ) NaN 0 NaN NaN(SNaN) ) 1 NaN NaN(QNaN) QNaN QNaN ( =1 =11 1 =110 0) ( - ) FPU NaN FPU J = FPU IA FPU FPU 8 80 ( BCD ) FPU ( ) 2 FPU TOP ST(0) ST(1) ST(2) ST(7) ST(0) ST(0) ST(1) ST(1) ST(2) ( ) 8 ST(0) ST(1) ST(0) ST(2) ST(1) ( ) FXCH 01/12/06 7
8 FPU 8 FPU 1 1 FPU 0 1 (FPU 11 ) FPU (FPU 48 ) FPU ( ) (FPU 48 ) FPU ( ) ( ) MMX MMX FPU MMX FPU EMMS EMMS FPU ( 1) MMX FPU MMX MMX FPU ( 0) TOP 0 TOP 0 0 FPU FPU MMX FPU 2.2 FPU 1 16 FPU 0 5(IM DM ZM OM UM PM) FPU ( ) 8 9 (PC) FPU PC=00B 24 PC=10B 53 PC=11B 64 PC=01B ( IA ) PC (RC) 01/12/06 8
9 IEEE [1] RC=00B RC=01B RC=10B RC=11B 12(X) ( ) ([1] 7.4 ) ( E max ) ( 0 E min ) ( ) (FPMAX = Emax ) ( 0 E min ) (FPMIN = Emin ) 0 X RC PC PM UM OM ZM DM IM : FPU 2 16 FPU FPU 0 5(IE DE ZE OE UE PE) 1 0(IE) 7(SF) ( ) ( ) (C1 = 0) (C1 = 1) 9(C1) 7(ES) (C0 C1 C2 C3) (C0 C2 C3 ) PE C1 = 1 [2] TOP 14(B) FPU 01/12/06 9
10 B C3 TOP C2 C1 C0 ES SF PE UE OE ZE DE IE : FPU 1: [1] 1 2 a b E min = -126 a = b = a b = ( ) ( ) = ( ) a b = ( 24 ) a b = ( ) a b = ( ) a b = ( ) a b = ( ) ( 24 ) ( 24 ) a b = (P ) a b = (P U ) a b = (P ) a b = (P U ) FPU (#I)(#IS - #IA - ) (#D) (#Z) (#O) 01/12/06 10
11 (#U) ( )(#P) 6 FPU / ( ) FPU ( ) ( ) ( ) FPU ( ) FPU (#I #D #Z) ( ) FPU SNaN ( QNaN) ( ) ( ) / 0 / 0 ( ) (IEEE [1] ) 0 0 FPU FPU FPU PC ( ) 15 ( ) MAXFP FPU ( ) FPU (2.7 8 ) FPU ( ) FPU 01/12/06 11
12 C1 C1 (C0 C3 ) (2.7 9 FPU FPU FPU PC ( ) 15 FPU ( ) FPU FPU ( ) FPU C1 C1 FPU / SNaN ( QNaN) QNaN ( QNaN ) ( ) FPU WAIT/FWAIT ( ) 01/12/06 12
13 ( WAIT/FWAIT ) 2: 1 2 a b a = b = ( FMUL FST 2 5 ) 24 ( 1 ) FMUL (IA-32 ) IA a b = a b = a b = a b = FST (32 ) FST P U P ( ) ( ( ) FPU FPU 01/12/06 13
14 ( ) / / FPU FPU / / FPU ( ) ( ) 2.4 ( ) ( ) (MS-DOS ) 2 CR0.NE CR0 NE (CR0.NE=1) ( FPU WAIT ) MMX 16(#MF) MMX ( ) (MS-DOS ) CR0 NE (CR0.NE=0) CPU FERR# (CR0.NE=1 ) FERR# MMX Inteli486 TM FERR# IGNNE# MMX IGNNE# 01/12/06 14
15 (PIC) ( )INTR# 2 )#NMI MMX CPU MMX FPU FPU ( ) FPU 2.5 NaN QNaN( NaN) ( ) QNaN QNaN/0.0 QNaN 2 FPU QNaN SNaN QNaN FPU SNaN SNaN 1 FPU SNaN FPU FRSTOR FPU (8 ) SNaN FRSTOR SNaN FPU SNaN FPU SNaN QNaN NaN NaN NaN NaN 2 (2 NaN 0 NaN ) Pentium Pro IA ( ) 01/12/06 15
16 2: FPU QNaN SNaN QNaN 2 SNaN 2 QNaN SNaN QNaN QNaN QNaN SNaN QNaN( NaN) SNaN QNaN QNaN QNaN SNaN QNaN( NaN) QNaN NaN QNaN 2.6 FPU FPU FPU 2.7 SSE SSE2 FPU FPU FPU FPU ( )6 FPU [2] 1. FLD: floating-point load FPU 80 FPU ST(0) : I D FST/FSTP: floating-point store - ST(0) FSTP 80 : I O U P FXCH: ST(i) ST(0) : 01/12/06 16
17 FCMOVcc: EFLAG CF ZF PF ST(i) ST(0) : FILD: FPU ST(0) : FIST/FISTP: ST(0) FISTP 64 : I P FBLD: 80 BCD FPU : FBSTP: FPU ST(0) 80 BCD ST(0) : I P 2. FLDZ FLD1 FLDPI FLDL2T FLDL2E FLDLG2 FLDLN2: log 2 10 log 2 e log 10 2 log e 2 ST(0) : 3. FADD/FADDP: floating-point add ST(0) ( 1 ) FADDP : I D O U P FIADD: FPU ST(0) : I D O U P FSUB/FSUBP/FSUBR/FSUBRP: floating-point subtract FSUB/FSUBP FADD/FADDP ( ST(0) 1 ) FSUBR/FSUBRP FSUB/FSUBP : I D O U P FISUB/FISUBR: subtract integer (converted to double-extended format) from floating-point FIADD ( ST(0) 1 ) FISUBR FISUB : I D O U P 01/12/06 17
18 FMUL/FMULP: floating-point multiply FADD/FADDP : I D O U P FIMUL: multiply floating-point and integer (converted to double-extended format) FIADD : I D O U P FDIV/FDIVP/FDIVR/FDIVRP: floating-point divide FDIV/FDIVP FADD/FADDP ( ST(0) ) FDIVR/FDIVRP FDIV/FDIVP : I D Z O U P FIDIV/FIDIVR: divide floating-point to integer (converted to double-extended format) FIADD ( ST(0) ) FIDIVR FIDIV : I D Z O U P FSQRT: : I D P FRNDINT: FPU : I D O U P FABS: : FCHS: ST(0) : FPREM: partial remainder ST(0) ST(1) ST(0) ( ) : I D U FPREM1: IEEE partial remainder ST(0) ST(1) IEEE [2] ST(0) ( ) : I D U FXTRACT: ST(0) ( 0x3fff ) : I D Z 4. FCOM/FCOMP/FCOMPP: compare real - FPU FPU FCOMP ST(0) FCOMPP FPU 2 FPU C3 C2 C0 QNaN : I D 01/12/06 18
19 FUCOM/FUCOMP/FUCOMPP: unordered compare real FCOM/FCOMP/FCOMPP QNaN : I D FICOM/FICOMP: FPU FICOMP ST(0) FPU C3 C2 C0 QNaN : I D FCOMI/FCOMIP: FPU FPU EFLAGS FCOMIP ST(0) QNaN : I FUCOMI/FUCOMIP: FCOMI/FCOMIP QNaN : I FTST: ST(0) 0.0 FPU C3 C2 C0 : I D FXAM: ST(0) NaN 0 FPU C3 C2 C0 : 5. FSIN: ST(0) ST(0) : I D U P FCOS: ST(0) ST(0) : I D P(U ) FSINCOS: ST(0) ST(0) FPU : I D U P FPTAN: tangent - ST(0) tan(st(0)) FPU 1.0 ( 2 63 ) : I D U P FPATAN: arctangent - ST(1) arctan(st(1)/st(0)) ST(0) : I D U P 66 ( ) 01/12/06 19
20 6. FYL2X: ST(1) ST(1) * log 2 ST(0) ST(0) : I D Z O U P FYL2XP1: ST(1) ST(1) * log 2 (ST(0) + 1.0) ST(0) : I D O U P F2XM1: ST(0) 2 ST(0) 1 : I D U P FSCALE: ST(0) ST(1) : I D O U P 7. FPU ( ) FINIT/FNINIT: (FINIT) (FNINIT) 64 FPU FLDCW: 2 FPU FPU FPU FSTCW/FNSTCW: (FSTCW) (FNSTCW) FPU 2 FSTSW/FNSTSW: (FSTSW) (FNSTSW) FPU 2 AX FCLEX/FNCLEX: (FCLEX) (FNCLEX) FLDENV: ( )14 28 FPU 1 FPU FSTENV/FNSTENV: (FSTENV) (FNSTENV) ( )14 28 FPU FRSTOR: ( ) FPU FPU FPU 01/12/06 20
21 FSAVE/FNSAVE: (FSAVE) (FNSAVE) ( ) FPU FPU FINCSTP: FPU TOP ( ) FDECSTP: FPU TOP ( ) FFREE: ST(i) FNOP: FWAIT/WAIT: FPU FNINIT FNSTENV FNSAVE FNSTSW FNSTCW FNCLEX FNSTSW FNSTCW FPU FNSTSW FNSTCW 2.7 ( FPU ) C([3] ) FPU IA-32 mov IA-32 DWORD PTR 32 TBYTE PTR 80 IEEE [1] 16 ( 10 ) 0x (0) 8 ( ) 24 ( ) = x * /12/06 21
22 3: IEEE [1] fpexpr res if (fexpr == res) printf ( SUCCESS\n ); else printf ( FAIL\n ); eps if (-eps < fexpr res && fexpr res < eps) printf ( SUCCESS\n ); else printf ( FAIL\n ); x x ( x) rn x x ( ) (( x) rn * ( x) rn ) rn = x #include <stdio.h> void main () { float x, y, z; char *px, *py; int i; unsigned short cw, *pcw; // control word and pointer to it pcw = &cw; // set control word cw = 0x003f; // round to nearest, 24 bits, floating-point exc. disabled // cw = 0x043f; // round down, 24 bits, floating-point exc. disabled // cw = 0x083f; // round up, 24 bits, floating-point exc. disabled // cw = 0x0c3f; // round to zero, 24 bits, floating-point exc. disabled mov eax, DWORD PTR pcw fldcw [eax] for (i = 0 ; i < 11 ; i++) { x = (float)i; // x = 1.0, 2.0,..., 10.0 // compute y = sqrt (x) px = (char *)&x; py = (char *)&y; mov eax, DWORD PTR px fld DWORD PTR [eax] fsqrt mov eax, DWORD PTR py fstp DWORD PTR [eax] 01/12/06 22
23 z = y * y; printf ("x = %f = 0x%x\n", x, *(int *)&x); printf ("y = %f = 0x%x\n", y, *(int *)&y); printf ("z = %f = 0x%x\n", z, *(int *)&z); if (z == x) printf ("EQUAL\n\n"); else printf ("NOT EQUAL\n\n"); x x z x = x = x 4: 1 #include <stdio.h> void main () { float a, b, c; // single precision numbers (of size 4 bytes) unsigned int u; // unsigned integer (of size 4 bytes) char *pa, *pb, *pc; // pointers to single precision numbers unsigned short sw, *psw; // status word and pointer to it unsigned short cw, *pcw; // control word and pointer to it // will compute c = a * b psw = &sw; pcw = &cw; // clear and read status word, set control word cw = 0x033f; // round to nearest, 64 bits, fp exc.disabled // cw = 0x073f; // round down, 64 bits, fp exc.disabled // cw = 0x0b3f; // round up, 64 bits, fp exc.disabled // cw = 0x0f3f; // round to zero, 64 bits, fp exc. disabled fclex mov eax, DWORD PTR pcw fldcw [eax] mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE COMPUTATION sw = %4.4x\n", sw); pa = (char *)&a; u = 0x00fffffe; a = *(float *)&u; // a = * 2^-126 pb = (char *)&b; u = 0x3f000001; b = *(float *)&u; // b = * 2^-1 pc = (char *)&c; // compute c = a * b mov eax, DWORD PTR pa; fld DWORD PTR [eax]; // push a on the FPU stack mov eax, DWORD PTR pb; 01/12/06 23
24 fld DWORD PTR [eax]; // push b on the FPU stack fmulp st(1), st(0); // a * b in st(1), pop st(0) mov eax, DWORD PTR pc; fstp DWORD PTR [eax]; // c = a * b from FPU stack to memory, pop st(0) mov eax, DWORD PTR psw fstsw [eax] printf ("AFTER COMPUTATION sw = %4.4x\n", sw); printf ("c = %8.8x = %f\n", *(unsigned int *)&c, c); 1.0 * ( ) BEFORE COMPUTATION sw = 0000 AFTER COMPUTATION sw = 0220 c = = * ( ) BEFORE COMPUTATION sw = 0000 AFTER COMPUTATION sw = 0030 c = 007fffff = : FPU IEEE x87 IEEE [1] 2 IEEE IEEE FPU IEEE IEEE IEEE ( 8 15 ) ( FPU IEEE 24 ) FPU IEEE FPU d = (a * b) / c (a = 1.0 * b = 1.0 * c = 1.0 * ) a * b = 1.0 * IEEE FPU a * b = 1.0 * FPU ( 15 ) d = (a * b) / c = 1.0 * FPU 2 IEEE ( IEEE ) 01/12/06 24
25 ( ) FPU 64 fst ( 6 ) 53 FPU #include <stdio.h> void main () { float a, b, c, d; // single precision floating-point numbers unsigned int u; // unsigned integer (of size 4 bytes) char *pa, *pb, *pc, *pd; // pointers to single precision numbers unsigned short sw, *psw; // status word and pointer to it // will compute d = (a * b) / c psw = &sw; // clear and read status word; set rounding to nearest, // and 64-bit precision finit mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE COMP. sw = %4.4x\n", sw); pa = (char *)&a; u = 0x ; a = *(float *)&u; // a = 1.0 * 2^115 pb = (char *)&b; u = 0x7e000000; b = *(float *)&u; // b = 1.0 * 2^125 pc = (char *)&c; u = 0x7b800000; c = *(float *)&u; // c = 1.0 * 2^120 pd = (char *)&d; // compute d = (a * b) / c holding the intermediate result // a * b = 2^240 on the FPU stack mov eax, DWORD PTR pa; fld DWORD PTR [eax]; // push a on the FPU stack mov eax, DWORD PTR pb; fld DWORD PTR [eax]; // push b on the FPU stack fmulp st(1), st(0); // a * b = 2^240 in st(1), pop st(0) mov eax, DWORD PTR pc; fld DWORD PTR [eax]; // push c on the FPU stack fdivp st(1), st(0) // st(1) / st(0) = 2^120 in st(1), pop st(0) mov eax, DWORD PTR pd; fstp DWORD PTR [eax]; // d = 2^120 from FPU stack to mem., pop st(0) // read status word mov eax, DWORD PTR psw fstsw [eax] printf ("AFTER FIRST COMP. sw = %4.4x\n", sw); printf ("d = %8.8x = %f\n", *(unsigned int *)&d, d); // d = 2^120 // compute d = (a * b) / c saving the intermediate result // a * b = 2^240 to memory // round to nearest, 64-bit precision, floating-point exc. disabled 01/12/06 25
26 fclex mov eax, DWORD PTR pa; fld DWORD PTR [eax]; // push a on the FPU stack mov eax, DWORD PTR pb; fld DWORD PTR [eax]; // push b on the FPU stack fmulp st(1), st(0); // a * b = 2^240 in st(1), pop st(0) mov eax, DWORD PTR pd; fstp DWORD PTR [eax]; // d = a * b from the FPU stack to mem, pop st(0) fld DWORD PTR [eax]; // push d = +Inf from memory on the FPU stack mov eax, DWORD PTR pc; fld DWORD PTR [eax]; // push c on the FPU stack fdivp st(1), st(0) // st(1) / st(0) = +Inf in st(1), pop st(0) mov eax, DWORD PTR pd; fstp DWORD PTR [eax]; // d = +Inf from the FPU stack to mem, pop st(0) // read status word mov eax, DWORD PTR psw fstsw [eax] printf ("AFTER SECOND COMP. sw = %4.4x\n", sw); printf ("d = %8.8x = %f\n", *(unsigned int *)&d, d); 1 (FPU ) ( ) IEEE ( ) AFTER FIRST COMP. sw = 0000 d=7b800000= AFTER SECOND COMP. sw = 0028 d = 7f = 1.#INF00 6: R R rn53 rn64 64 ((R) rn64 ) rn53 = (R) rn53 R ( ) ( 64 ) ( 53 ) * ( 24 ) 2 1 ( 24 ) FPU ( 15 ) ( 24 8 ) ulp 01/12/06 26
27 2 FPU ( ) ( 24 8 ) #include <stdio.h> void main () { float a, b, c; // single precision floating-point numbers unsigned int u; // unsigned integer (of size 4 bytes) char *pa, *pb, *pc; // pointers to single precision numbers unsigned short sw, *psw; // status word and pointer to it unsigned short cw, *pcw; // control word and pointer to it // will compute c = a * b psw = &sw; pcw = &cw; // clear status flags, read status word, set control word cw = 0x003f; // round to nearest, 24 bits, fp exc. disabled fclex mov eax, DWORD PTR pcw fldcw [eax] mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE FIRST COMP. sw = %4.4x\n", sw); pa = (char *)&a; u = 0x ; a = *(float *)&u; // a = * 2^-126 pb = (char *)&b; u = 0x3f080000; b = *(float *)&u; // b = * 2^-1 pc = (char *)&c; c = 123.0; // initialize c to random value // compute c = a * b with 24 bits of precision; // result a * b with `unbounded' exponent on FPU stack mov eax, DWORD PTR pa fld DWORD PTR [eax] // push a on the FPU stack mov eax, DWORD PTR pb fld DWORD PTR [eax] // push b on the FPU stack fmulp st(1), st(0) // a * b in st(1), pop st(0) mov eax, DWORD PTR pc fstp DWORD PTR [eax] // c = a * b from FPU stack to memory, pop st(0) // read status word mov eax, DWORD PTR psw fstsw [eax] printf ("AFTER FIRST COMP. sw = %4.4x\n", sw); printf ("AFTER FIRST COMP. c = %8.8x = %f\n", *(unsigned int *)&c, c); // c = * 2^-126 // clear status flags, read status word, set control word cw = 0x023f; // round to nearest, 53 bits, fp exc. disabled 01/12/06 27
28 fclex mov eax, DWORD PTR pcw fldcw [eax] mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE SECOND COMP. sw = %4.4x\n", sw); // compute c = a * b with 53 bits of precision; // result a * b with `unbounded' exponent on FPU stack mov eax, DWORD PTR pa fld DWORD PTR [eax] // push a on the FPU stack mov eax, DWORD PTR pb fld DWORD PTR [eax] // push b on the FPU stack fmulp st(1), st(0) // a * b in st(1), pop st(0) mov eax, DWORD PTR pc fstp DWORD PTR [eax] // c = a * b from FPU stack to memory, pop st(0) // read status word mov eax, DWORD PTR psw fstsw [eax] printf ("AFTER SECOND COMP. sw = %4.4x\n", sw); printf ("AFTER SECOND COMP. c = %8.8x = %f\n", *(unsigned int *)&c, c); // c = * 2^-126 BEFORE FIRST COMP. sw = 0000 AFTER FIRST COMP. sw = 0030 AFTER FIRST COMP. c = = BEFORE SECOND COMP. sw = 0000 AFTER SECOND COMP. sw = 0230 AFTER SECOND COMP. c = = : (FDIVP 0.0 ) FSTP (FDIVP FWAIT ) try/ except _try except () ( ) EXCEPTION_EXECUTE_HANDLER except () ( [3] ) #include <stdio.h> #include <excpt.h> void main () { float f; unsigned short cw, *pcw; // control word and pointer to it pcw = &cw; 01/12/06 28
29 // clear status flags, set control word cw = 0x033b; // round to nearest, 64 bits, zero-divide exceptions enabled fclex mov eax, DWORD PTR pcw fldcw [eax] try { printf ("TRY BLOCK BEFORE DIVIDE BY 0\n"); fldpi // load in ST(0) fldz // load 0.0 in ST(0); in ST(1) fdivp st(1), st(0) // divide ST(1) by ST(0), result in ST(1), pop fstp f // store ST(0) in memory and pop stack top printf ("TRY BLOCK AFTER DIVIDE BY 0 \n"); except(exception_execute_handler) { printf ("EXCEPT BLOCK\n"); ( ) TRY BLOCK BEFORE DIVIDE BY 0 EXCEPT BLOCK FSTP TRY BLOCK BEFORE DIVIDE BY 0 TRY BLOCK AFTER DIVIDE BY 0 8: ( * ) include <stdio.h> #include <excpt.h> void main () { float a, b, c; // single precision floating-point numbers unsigned int u; // unsigned integer (of size 4 bytes) char *pa, *pb, *pc; // pointers to single precision numbers unsigned short t[5], *pt; unsigned short sw, *psw; // status word and pointer to it unsigned short cw, *pcw; // control word and pointer to it psw = &sw; pcw = &cw; // clear exception flags, read status word, // set control word cw = 0x0337; // round to nearest, 64 bits, // overflow exceptions enabled 01/12/06 29
30 fclex mov eax, DWORD PTR pcw fldcw [eax] mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE COMP. sw = %4.4x\n", sw); pa = (char *)&a; u = 0x ; a = *(float *)&u; // a = 1.0 * 2^115 pb = (char *)&b; u = 0x7e000000; b = *(float *)&u; // b = 1.0 * 2^125 pc = (char *)&c; c = 0.0; pt = t; try { printf ("TRY BLOCK BEFORE OVERFLOW\n"); // compute c = a * b mov eax, DWORD PTR pa fld DWORD PTR [eax] // push a on the FPU stack mov eax, DWORD PTR pb fld DWORD PTR [eax] // push b on the FPU stack fmulp st(1), st(0) // a * b in st(1), pop st(0) // cause the overflow exception mov eax, DWORD PTR pc fstp DWORD PTR [eax] // c = a * b from FPU stack to memory, pop st(0) fwait // trigger floating-point exception if any printf ("TRY BLOCK AFTER OVERFLOW\n"); except(exception_execute_handler) { printf ("EXCEPT BLOCK\n"); // clear exception flags, read status word, // set control word cw = 0x033f; // round to nearest, 64 bits, // exceptions disabled mov eax, DWORD PTR psw fnstsw [eax] fnclex mov eax, DWORD PTR pcw fldcw [eax] printf ("sw = %4.4x\n", sw); // sw=0xb888: B=1, TOP=111, ES=1, OE=1 mov eax, DWORD PTR pt fstp TBYTE PTR [eax] // c = a * b from FPU stack to memory, pop st(0) printf ("t = %4.4x%4.4x%4.4x%4.4x%4.4x\n", t[4],t[3],t[2],t[1],t[0]); // t = 2^240 01/12/06 30
31 FPU (sw=0xb888) ( B=1 TOP=111 ES=1 OE=1 ) (0x40ef ) FPU BEFORE COMP. sw = 0000 TRY BLOCK BEFORE OVERFLOW EXCEPT BLOCK sw = b888 t = 40ef FSTP FSTP FPU 32 9: FPU 2 FPU ( * ) #include <stdio.h> #include <float.h> #include <excpt.h> void main () { unsigned short a[5], b[5], c[5], *pa, *pb, *pc; unsigned short sw, *psw; // status word and pointer to it unsigned short cw, *pcw; // control word and pointer to it psw = &sw; pcw = &cw; // clear exception flags, read status word, // set control word cw = 0x0b37; // round up, 64 bits, overflow exc. enabled fclex mov eax, DWORD PTR pcw fldcw [eax] mov eax, DWORD PTR psw fstsw [eax] printf ("BEFORE COMP. sw = %4.4x\n", sw); // a = 1.0 * 2^16000, b = 1.0 * 2^16000 a[4] = 0x7e7f; a[3] = 0x8000; a[2] = 0x0000; a[1] = 0x0000; a[0] = 0x0001; b[4] = 0x7e7f; b[3] = 0x8000; b[2] = 0x0000; b[1] = 0x0000; b[0] = 0x0001; pa = a; pb = b; pc = c; try { printf ("TRY BLOCK BEFORE OVERFLOW\n"); // compute c = a * b mov eax, DWORD PTR pa fld TBYTE PTR [eax] // push a on the FPU stack mov eax, DWORD PTR pb fld TBYTE PTR [eax] // push b on the FPU stack fmulp st(1), st(0) // a * b in st(1), pop st(0) fwait // trigger floating-point exception if any 01/12/06 31
32 printf ("TRY BLOCK AFTER OVERFLOW\n"); except(exception_execute_handler) { printf ("EXCEPT BLOCK\n"); // clear exceptions, read status word, set control word cw = 0x0b3f; // round up, 64 bits, exceptions disabled mov eax, DWORD PTR psw fnstsw [eax] fnclex mov eax, DWORD PTR pcw fldcw [eax] printf ("sw = %4.4x\n", sw); // sw=0xbaa8: // B=1, TOP=111, C1=1, ES=1, PE=1, OE=1 mov eax, DWORD PTR pc fstp TBYTE PTR [eax] // c = a * b from FPU stack to memory, pop st(0) printf ("c = %4.4x%4.4x%4.4x%4.4x%4.4x\n", c[4],c[3],c[2],c[1],c[0]); // c = 2^32000 / 2^24576 = 2^7424 (biased exponent is 0x5cff) BEFORE COMP. sw = 0000 TRY BLOCK BEFORE OVERFLOW EXCEPT BLOCK sw = baa8 c = 5cff FPU (0x5cff = ) FPU (sw = baa8) B=1 TOP=111 C1=1 ES=1 PE=1 OE=1 (C1=1 ) FMUL /12/06 32
33 3 SIMD SIMD (SSE)( ) ( ) SIMD SSE 1 ( FPU ) 0 NaN 2D 3D 3.1 SIMD SSE ( 3) (FPU FXCH ) ( IA-32 ) XMM7 XMM6 XMM5 XMM4 XMM3 XMM2 XMM1 XMM0 3: SIMD SIMD 4 ( 4 X1 X2 X3 X4 X1 ) X4 X3 X2 X1 4: /12/06 33
34 16 SSE ( ) ( ) 4 ( ) 3 ( ) SIMD / SSE 32 / ( 5) 31 16( ) 6 0 FPU / SSE/ MMX SSE SSE2( 4 ) MMX FPU TOP=0 0( FPU ) FZ RC RC PM UM OM ZM DM IM Res PE UE OE ZE DE IE 5: / MXCSR / 5 0 SSE MXCSR (PC) 15 (MXCSR FZ ) 0 MXCSR SSE FZ (RC) IEEE [1] (RC=00B RC=01B RC=10B RC=11B ) (PM UM OM ZM DM IM) SIMD ( ) ( ) 01/12/06 34
35 5 0(PE UE OE ZE DE IE) 1 ( ) FPU MXCSR SSE 4 (OR) 10: SSE 2 IEEE 1 MULSS FPU 2 (FMUL FST) FPU FMUL 1 2 a b a = b = ( 24 ) a b = ( ) a b = ( ) a b = ( ) a b = ( ) ( 24 ) ( 0 ) a b = (P ) a b = +0.0 (P U ) a b = (P ) a b = +0.0 (P U ) 3.3 SIMD FPU ( ) 6 MXCSR / ( ) 01/12/06 35
36 ( ) ( ) ( ) SIMD FPU 1 MXCSR (OR) ( ) SIMD FPU SIMD 19 FPU SIMD COMISS UCOMISS( ) EFLAGS x87 (x87 ) SSE SIMD MXCSR (OR) ( ) SSE FPU ( ) SIMD FPU (SNaN NaN) QNaN ( QNaN ) ( ) MXCSR FPU FPU 01/12/06 36
37 FPU SSE 2 SIMD 3 SSE / FPU / 1 SIMD / 0 ( MXCSR FZ UM ) (PM 0 ( COMISS UCOMISS) EFLAGS ( ) EFLAGS 3.4 SSE FPU SSE MXCSR SSE MXCSR 4 x87 ( ) SIMD ( IEEE [1] ) 4 (1 2 ) ( ( ) 01/12/06 37
38 3.5 NaN FPU SIMD QNaN ( / ) ( 2 )FPU NaN 3 SSE QNaN 3: SSE QNaN SNaN QNaN 2 SNaN 2 QNaN QNaN 1 NaN( 1 SNaN QNaN ) 1 NaN(QNaN ) 1 NaN SNaN 1 SNaN QNaN( NaN) SNaN QNaN 1 QNaN QNaN NaN QNaN 3.6 SIMD SSE ( ) MMX 32 IA-32 ( [2] ) 4 PS ( packed single precision ) SS ( scalar single precision ) SSE 1. MOVAPS/MOVUPS: move aligned/unaligned packed single precision floating-point; SIMD SIMD 128 : MOVHPS/MOVLPS: move aligned, high/low packed single precision floating-point; SIMD / 64 ( / ) : 01/12/06 38
39 MOVHLPS/MOVLHPS: move high/low to low/high packed single precision floating-point; / 64 / 64 ( / 64 ) : MOVMSKPS: move mask packed, single precision floating-point to r32; 4 32 IA-32 r32 : MOVSS: move scalar single precision floating-point; SIMD 32 SIMD : 2. ADDPS/ADDSS/SUBPS/SUBSS/MULPS/MULSS: add/subtract/multiply packed/scalar, single precision floating-point; 1 SIMD 2 SIMD : I D O U P DIVPS/DIVSS: divide packed/scalar, single precision floating-point; 1 SIMD 2 SIMD : I Z D O U P SQRTPS/SQRTSS: square root packed/scalar, single precision floating-point; SIMD SIMD : I D P 3. MAXPS/MAXSS/MINPS/MINSS: maximum/minimum packed/scalar, single precision floatingpoint; 1 SIMD 2 SIMD : I D( NaN ) 4. CMPPS/CMPSS: compare packed/scalar, single precision floating-point; 1 SIMD 2 SIMD 1( ) 0( ) 32 : I D( lt le nlt nle NaN SNaN ) COMISS/UCOMISS: compare scalar single precision floating-point ordered/unordered and set EFLAGS; 1 SIMD 2 SIMD EFLAGS ZF PF CF : I D( COMISS NaN UCOMISS SNaN ) 01/12/06 39
40 5. CVTPI2PS: MMX 2 32 SIMD ( 2 )2 : P CVTSI2SS: 1 32 SIMD ( )1 : P CVTPS2PI/CVTTPS2PI: SIMD 2 2 MMX 2 32 CVTTPS2PI MXCSR ( ) : I P CVTSS2SI/CVTTSS2SI: SIMD 1 32 CVTTSS2SI MXCSR ( ) : I P 6. ( ) ANDPS/ANDNPS/ORPS/XORPS: packed logical AND, AND-NOT, OR, XOR; : 7. RCPPS/RCPSS: packed/scalar, single precision floating-point reciprocal approximation( ); SIMD SIMD : RSQRTPS/RSQRTSS: packed/scalar, single precision floating-point square root reciprocal approximation( ); SIMD SIMD : 8. FXSAVE/FXRSTOR: 512 FP/MMX SIMD / CS( ) IP( ) FOP( ) FTW(FPU ) FSW(FPU ) FCW(FPU ) MXCSR(SIMD / ) DS( ) DP( ) 8 FPU /MMX 8 SIMD : STMXCSR/LDMXCSR: 32 SIMD / / : 01/12/06 40
41 FXSAVE FXRSTOR FSAVE FRSTOR / SSE SIMD SIMD ( SIMD ) 32 SSE x87 MMX MMX SIMD 3.7 SSE SSE IA-32 ( 8086 ) SSE SSE : CR0.EM( 2) = 0 SSE : CPUID.XMM(EDX 25)=1 FXSAVE/FXRSTOR : CPUID.FXSR(EDX 24)=1 OS SIMD FP : CR4.OSFXSR( 9)=1 SIMD ( [2] ) SIMD SSE OS SIMD : CR4.OSXMMEXCPT( 10)= SSE 11: SSE SIMD (1.0, 1.0, 1.0, 1.0) ( , 0.0, , SNaN) ( ) 1 MXCSR ( ) MXCSR MXCSR SIMD (+inf, +inf, 0.0, QNaN) 1 01/12/06 41
42 SNaN NaN MXCSR MXCSR 1 #include <stdio.h> void main () { char *mem; unsigned int uimem[4]; int mxcsr, *pmxcsr; mem = (char *)uimem; // set and then read new value of MXCSR mxcsr = 0x00009f80; // ftz = 1, rc = 00 (to nearest), traps disabled, flags clear pmxcsr = &mxcsr; mov eax, DWORD PTR pmxcsr ldmxcsr [eax] stmxcsr [eax] printf ("BEFORE SIMD DIVIDE: MXCSR = 0x%8.8x\n", mxcsr); // load first set of operands uimem[0] = 0x3f800000; // 1.0 uimem[1] = 0x3f800000; // 1.0 uimem[2] = 0x3f800000; // 1.0 uimem[3] = 0x3f800000; // 1.0 mov eax, DWORD PTR mem; movups XMM1, [eax]; // load second set of operands uimem[0] = 0x ; // * 2^-126 uimem[1] = 0x ; // 0.0 uimem[2] = 0x7f7fffff; // * 2^127 uimem[3] = 0x7fbf0000; // SNaN mov eax, DWORD PTR mem; movups XMM2, [eax]; // perform SIMD divide and store result to memory divps XMM1, XMM2; mov eax, DWORD PTR mem; movups [eax], XMM1; // read new value of MXCSR mov eax, DWORD PTR pmxcsr stmxcsr [eax] printf ("AFTER SIMD DIVIDE: MXCSR = 0x%8.8x\n", mxcsr); printf ("res = %8.8x %8.8x %8.8x %8.8x = %f %f %f %f\n", 01/12/06 42
43 uimem[0], uimem[1], uimem[2], uimem[3], *(float *)&uimem[0], *(float *)&uimem[1], *(float *)&uimem[2], *(float *)&uimem[3]); The output is: BEFORE SIMD DIVIDE: MXCSR = 0x00009f80 AFTER SIMD DIVIDE: MXCSR = 0x00009fbf Res = 7f f fff0000 = 1.#INF00 1.#INF #QNAN0 MOVUPS SIMD SIMD 16 MOVAPS 16 12: SSE 1.0 / (sqrt (a) 1.0) / (sqrt (a) 1.0) a (a = = ) ( ) R = ( ) 2 24 a = XMM1 #include <stdio.h> void main () { char *mem; unsigned int *uimem; mem = (char *)(((int)malloc (144) + 16) & ~0x0f); // 16-byte aligned uimem = (unsigned int *)mem; // load x[i] in XMM1, i = 0,3 uimem[0] = 0x ; // 2.0 uimem[1] = 0x ; // 3.0 uimem[2] = 0x ; // 4.0 uimem[3] = 0x3f800001; // ulp ( ^-23) mov eax, DWORD PTR mem; movaps XMM1, [eax]; // load y[i] = 1.0 in XMM2, i = 0,3 uimem[0] = 0x3f800000; // 1.0 uimem[1] = 0x3f800000; // 1.0 uimem[2] = 0x3f800000; // 1.0 uimem[3] = 0x3f800000; // 1.0 mov eax, DWORD PTR mem; movaps XMM2, [eax]; // calculate 1.0 / (sqrt (x[i]) - 1.0), i = 0,3 // calculate sqrt (x[i]) in XMM1, i = 0,3 sqrtps XMM1, XMM1; // calculate sqrt (x[i]) in XMM1, i = 0,3 01/12/06 43
44 subps XMM1, XMM2; // calculate 1.0 / (sqrt (x[i]) - 1.0) in XMM2, i = 0,3 divps XMM2, XMM1; // store result in memory mov eax, DWORD PTR mem; movaps [eax], XMM2; printf ("res = %8.8x %8.8x %8.8x %8.8x = %f %f %f %f\n", uimem[0], uimem[1], uimem[2], uimem[3], *(float *)&uimem[0], *(float *)&uimem[1], *(float *)&uimem[2], *(float *)&uimem[3]); res = 401a827a 3faed9ec 3f f = #INF00 a = ( ) SSE2 01/12/06 44
45 4 SIMD SIMD (SSE2) IA MMX / SSE2 SSE2 MMX SSE SSE2 2 ( ) SIMD SSE2 1 ( FPU ) 0 NaN / FPU 4.1 SIMD SSE2 SSE ( 3) SIMD (XMM ) SSE2 / OS SSE / SIMD 2 ( 6 X1 X2 X1 ) X2 X1 6: SIMD / SSE / (MXCSR) SSE2 SSE2 MXCSR (PC) 1 ( ) SSE MXCSR SSE /12/06 45
46 2 (OR) SSE2 ( ) ( ) ( ) ( ) SSE2 FPU SSE ( ) 6 MXCSR / ( ) (MXCSR SSE ) ( ) ( ) ( ) SIMD FPU 1 MXCSR (OR) ( ) SIMD FPU SIMD 19 FPU SIMD COMISS UCOMISS( ) EFLAGS FPU (FPU ) SSE2 SIMD MXCSR (OR) ( ) SSE2 FPU ( ) SSE2 FPU SSE MXCSR SSE 01/12/06 46
47 FPU ( FPU ) FPU SSE2( ) 2 SIMD 3 / SSE2 FPU / SSE 1 SIMD / 0 ( MXCSR FZ UM ) (PM 0 ( COMISS UCOMISS) EFLAGS ( ) EFLAGS 4.4 SSE2 FPU SSE SSE2 MXCSR SSE2 SSE MXCSR 2 x87 ( ) SIMD ( IEEE [1] ) 2 ( ) ( ) 4.5 NaN FPU SSE SSE2 QNaN ( / ) SSE2 2 FPU QNaN 3 SSE NaN 01/12/06 47
48 4.6 SSE2 SSE2 ( ) MMX 32 IA-32 ( [2] ) PD ( packed double precision ) SD ( scalar double precision ) SSE2 1. MOVAPD/MOVUPD: move aligned/unaligned packed double precision floating-point; SIMD SIMD 128 : MOVHPD/MOVLPD: move aligned, high/low packed double precision floating-point; SIMD / 64 ( / ) : MOVMSKPD: move mask packed, double precision floating-point to r32; 2 32 IA-32 r32 : MOVSD: move scalar double precision floating-point; SIMD 64 SIMD : 2. ADDPD/ADDSD/SUBPD/SUBSD/MULPD/MULSD: add/subtract/multiply packed/scalar, double precision floating-point; 1 SIMD 2 SIMD : I, D, O, U, P DIVPD/DIVSD: divide packed/scalar, double precision floating-point; 1 SIMD 2 SIMD : I, Z, D, O, U, P SQRTPD/SQRTSD: square root packed/scalar, double precision floating-point; SIMD SIMD : I, D, P 01/12/06 48
49 3. MAXPD/MAXSD/MINPD/MINSD: maximum/minimum packed/scalar, double precision floating-point; 1 SIMD 2 SIMD : I, D( NaN ) 4. CMPPD/CMPSD: compare packed/scalar, double precision floating-point; 1 SIMD 2 SIMD 1( ) 0( ) 64 : I D( lt le nlt nle NaN SNaN ) COMISD/UCOMISD: compare scalar double precision floating-point ordered/unordered and set EFLAGS; 1 SIMD 2 SIMD EFLAGS ZF PF CF : I D( COMISD NaN UCOMISD SNaN ) 5. CVTPD2PI: MXCSR SIMD MMX 32 CVTSD2SI: MXCSR SIMD 1 32 IA CVTTPD2PI: SIMD MMX 32 CVTTSD2SI: SIMD 1 32 IA CVTPI2PD: MMX 2 32 SIMD 2 CVTSI2SD: 32 IA SIMD CVTPD2DQ/CVTTPD2DQ: SIMD 2 SIMD 2 32 CVTPD2DQ 01/12/06 49
50 MXCSR CVTTPD2DQ CVTDQ2PD: SIMD 2 32 SIMD 2 CVTPS2PD: SIMD 2 SIMD 2 CVTSS2SD: SIMD SIMD CVTPD2PS: SIMD 2 SIMD 2 CVTSD2SS: SIMD SIMD CVTPS2DQ/CVTTPS2DQ: SIMD 4 SIMD 4 32 CVTPS2DQ MXCSR CVTTPS2DQ CVTDQ2PS: SIMD 4 32 SIMD 4 6. ( ) ANDPD/ANDNPD/ORPD/XORPD: packed logical AND, AND-NOT, OR, XOR; : 7. SSE2 : SSE (FXSAVE, FXRSTOR, STMXCSR, LDMXCSR) SSE2 SIMD SIMD ( SIMD ) 64 SSE 4.7 SSE2 SSE2 IA-32 ( 8086 ) SSE2 SSE2 : CR0.EM( 2) = 0 SSE2 : CPUID.WNI=1 FXSAVE/FXRSTOR : CPUID.FXSR(EDX 24)=1 01/12/06 50
51 OS SIMD FP : CR4.OSFXSR( 9)=1 SIMD ( [2] ) SIMD SSE2 OS SIMD : CR4.OSXMMEXCPT( 10)= : SSE2 1.0 / (sqrt (a) 1.0) 12 SSE 1.0 / (sqrt (a) 1.0) a (a = = ) R = ( ) 2 24 a = XMM1 #include <stdio.h> void main () { char *mem; unsigned int *uimem; mem = (char *)(((int)malloc (144) + 16) & ~0x0f); // 16-byte aligned // printf ("mem = %x\n\n", (int)mem); uimem = (unsigned int *)mem; // load x[i] in XMM1, i = 0,1 uimem[1] = 0x ; uimem[0] = 0x ; // 2.0 (in uimem[1], uimem[0]) uimem[3] = 0x3ff00000; uimem[2] = 0x ; // ^-23 (in uimem[3], uimem[2]) mov eax, DWORD PTR mem; movaps XMM1, [eax]; // load y[i] = 1.0 in XMM2, i = 0,1 uimem[1] = 0x3ff00000; uimem[0] = 0x ; // 1.0 uimem[3] = 0x3ff00000; uimem[2] = 0x ; // 1.0 mov eax, DWORD PTR mem; movaps XMM2, [eax]; // calculate 1.0 / (sqrt (x[i]) - 1.0), i = 0,1 // calculate sqrt (x[i]) in XMM1, i = 0,1 sqrtpd XMM1, XMM1; // calculate sqrt (x[i]) in XMM1, i = 0,1 subpd XMM1, XMM2; // calculate 1.0 / (sqrt (x[i]) - 1.0) in XMM2, i = 0,1 divpd XMM2, XMM1; 01/12/06 51
52 // store result in memory mov eax, DWORD PTR mem; movaps [eax], XMM2; printf ("res = %8.8x%8.8x %8.8x%8.8x = %f %f\n", uimem[1], uimem[0], uimem[3], uimem[2], *(double *)&uimem[0], *(double *)&uimem[2]); res = f333f9de = (uimem[3] uimem[2] )a = R R* = ( ) 2 24 ε = (R R*) / R = ( ) / ( ) ( 12 ) ( ) 1.6 (ε ) 01/12/06 52
53 5 4 IA-32 FPU SSE SSE2 4: IA-32 FPU SSE SSE2 FPU SSE SSE2 FPU SSE OS SSE2 OS FPU OS SSE OS SSE2 OS OS 4 SIMD 2 SIMD : : : IA-32 IA-32 ( ) (SSE2 (SSE ) ) / / / FPU / / MXCSR(SSE2 ) MXCSR(SSE ) 01/12/06 53
54 4: IA-32 FPU SSE SSE2 ( ) FPU SSE SSE2 4 2 (OR) (OR) / / (I D Z) (I D Z) (I D Z) (O U P) (O U P) (O U P) ( ) 01/12/06 54
55 4: IA-32 FPU SSE SSE2 ( ) FPU SSE SSE2 FPU IEEE % IEEE IEEE % % ( (IEEE 754 ) ) (IEEE 754 ) FPU ( SSE SSE2 SSE2 SSE )SSE SSE2 NaN ( NaN ( NaN )FPU )FPU FPU SSE SSE2 14: FPU SSE SSE2 ( ) (((1 / ((1 / 10) / (1 / 3)) + 3 / 10) / 11) * (1 / (1 / 99) + 11)) * 39 = 1417 SSE ( 4 ) #include <stdio.h> void main () { float res[4], *pres = res, a1[4] = {1.0, 1.0, 1.0, 1.0, *pa1 = a1, a3[4] = {3.0, 3.0, 3.0, 3.0, *pa3 = a3, a10[4] = {10.0, 10.0, 10.0, 10.0, *pa10 = a10, a11[4] = {11.0, 11.0, 11.0, 11.0, *pa11 = a11, a39[4] = {39.0, 39.0, 39.0, 39.0, *pa39 = a39, a99[4] = {99.0, 99.0, 99.0, 99.0, *pa99 = a99; mov eax, DWORD PTR pa1 movups XMM5, [eax] // 1 in xmm5 01/12/06 55
56 movaps XMM1, XMM5 // 1 in xmm1 mov eax, DWORD PTR pa10 movups XMM2, [eax] // 10 in xmm2 divps XMM1, XMM2 // 1/10 in xmm1 movaps XMM2, XMM5 // 1 in xmm2 mov eax, DWORD PTR pa3 movups XMM3, [eax] // 3 in xmm3 divps XMM2, XMM3 // 1/3 in xmm2 divps XMM1, XMM2 // 3/10 in xmm1 movaps XMM2, XMM5 // 1 in xmm2 divps XMM2, XMM1 // 10/3 in xmm2 mov eax, DWORD PTR pa10 movups XMM1, [eax] // 10 in xmm1 divps XMM3, XMM1 // 3/10 in xmm3 addps XMM2, XMM3 // 109/30 in xmm2 mov eax, DWORD PTR pa11 movups XMM1, [eax] // 11 in xmm1 divps XMM2, XMM1 // 109/330 in xmm2 mov eax, DWORD PTR pa99 movups XMM3, [eax] // 99 in xmm3 movups XMM4, XMM5 // 1 in xmm4 divps XMM4, XMM3 // 1/99 in xmm4 divps XMM5, XMM4 // 99 in xmm5 addps XMM1, XMM5 // 110 in xmm1 mulps XMM1, XMM2 // 109/3 in xmm1 mov eax, DWORD PTR pa39 movups XMM2, [eax] // 39 in xmm2 mulps XMM1, XMM2 // 1417 in xmm1 mov eax, DWORD PTR pres; movups [eax], XMM1; printf ("res = \n\t%8.8x %8.8x %8.8x %8.8x = \n\t%f %f %f %f\n", *(unsigned int *)&res[0], *(unsigned int *)&res[1], *(unsigned int *)&res[2], *(unsigned int *)&res[3], res[0], res[1], res[2], res[3]); IEEE res = 44b b b b12001 = ulp res = ulp = = e = ε 1 = FPU 24 FPU IEEE SSE2 ( ) ( 2 ) 01/12/06 56
57 #include <stdio.h> void main () { double res[2], *pres = res, a1[2] = {1.0, 1.0, *pa1 = a1, a3[2] = {3.0, 3.0, *pa3 = a3, a10[2] = {10.0, 10.0, *pa10 = a10, a11[2] = {11.0, 11.0, *pa11 = a11, a39[2] = {39.0, 39.0, *pa39 = a39, a99[2] = {99.0, 99.0, *pa99 = a99; unsigned int *uint; uint = (unsigned int *)res; mov eax, DWORD PTR pa1 movupd XMM5, [eax] // 1 in xmm5 movapd XMM1, XMM5 // 1 in xmm1 mov eax, DWORD PTR pa10 movupd XMM2, [eax] // 10 in xmm2 divpd XMM1, XMM2 // 1/10 in xmm1 movapd XMM2, XMM5 // 1 in xmm2 mov eax, DWORD PTR pa3 movupd XMM3, [eax] // 3 in xmm3 divpd XMM2, XMM3 // 1/3 in xmm2 divpd XMM1, XMM2 // 3/10 in xmm1 movapd XMM2, XMM5 // 1 in xmm2 divpd XMM2, XMM1 // 10/3 in xmm2 mov eax, DWORD PTR pa10 movupd XMM1, [eax] // 10 in xmm1 divpd XMM3, XMM1 // 3/10 in xmm3 addpd XMM2, XMM3 // 109/30 in xmm2 mov eax, DWORD PTR pa11 movupd XMM1, [eax] // 11 in xmm1 divpd XMM2, XMM1 // 109/330 in xmm2 mov eax, DWORD PTR pa99 movupd XMM3, [eax] // 99 in xmm3 movupd XMM4, XMM5 // 1 in xmm4 divpd XMM4, XMM3 // 1/99 in xmm4 divpd XMM5, XMM4 // 99 in xmm5 addpd XMM1, XMM5 // 110 in xmm1 mulpd XMM1, XMM2 // 109/3 in xmm1 mov eax, DWORD PTR pa39 movupd XMM2, [eax] // 39 in xmm2 mulpd XMM1, XMM2 // 1417 in xmm1 mov eax, DWORD PTR pres; movupd [eax], XMM1; printf ("res = \n\t%8.8x%8.8x %8.8x%8.8x = \n\t%f %f\n", uint[3], uint[2], uint[1], uint[0], res[1], res[0]); IEEE res = fffffffffe fffffffffe = /12/06 57
58 1417 2ulp res = ulp = = e = ε 2 = (ε 1 = ) FPU 53 FPU IEEE FPU (FPU PC=11 ) #include <stdio.h> void main () { float a3 = 3., a10 = 10., a11 = 11., a39 = 39., a99 = 99.; char *pa3, *pa10, *pa11, *pa39, *pa99; // pointers to single precision numbers unsigned short t[5], *pt; // 10-byte (80-bit) result unsigned short cw, *pcw; // control word and pointer to it float res; // result, used just to print the decimal value char *pres; pa3 = (char *)&a3; pa10 = (char *)&a10; pa11 = (char *)&a11; pa39 = (char *)&a39; pa99 = (char *)&a99; pt = t; pres = (char *)&res; pcw = &cw; // set control word cw = 0x033f; // round to nearest, 64 bits, exceptions disabled // (double-extended precision) // cw = 0x023f; // (use for pure IEEE double precision) // round to nearest, 53 bits, exceptions disabled // cw = 0x003f; // (use for pure IEEE single precision) // round to nearest, 24 bits, exceptions disabled mov eax, DWORD PTR pcw fldcw [eax] // compute E = fld1 // 1 in st(0) mov eax, DWORD PTR pa10 fdiv DWORD PTR [eax] // 1/10 in st(0) fld1 // 1 in st(0), 1/10 in st(1) mov eax, DWORD PTR pa3 fdiv DWORD PTR [eax] // 1/3 in st(0), 1/10 in st(1) fdivp st(1), st(0) // 3/10 in st(0) fld1 // 1 in st(0), 3/10 in st(1) fxch // 3/10 in st(0), 1 in st(1) 01/12/06 58
59 fdivp st(1), st(0) // 10/3 in st(0) mov eax, DWORD PTR pa3 fld DWORD PTR [eax] // 3 in st(0), 10/3 in st(1) mov eax, DWORD PTR pa10 fdiv DWORD PTR [eax] // 3/10 in st(0), 10/3 in st(1) faddp st(1), st(0) // 109/30 in st(0) mov eax, DWORD PTR pa11 fdiv DWORD PTR [eax] // 109/330 in st(0) fld1 // 1 in st(0), 109/330 in st(1) mov eax, DWORD PTR pa99 fdiv DWORD PTR [eax] // 1/99 in st(0), 109/330 in st(1) fld1 // 1 in st(0), 1/99 in st(1), 109/330 in st(2) fxch // 1/99 in st(0), 1 in st(1), 109/330 in st(2) fdivp st(1), st(0) // 99 in st(0), 109/330 in st(1) mov eax, DWORD PTR pa11 fadd DWORD PTR [eax] // 110 in st(0), 109/330 in st(1) fmulp st(1), st(0) // 109/3 in st(0) mov eax, DWORD PTR pa39 fmul DWORD PTR [eax] // 1417 in st(0) mov eax, DWORD PTR pres fst DWORD PTR [eax] // res from the FPU stack to memory, pop st(0) mov eax, DWORD PTR pt fstp TBYTE PTR [eax] // res from the FPU stack to memory, pop st(0) printf ("res = %4.4x%4.4x%4.4x%4.4x%4.4x\n", t[4], t[3], t[2], t[1], t[0]); // t = printf ("res = %6.6f\n", res); IEEE res = 4009b res = ulp res = ulp = = e = ε 3 = ε 1 = > ε 2 = > ε 3 = /12/06 59
60 6 FPU BCD ( ) SIMD SSE SSE2 IA-32 FPU SSE SSE2 IEEE IEEE ( SSE SSE2 ) IA-32 IEEE 1 01/12/06 60
AxC_lj.fm
IA-32 IA-32 Intel Pentium 4 Intel NetBurst 1 2 /SIMD IA-32 Pentium 4 ( OP) IA-32 IA-32 ( OP) 1 I/O 2 xchg ( OP) 5 ( OP) IA-32 ROM ( OP) ROM ROM ( OP) ( OP) 4 1 32 ROM 16 PADDQ PMULUDQ 2 1 1 1 2 2 2 1 http://www.intel.co.jp/jp/developer/vtune/
64bit SSE2 SSE2 FPU Visual C++ 64bit Inline Assembler 4 FPU SSE2 4.1 FPU Control Word FPU 16bit R R R IC RC(2) PC(2) R R PM UM OM ZM DM IM R: reserved
(Version: 2013/5/16) Intel CPU ([email protected]) 1 Intel CPU( AMD CPU) 64bit SIMD Inline Assemler Windows Visual C++ Linux gcc 2 FPU SSE2 Intel CPU double 8087 FPU (floating point number processing unit)
64bit SSE2 SSE2 FPU Visual C++ 64bit Inline Assembler 4 FPU SSE2 4.1 FPU Control Word FPU 16bit R R R IC RC(2) PC(2) R R PM UM OM ZM DM IM R: reserved
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