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ありさむらかわ
7 years ago
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2 (1/2) LSISoC: (1) (*) (*) GPU SIMD MIMD FPGA DES, AES

3 (2/2) (2) FPGA(8bit) (ISS: Instruction Set Simulator) (3) (4) LSI

4 ECU110100ECU1 ECU ECU ECU ECU FPGA ECU main() { int i, j, k for { } 1

5 GP-GPU A Parallel Logic Simulation Method using GP-GPU ~ ~ GPU GPU main(){ MemoryCopy(HostToDevice) kernel<<<blocks,threads>>> MemoryCopy(DeviceToHost) } GPU CPUHost GPUSM SM STEP1 6 7 L M N STEP CG1 CG2 CG3 3 GPUDevice SM SM 2 nsm GPU 2 STEP L M N SM1 SM2 SM3 GPU ModelSim GPU Geforce GTX480 PC Intel Core i GHz 100,000 - SEQSim - GPUSim - ModelSim SE 6.2e 3. SEQSim GPUSim5.1 GPUSim-M bit processor GPU* *Geforce TITAN cpu x cpu x cpu x sim

Research of Acceleration Method for Logic Simulation based on Parallel Algorithm () C SpecC Basic block JAXA - Elegant / Visual Spec 3 5 4 2 6 1 SpecC 4 ( ) () (1) ()(2) 1. 2. ModelSim - :Elegant/Visual Spec(ver4.

6 Research of Acceleration Method for Logic Simulation based on Parallel Algorithm () C SpecC Basic block JAXA - Elegant / Visual Spec SpecC 4 ( ) () (1) ()(2) ModelSim - :Elegant/Visual Spec(ver4.1.6) - :ARM946E-S(200MHz) * - ModelSim SE 6.2e() - PCIntel Core i GHz 10, sim vs sim(8) sim 8sim cpu x810.4 sim(8) vs sim sim cpu x84.6 (3210) (2) ANDOR

7 FPGA A Logic Simulation Method using FPGA ~ ~ FPGA FPGA ( ) 1. SIM Onchip SRAM Offchip RAM FPGA ModelSim FPGA50MHz 10,000 ModelSim SE 6.2e( PC Intel Core i GHz (FPGA_SIM256) (FPGA_SIM1) cpu x (FPGA_SIM256) cpu x BRAMFPGA offchipram 2~ LSI10

8 FPGA A Proposal of FPGA Microcontroller FPGA FPGA FPGA PC GUI FPGA PCFPGA FPGA110 FPGA2 2. PCFPGA PCFPGA2 FPGAPC FPGA 1. FPGA 8 : RS232C : LSI FPGA control-line : RAM(ISS) ISSFPGA Debug : PC 8 RAM/ MEM : debug_out : PC LED_out: 7SEGLED 3. GUI FPGA40MHz 5760!! FPGA 57601!! 1.ISS 2.FPGA 3.ISSFPGA

9 Compact Logic Optimization Method for Partial Logic Circuits GPU 1. ()

10 FPGA High Speed Encryption Unit based on FPGA for Mobile Terminal ~ ~ AES FPGA AES 128bit 41 PC RS232C 通信モジュール 1 PC BRAM FPGA AES 暗号化ユニット RS232C FPGA AES BRAM CLK 128bit AES Key data In data mc0 mc1 mc2 mc3 Add RoundKey Key Expansion mc00 mc01 mc02 mc03 mc10 mc11 mc12 mc13 mc20 mc21 mc22 mc23 mc30 mc31 mc32 mc33 Sub Bytes 2.AES GF2 GF3 GF1 GF1 GF1 GF2 GF3 GF1 GF1 GF1 GF2 GF3 GF3 GF1 GF1 GF2 3.MixColumns 2.4MB SpecC ARM9200MH 11.2sec ModelSim 100MHAES 0.19sec FPGA XOR XOR XOR XOR 4MixColumns GF Shift Rows Mix Columns 128bit 59 out

11 Proposal of Alert System using Medical Data Analysis DWH DWH ( ) : 1. DWH Y 1x1 2x2 nx n, n Y: () xn: 01 1 Y 1 e 1 ( 1 x 1 2 x 2 n x n ), n Y: xn: IF-THEN YES A 1 NO B NO 2 2. YES C 1 X1 X2 B2 X1 2 X2 B2A B1 S1 A B1 S2 1,2 : A, B, C : XML A X1 B1 = B1X1 X2 B2 = B2X2 A B1X1 B2X2 Y 1x1 2x2 S1 3. DWH Y n x n

GP-GPU Evaluation of parallel logic simulation performance using GP-GPU GP-GPU GPU 8 Graphics Processing Unit GPU GTX 480 GP-GPUGeneral Purpose GPU GPU GPU SM /SM SM

12 GP-GPU Evaluation of parallel logic simulation performance using GP-GPU GP-GPU GPU 8 Graphics Processing Unit GPU GTX 480 GP-GPUGeneral Purpose GPU GPU GPU SM /SM SM GTX780, GPU 100,000 ModelSim SE 6.2e( PC Intel Core i GHz 2. Adder4 x 640GPU 10 Ldpc_enGT540MQuadro600 7GTX480, ,000 GPU GP-GPU ModelSim GTX780 GTX480

13 NTT NTT NEC

FIT2013( 第 12 回情報科学技術フォーラム ) I-032 Acceleration of Adaptive Bilateral Filter base on Spatial Decomposition and Symmetry of Weights 1. Taiki Makishi Ch

FIT2013( 第 12 回情報科学技術フォーラム ) I-032 Acceleration of Adaptive Bilateral Filter base on Spatial Decomposition and Symmetry of Weights 1. Taiki Makishi Ch I-032 Acceleration of Adaptive Bilateral Filter base on Spatial Decomposition and Symmetry of Weights 1. Taiki Makishi Chikatoshi Yamada Shuichi Ichikawa Gaussian Filter GF GF Bilateral Filter BF CG [1]