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1 SEE SEUSingle Event Upset SELSingle Event Latchup 245 J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
2 SEBSingle Event Burnout J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
3 2.3SER N N SER FCS Q F A crit Kexp Q s F K CS A Q Q 247 J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
4 J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
5 WN 249 J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
6 4.3 SER 68 J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
7 5 1 ComputerWorld, p. 12, Dec. 3, In-flight upset, 154 km west of learmonth, WA, 7 October 2008, VH-QPA Airbus A ,ATSB Transp. Safety Report - Aviation Occurrence Investig., no. AO , pp , Dec K. Shimbo, T. Toba, K. Nishii, E. Ibe, Y. Taniguchi, and Y. Yahagi, Quantification & mitigation techniques of soft-error rates in routers validated in accelerated neutron irradiation test and field test, SELSE, J. Warnock, et. al., 22nm next-generation IBM system z microprocessor,in ISSCC, Feb. 2015, pp R. Kan, T. Tanaka, G. Sugizaki, R. Nishiyama, S. Sakabayashi, Y. Koyanagi, R. Iwatsuki, K. Hayasaka, T. Uemura, G. Ito, Y. Ozeki, H. Adachi, K. Furuya, and T. Motokurumada, A 10th generation 16-core sparc64 processor for mission-critical unix server, in ISSCC, 2013, pp , SRAM MOSFET, Technical report of IEICE. ICD, vol. 103, no. 2, pp , J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
8 SRAM,Technical report of IEICE. ICD, vol. 105, no. 2, pp , ,no. 903, pp , P. Hazucha, C. Svensson, and S. Wender, Cosmic- Ray Soft Error Rate Characterization of a Standard 0.6-m CMOS Process,IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp , P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic,in ICDSN, 2002, pp P. Hazucha and C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate,ieee Trans. Nucl. Sci., vol. 47, no. 6, pp , M. Hifumi, E. Sonezaki, J. Furuta, and K. Kobayashi, Radiation hardness evaluations of ffs on 28nm and 65nm thin BOX FD-SOI processes by heavy-ion irradiation,in RASEDA, Nov. 2015, pp J. Furuta, J. Yamaguchi, and K. Kobayashi, A radiation-hardened non-redundant flip-flop, stacked leveling critical charge flip-flop in a 65 nm thin BOX FD-SOI process,ieee Trans. Nucl. Sci., vol. 63, no. 4, pp , Aug A. Makihara, T. Yamaguchi, Y. Tsuchiya, T. Arimitsu, H. Asai, Y. Iide, H. Shindou, S. Kuboyama, and S. Matsuda, SEE in a 0.15 m fully depleted CMOS/ SOI commercial process,ieee Trans. Nucl. Sci., vol. 51, no. 6, pp , J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera, A 65nm bistable cross-coupled dual modular redundancy flip-flop capable of protecting soft errors on the C-element,in VLSI Circuit Symp., June 2010, pp C. Hamanaka, R. Yamamoto, J. Furuta, K. Kubota, K. Kobayashi, and H. Onodera, Variation-tolerance of a 65-nm error-hardened dual-modular-redundancy flip-flop measured by shift-register-based monitor structures,ieice Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp , Dec R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera, An area-effcient 65 nm radiationhard dual-modular flip-flop to avoid multiple cell upsets,ieee Trans. Nucl. Sci., vol. 58, no. 6, pp , Dec C. Takahashi, S. Shibahara, K. Fukuoka, J. Matsushima, Y. Kitaji, Y. Shimazaki, H. Hara, and T. Irita, A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10 7 random hardware failures per hour reliability,in ISSCC, Jan. 2016, pp M. Miyamura, S. Nakaya, M. Tada, T. Sakamoto, K. Okamoto, N. Banno, S. Ishida, K. Ito, H. Hada, N. Sakimura, T. Sugibayashi, and M. Motomura, Programmable cell array using rewritable solidelectrolyte switch integrated in 90nm CMOS,in ISSCC, Feb. 2011, pp T. Uemura, Y. Tosaka, H. Matsuyama, K. Shono, C. Uchibori, K. Takahisa, M. Fukuda, and K. Hatanaka, SEILA: Soft error immune latch for mitigating multi-node-seu and local-clock-set,in IRPS, May 2010, pp H. Asai, K. Sugimoto, I. Nashiyama, Y. Iide, K. Shiba, M. Matsuda, and Y. Miyazaki, Terrestrial neutroninduced single-event burnout in SiC power diodes, IEEE Trans. Nucl. Sci., vol. 59, no. 4, pp , Aug N. Kanekawa, E. H. Ibe, T. Suga, and Y. Uematsu, Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances, Springer Science & Business Media, Y. Tosaka, R. Takasu, T. Uemura, H. Ehara, H. Matsuyama, S. Satoh, A. Kawai, and M. Hayashi, Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of mauna kea,in IRPS, May 2008, pp L. F. Kastensmidt, L. Carro, and R. Reis, Fault- Tolerance Techniques for SRAM-Based FPGAs, Springer, K. Zhang, S. Umehara, J. Yamaguchi, J. Furuta, and K. Kobayashi, Analysis of soft error rates in 65- and 28-nm FD-SOI processes depending on BOX region thickness and body bias by Monte-Carlo based simulations,ieee Trans. Nucl. Sci., vol. 63, no. 4, pp , Aug J. Particle Accelerator Society of Japan, Vol. 13, No. 4,
DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 Gate Gate Source n Drain n Source n BOX Drain n 2 SOI 2 3 TCAD 4 PHITSTCAD (LSI)
DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 28nm UTBB FDSOI SOI 28nm UTBB FDSOI Analysis of Soft Error Rates in a 28nm UTBB FDSOI Structure by DeviceLevel Simulation Shigehiro Umehara
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CREST ディペンダブル VLSI システムの基盤技術 領域会議 2011 年 7 月 1,2 日科学技術振興機構 CMOS テ ハ イスの中性子起因ソフトエラーの定量化と対策技術開発戦略ー過去から未来へー IRPS2011での招待講演 IRPS 2011レポート 中性子線がボードのCPUやメモリなどを誤動作させる仕組み で紹介 [http://pc.watch.impress.co.jp/docs/news/event/20110505_443999.html
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