Vol. 45 No. SIG 3(ACS 5) Mar. 2004 Responsive Link, FA OA Responsive Link Responsive Link Hot-Plug&Play Responsive Link Responsive Processor Responsive Multithreaded Processor IPSJ-TS 0006:2003 ISO/IEC SC25 WG4 Design and Implementation of Real-time Communication Responsive Link for Distributed Control Nobuyuki Yamasaki, In this paper, we design and implement Responsive Link for distributed real-time control, which can be applied to various electronic control systems including robot systems, mechatronic systems, home automation, office automation, factory automation, etc. In order to realize flexible real-time communications, Responsive Link has many unique features including separation of data transmission for soft real-time (data link) and event transmission for hard real-time (event link), independent routing of the data link and the event link, priority based packet overtaking (the packet with higher priority overtakes other packets at each node.), packet acceleration/deceleration using priority replacement (packet priority can be replaced with a new priority level at each node to accelerate/decelerate packets under distributed control.), prioritized routing (when multiple packets with different priority levels are sent to the same destination, the different route can be set to realize exclusive communication lines or detours.), dynamically variable link speed (800, 400, 200, 100, 50, 25, 12.5 [Mbaud]), hot-plug&play, topology free, etc. Responsive Link is implemented on Responsive Processor and RMT Processor for distributed control. Responsive Link has been standardized as IPSJ- TS 0006:2003 in Japan. Responsive Link is also under standardisation at ISO/IEC JTC1 SC25 WG4. 1. Keio University Presently with an associate researcher of National Institute of Advanced Industrial Science and Technology Responsive Link Responsive Link 1) 50
Vol. 45 No. SIG 3(ACS 5) Responsive Link 51 Responsive Link Responsive Link WG6 2) IPSJ-TS 0006:2003 ISO/IEC JTC1 SC25 WG4 3) 2. 2.1 2 2.1.1 0 100 [µsec] 10 [msec] 2.1.2 0 1 EDF Fig. 1 EDF scheduling. MPEG 10 [msec] 1 [sec] Responsive Link 2.2 EDF Earliest Deadline First RM Rate Monotonic 1 EDF
52 Mar. 2004 4),5) Responsive Link 2.3 Ethernet ATM Fibre Channel IEEE-1394 USB2.0 Ethernet CSMA/CD ATM IEEE1394 AV I/O 63 Plug&Play USB2.0 I/O PC I/O 127 PC IEEE1394 3. Responsive Link 3.1 1 1
Vol. 45 No. SIG 3(ACS 5) Responsive Link 53 2 Responsive Link Fig. 2 Responsive Link interface. point-to-point 2 3.2 3 Responsive Link 16 8 64 56 1 3 4 Rate Monotonic Scheduling 3 Responsive Link Fig. 3 Packet format of Responsive Link. 4 Responsive Link Fig. 4 Header format of Responsive Link. 256 6) Responsive Link 256 8bit 0 Responsive Link 2 32 4 Responsive Link 12 bit 12 bit 8 bit 2 12 = 4096 4096 24 bit 8 bit 2 24 =16M 3.3
54 Mar. 2004 5 Responsive Link Fig. 5 Network switch of Responsive Link. 7) 5 5 5 1 4 5 In0 4 Out0 4 3.4 4.1 5 8 bit byte 6 5 1 6 In In-Pointer 0 3 7 6 L0 L4 L2 2
Vol. 45 No. SIG 3(ACS 5) Responsive Link 55 6 Fig. 6 Responsive Link Overtaking buffer of Responsive Link. 7 Responsive Link Fig. 7 Routing table of Responsive Link. 6 L0 L4 Out0 Out4 5 Priority ArbitorN 6 PriorityN 5 Priority ArbitorN 1 In-pointer 1 In 1 L1 L3 Out-pointer1 Out-pointer3 1 Out1 Out3 Priority1 Priority3 Out3 Priority Arbitor3
56 Mar. 2004 1 Out3 Out3 1 L3 Out1 Priorty1 Out1 Out1 2 Out-pointer1 2 Priority1 Out1 Out-pointer1 1 1 6 1 SDRAM sdram-in-flagn 2 sdram-out-flagn / 6 sdramout-pointer SDRAM sdramin-pointer Responsive Link SDRAM 3.4 Responsive Link 7 Responsive Link 7 Reference Referent EE DE L[4-0] Responsive Link TLB MMU
Vol. 45 No. SIG 3(ACS 5) Responsive Link 57 Responsive Link RT-OS Responsive Link LRU RT-OS 3.5 7) 7 7 7 PE PE Priority[7-0] P7 P0 3.6 8) 0 (1) 1 (2) 0 0 8 2 0 3 3 Re-
58 Mar. 2004 3.7 Responsive Link CRC 8 Responsive Link Fig. 8 Prioritized routing of Responsive Link. 9 Responsive Link Fig. 9 Prioritized tree routing of Responsive Link. sponsive Link 9 9 0 5 0 1 2 1 0 5 1 3 1 8 bit 4 bit 1 bit 3.7.1 CODEC Responsive Link CODEC 8 bit 4 bit 12 bit 1 CODEC (1) ( 2 ) Bit Stuffing 1 0 ( 3 ) NRZI 9) 3.7.2 x 4 + x +1 8 bit LSB 4 bit 12 bit 1 bit 1 12 bit MSB 1 bit 3.7.3 Bit Stuffing 1 5 1 0
Vol. 45 No. SIG 3(ACS 5) Responsive Link 59 1 2 Table 1 Syndrome and error position. Table 2 Communication speed vs. cable. Syndrome Error Position (4 Meaning redundancy bits) 0000 00000000 0000 No error 0001 00000000 0001 Redundancy-bit error 0010 00000000 0010 Redundancy-bit error 0100 00000000 0100 Redundancy-bit error 1000 00000000 1000 Redundancy-bit error 0011 00000001 0000 0bit error 0110 00000010 0000 1bit error 1100 00000100 0000 2bit error 1011 00001000 0000 3bit error 0101 00010000 0000 4bit error 1010 00100000 0000 5bit error 0111 01000000 0000 6bit error 1110 10000000 0000 7bit error 3.7.4 NRZI NRZI Non Return to Zero InvertedNRZI 0 1 3.7.5 000001111110 1 6 bit stuffing 1 3.7.6 DPLL DPLL Digital Phase Lock Loop 1 bit 4 8 16 32 64 128 256 DPLL 3.7.7 Responsive Link 1 [bit/frame] Speed (Mbaud) 100 200 400 800 Maximum Length (m) 100 80 60 40 Recommendable Cable Cat5e Cat5e Cat6 Cat6 3 Dirty 4 byte Dirty Dirty 1 Correct Fatal 3.7.8 Responsive Link 800 400 200 100 50 12.5 6.25 [Mbaud] 2 800 [Mbaud] Category6 40 [m] DPLL 3.2 [GHz] 1 1 1.6 [GHz] 2 4 DPLL DPLL DPLL 2 4. Responsive Link Responsive Processor 1) Responsive MultiThreaded (RMT ) Processor 10),11) 2
60 Mar. 2004 4.1 Responsive Processor Responsive Processor Responsive Link Responsive Link Responsive Processor Responsive Link 100 [Mbaud] 4 2 bit Responsive Processor 30 Responsive Processor 5 5 5 Responsive Link 1 4 8 SDRAM 16 [MB] 256 CAM DPM CAM CAM IP CAM 32 DPM 8 0 0 DPM 16 256 8 16 1 8 bit 3.3 CODEC 12 14 1 byte 8 bit 12 10 Responsive Processor Fig. 10 Layout of Responsive Processor. 1 1 2 10 Responsive Processor SPARC 300 [k gates] 8 Responsive Link 2 5 Responsive Link 400 [k gates] 0.35µm CMOS 4 2,378 [k gates] 14.5 [mm] 14.5 [mm]=210 [mm 2 ] 416 BGA 40 [mm] 40 [mm] 3.3 [V] 2 [W] 3
Vol. 45 No. SIG 3(ACS 5) Responsive Link 61 3 Responsive Link Table 3 Speed vs. power on Responsive Link. Modulation (Mbaud) 100 50 25 12.5 6.25 Data Speed (Mbps) 67 33 17 8 4 Event Latency(µsec) 3.1 6.2 12.5 25.0 50.5 Power (W) 0.2 0.1 0.05 0.02 0.01 11 Responsive Link Fig. 11 Hop counts vs. latency of Responsive Link. 100 [Mbaud] 1 8 byte Latency of Event =2.1[µsec] + 1.0[µsec] n [hops] 2.1 [µsec] 1 [hop] 1.0 [µsec] 12) Gigabit Ethernet Myrinet 13) 4 [byte] 10 [µsec] 11 Responsive Processor 25 [Mbaud] Responsive Link ideal OT Responsive Processor RT-OS RT- Frontier 14) OS ideal OT 12 RMT Processor Fig. 12 Layout of RMT Processor. 4.2 RMT Processor RMT Processor Responsive Link Responsive Link RMT Processor Responsive Link 800 [Mbaud] 8 DDR SDRAM 256 [MB] 256 RMT Processor 1 Systemon-a-chip RMT Processing Unit 8way SMT Responsive Link PCI64 USB2.0 IEEE1394 DDR SDRAM I/F DMAC PWM 12 RMT Processor
62 Mar. 2004 RMT 6 [M gates] Responsive Link 4 600 [k gates] 0.13µm CMOS 8 Cu 14 [M gates] 10.0 [mm] 10.0 [mm]=100 [mm 2 ] BGA 40 [mm] 40 [mm] Core 1.0 [V] I/O 2.5 [V] 8 [W] 5. Responsive Link WG6 2003 9 IPSJ-TS 0006:2003 2) ISO/IEC JTC1 SC25 WG4 3) 6. Responsive Link Responsive Link Hot-Plug&Play Responsive Link PRESTO SORST Responsive Processor COE RMT Processor Responsive Link WG6 ISO/IEC JTC1 SC25 WG4 Responsive Link SG DHRC 1) Vol.19, No.3, pp.68 77 (2001). 2) http://www.itscj.ipsj.or.jp/ipsj-ts/ index.html 3) http://www.itscj.ipsj.or.jp/committees/sc25/ sc25.html 4) Vol.36, No.7, pp.1619 1629 (1995). 5) CODA Vol.J78 D I, No.8, pp.777 787 (1995). 6) Liu, J.W.S.: Real-Time Systems, pp. 159 179, Prentice Hall (2000). 7) 3460080 11-343139 (2003). 8) 2002-330162 (2002). 9) Halsall, F.: Data Communications, Computer Networks, and Open Systems, Forth Edition, Addison-Wesley Publishing Company (1995). 10) Vol.44, No.1, pp.6 13 (2003). 11) Responsive Multithreaded Processor 2003- ARC-145 pp.31 36 (2003). 12) OS µ PULSER Vol.98, No.687, pp.47 54 (1999). 13) http://www.myrinet.com/ 14) Kobayashi, H. and Yamasaki, N.: Scheduling Imprecise Computations with Wind-up Parts, 19th International Conference on Computers
Vol. 45 No. SIG 3(ACS 5) Responsive Link 63 and Their Applications, pp.232 235 (2003). ( 15 7 31 ) ( 15 11 1 ) 1966 5 1 1991 1996 1998 10 2000 4 1997 2000 21 LSI IEEE