Report Template

Similar documents
スライド 1

Stratix IIデバイス・ハンドブック Volume 1

MAX IIデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト

Report Template

コンフィギュレーション & テスト

Arria GXデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト

基盤設計時資料

IEEE (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices

PowerPoint Presentation

Nios II ハードウェア・チュートリアル

HA8000シリーズ ユーザーズガイド ~BIOS編~ HA8000/RS110/TS10 2013年6月~モデル

ECP2/ECP2M ユーザーズガイド

PowerPoint Presentation

Beryll Beryll Cyclone V GX FPGA FPGA ROM...

Nios II 簡易チュートリアル

1 2

XC9500 ISP CPLD JTAG Port 3 JTAG Controller In-System Programming Controller 8 36 Function Block Macrocells to 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCO

1 138

CM1-GTX

TOPLON PRIO操作手順

Revision

Microsoft Word - PIVマニュアル.doc

Version1.5

AN 100: ISPを使用するためのガイドライン

untitled

取扱説明書の読み替え一覧表

HA8000-bdシリーズ RAID設定ガイド HA8000-bd/BD10X2

ProVisionaire Control V3.0セットアップガイド

94

1 2

Power Calculator

A-GAGE High - Resolution MINI ARRAY Instruction Manual Printed in Japan J20005M

Express5800/320Lb, 320Lb-R, 320Lb2-R, 320Lc, 320Lc-Rユーザーズガイド(セットアップ編)

Report Template

Cleaner XL 1.5 クイックインストールガイド

GM-F520S/GM-F470S/GM-F420S

4

BIOS 設定書 BIOS 出荷時設定 BIOS 設定を工場出荷状態に戻す必要がある場合は 本書の手順に従って作業をおこなってください BIOS 設定を変更されていない場合は 本書の作業は必要ありません BIOS 出荷時設定は以下の手順でおこないます スタート A) BIOS の Setup Uti

4

Quartus II はじめてガイド - デバイス・プログラミング方法

AN 100: ISPを使用するためのガイドライン

IP1_ug.book

Quartus Prime はじめてガイド - デバイス・プログラミングの方法

Arduino UNO IS Report No. Report Medical Information System Laboratory

untitled

Introduction Purpose This training course demonstrates the use of the High-performance Embedded Workshop (HEW), a key tool for developing software for

DICOM UG_JPN_P book

DL1720/DL1740ディジタルオシロスコープユーザーズマニュアル

PowerPoint Presentation

Microsoft Word - Meta70_Preferences.doc

Cyclone II Device Handbook

2

WinPSKユーザーズガイド

Express5800/i110Rc-1hユーザーズガイド


本機をお使いの方へ

Specview Specview Specview STSCI(Space Telescope SCience Institute) VO Specview Web page htt


ワイヤレス~イーサネットレシーバー UWTC-REC3

1 124

EQUIUM EQUIUM S5010 1

iStorage NS500Rbユーザーズガイド

1 122

JAJP.indd

REVISION 2.85(6).I 1

R1LV1616H-I シリーズ

Quartus Prime - プログラミング・ファイルの生成や変換(Convert Programming Files)

1 2

0.2 Button TextBox: menu tab 2

N Express5800/R320a-E4 N Express5800/R320a-M4 ユーザーズガイド

Express5800/R320a-E4/Express5800/R320b-M4ユーザーズガイド

Express5800/R320a-E4, Express5800/R320b-M4ユーザーズガイド

Express5800/320Lc/320Lc-Rユーザーズガイド(セットアップ編)

RAID RAID 0 RAID 1 RAID 5 RAID * ( -1) * ( /2) * RAID A. SATA SSD B. BIOS SATA ( 1) C. RAID BIOS RAID D. RAID/AHCI 2 SATA SSD ( 1) ( ( 3) 2

MINI2440マニュアル


1 142

SR-X526R1 サーバ収容スイッチ ご利用にあたって

RAID RAID 0 RAID 1 RAID 5 RAID * ( -1) * ( /2) * RAID A. SATA B. BIOS SATA ( 1) C. RAID BIOS RAID D. SATA RAID/AHCI 2 SATA M.2 SSD ( 2) ( (

Introduction Purpose The course describes library configuration and usage in the High Performance Embedded Workshop (HEW), which speeds development of

R1LV0416Dシリーズ データシート

RT300i/RT140x/RT105i 取扱説明書

New version (2.15.1) of Specview is now available Dismiss Windows Specview.bat set spv= Specview set jhome= JAVA (C:\Program Files\Java\jre<version>\

RTX830 取扱説明書


RX600 & RX200シリーズ アプリケーションノート RX用仮想EEPROM

TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016

RT300/140/105シリーズ 取扱説明書

SR-X324T2/316T2 サーバ収容スイッチ ご利用にあたって

SR-X324T1/316T1 サーバ収容スイッチ ご利用にあたって

デジタル回路入門

Цифровой спутниковый ресивер Lumax DV 2400 IRD

2

quattro.PDF

PDW-75MD

oxygen49-61_userguide

DS90CP Gbps 4x4 LVDS Crosspoint Switch (jp)

FMUP-204取扱説明書

SR-X340TR1 サーバ収容スイッチ ご利用にあたって

ESP32-KEY-KIT-R1 (ESP-WROOM-32 ) Copyright c 2

Transcription:

1

( ) 4... 4... 4 ispvm system... 5... 6... 6... 7 I/O... 7 USB... 9... 12 ( )... 14... 15 ( ) 16... 16 Dual Boot... 16 Primary Image file... 19 USERCODE/UES... 21 I/O... 22... 24 ATE... 26 SVF... 29 SVF... 29 SVF... 30 VME... 31 VME... 31 C... 33 CPU... 34... 36 Universal File Writer... 37... 38 Application Specific BSDL File Generator... 39 Model300... 40 () 42... 42 2

... 43... 43 SVF... 45 3

( ) isplever Lattice isplever HP http://www.latticesemi.com/ (1) isp (2) (3) (4) / (5) /UES (6) (7) I/O (8) VME /VME-Processor (9) ATE HP, Genrad, Teradyne Marconi ATE AET (10) SVF (11) SVF (12) IEEE1532(ISC) (13) FPGA (14) (15) XML (.XCF ) TDI TDO JEDEC BYPASS ( 1 ) SVF /ispen /ENABLE /TRST /BSCAN /EPEN BSCAN ( I/O HiZ) 4

ispvm system Windows [] [ ] [Lattice Semiconductor] [] isplever Project Navigator isplever Project Navigator 1-1 ispvm 1-2 1-2 isplever 5

Lattice PC USB 25pin 1-3 Vantis http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf PC USB 6

PC 3 [isptools] [Device Scan] F2 ISP JTAG ISP Mix Scan 1-4 SCAN SCAN 1-4 JTAG-NOP I/O SCAN [Options] [Cable and I/O Setup] 7

I/O 1-5 I/O 1-1 1-1 I/O Cable Type Lattice Vantis Vantis USB USB Port Setting Auto Detect ( Vantis ) Custom Port 0x TRST/Reset Pin Connected Done Pin Connected ispen/bscan Pin Connected Prog Pin Connected INIT Pin Connected TRST DONE ispen/bscan Prog INIT ON Set High Active High Set Low Active Low OFF: ON OFF: ON Set High Active High Set Low Active Low OFF: ON OFF: ON OFF: Windows XP USB 8

USB Admin ispvmsystem 1-6 USB 1-6 USB 1-7 1-7 USB USB PC Wizard Wizard 1-8 9

1-9 C: WINDOWS Sysytem32 1-9 1-10Lattice USB ISP Programmer Lattice USB ISP Programmer ispvmsystem 1-10 10

1-11 1-11 Windows USB Lattice USB ISP Programmer 1-12 USB 11

1-4 SCAN 1-13 1-13 Data File Browse EC/ECP/ECP2/SC bit rbf XP/XO isc jed 1-2 Fast Program Erase,Programming,Verify Erase,Programming,Verify,Secure Verify Only Verify ID Erase Only Display ID Bypass Calculate Checksum Verify USERCODE Display USERCODE Read and Save JEDEC Read DONE bit 1-2 (*1) DONE bit *1 Verify,Checksum 12

Device Access Options 1-3 1-5 1-3 Device Access Options (EC/ECP/ECP2 ) JTAG 1532 Mode Static RAM Cell Background SPI Flash Programming Advanced SPI Flash Programming Serial Mode JTAG JTAG SPI FPGA SPI 1-4 Device Access Options (SC ) JTAG Mode Serial Mode JTAG 1-5 Device Access Options (XP/XO ) Flash Programing Mode Flash Background Mode Static RAM Cell Mode Static RAM Cell Backgournd Mode SRAM SRAM 13

( ) GO () ( ) 1-14 PASS DONE Operation FAIL PASS DONE ( ) FAIL ispvm( ) LOG [Edit] [Clear Log File] 14

JTAG u [File] [Save] Save 1-15 xcf spvm Systemu [File] [Save] ( ) ( ) 15

( ) ispvm Dual Boot Lattice ECP2/ECP2M SPI Flash Dual Boot ispvm SCAN 2-1 ECP2/M Device List 2-1 2-2 16

2-2 Device Access Options Dual Boot SPI Flash Programming SPI Flash Options 17

2-3 SPI Flash 6 Flash Device Select SPI Flash Data File Browse Operation SPI Flash Erase,Program,Verify Golden Boot File Primary Boot File Golden Boot File Primary boot file Primary Boot File Generate OK 18

Primary Image file ispvm Primary Image File Dual Boot Log Primary Image Golden Image 2-4 LOG ispvm LOG 2-5 2-5 Golden Primary Start Enc Primary Primary 2.2 SPI Flash 19

2-6 SPI Flash 6 Flash Device Select SPI Flash Data File Browse Operation SPI Flash Erase,Program,Verify Staring Address Ending Address OK 20

USERCODE/UES FPGA USERCODE USERCODE [Option] [Dsiplay USERCODE/UES Options] 2. Device Information [Advanced] [Advanced Device Information] 3. [USERCODE/UES Field]UES [Apply UES] 4. [Auto-Increment After Program by] 1 0 2-7 USERCODE/UES USECODE USERCODE/UES Field in 2-8 Advanced Device Information 21

I/O I/O 1. [Device Information] 2. [Expand] 3. [Device Information][I/O Status] I/O I/O 2-9 Device Information I/O 2-1 CustomDynamic IO BSDL Edit 2-1 Device Access Options (EC/ECP/ECP2 ) High-Z(Default) All 1 s All 0 s Leave Alone Custom Dynamic IO Caputure Hi-Z High Low I/O ( High-Z ) Leave Alone Custom Leave Alone Edit I/O Dynamic 22

I/O CustomDynamic IOBSDL BSDL HP () BSDL EDIT [IO Vector Editor] 2-10 I/O Vector Editor [IO Vector Editor] I/O ( ) [Apply] [Save As] I/O (*.iov) 23

[Project] [Project Setting] 2-11 2-11 2-2 Sequential Program Turbo Program Entire Chain Selected Device Operation Override Disable Board Setup Checking Avoid Test Logic Reset State Continue Download Even on Error Starting/Ending TAP State (JTAG ) (Lattice /) JTAG Test Logic Reset JTAG 24

[Advance] 2-12 () 2-3 () TCK Low Pulse Width Delay Comment TCK 25

ATE (ATE : Automatic Test Equipment) ATE Gen Rad HP 3070 HP 3065 Teradyne 1800 Teradyne L200/300 SVF(Serial Vector Format) ATE SVF ATE SVF http://www.asset-intertech.com : isptools ispvmsystem documents svf_standard.pdf ATE Project Generate ATE Vector ATE 2-13 ATE 26

Tester Type 2-14 ATE 2-14 ATE Tester Type Header File Advanced More 2-15 ATE Advanced Options 27

2-4 Split File Maximum number of vectors per file Split File without initialization Program Vectors Only Erase Vectors Only Vector Signal Order HP-PFC Data ATE ispen,mode SCLK ATE More OK ATE Advanced Options ATE Generate ATE 28

SVF SVF Project Generate SVF File SVF SVF 2-16 SVF SVF 2-17 SVF Options Build SVF File For Single Device Generate SVF 2-17 SVF () 29

SVF SVF 2-18 SVF Options Build Sequential Chain SVF File Generate SVF 2-18 SVF () 30

VME VME VME VME VME Project Generate SVF File VME 2-19 VME VME VME12 VME11 VME** ** VME 2-20 VME 31

2-5 2-5 Programing Mode Continue If Fail Turbo VME File Compress VME File Loop VME FIle Commnet VME Program Setting.. Turbo VME VME VME Generate VME 32

C 2-20 VME VME2HEX 2-21 VME HEX 2-21 VME HEX Generate 2-22 ( c) ( h) 2-22 C 33

ispvm CPU ispvmsystem ispvmembedded SoureCode readme.txt CPU FPGA CPU CPU Project Generate SVF File CPU 2-23 CPU CPU 2-24 CPU 2-6 34

2-6 Format Comment Output File Advanced Configuration Mode Byte Wide Bit Mirror Binary C-CODE Intel-HEX HEX Text( ) ON Browse CFG HEX MSB LSB Generate CPU 35

isvvm System : ispvm ispvm.exe infile <> /-processtype< >/-cabletype< >/-portaddress< >/-processmode< > 2-7 () ( ) ( ) ( ) ( ) USB ( ) xcf dld (turbo) (sequetial) (lattice) (vantis) USB (usb) LPT1(0x0378) LPT2(0x0278) LPT3(0x03BC) (0xXXXX)LPT1(0x0378) 0 15 15 Ezusb-15 Ezusb-0 (-h)(-o) (-w) C: isptools ispvmsystem ispvm.exe -infile C: demo demo.xcf -processtype turbo -cabletype lattice -portaddress 0x0278 36

Universal File Writer Universal File Writer( UFW) UFW isptools Universal File Writer UFW 2-25 VME UFW 2-26 Universal File Writer(UFW) UFW 37

EC/ECP/ECP2 UFW UFW Bitstream Bitstream Settings [Compression] ON 2-27 38

Application Specific BSDL File Generator Application Specific BSDL File Generator BSDL(Boundary Scan Description Language) VREF LVDS I/O BSDL VREF LVDS BSDL JEDEC ISC BSDL WEB Application Specific BSDL File Generator s isptools Application Specifig BSDL File Generator BSDL BSDL 2-28 Application Specific BSDL File Generator BSDL BLDL Generate 39

Model300 Model300 Lattice ISP/JTAG Model300 Model300 Vcc 1.8V,2.5V,3.3V 5.0V ispvm Model300 AC Web 2-29 Model300 40

Model300 Model300 Programmer isptools Model300 Programmer ( M300 ) 2-30 Model300 Programmer Model300 Programmer Auto-Detect ( ) LED ( Model300 ) Go Status ( ) 41

() JTAG / IDCODE JTAG isptools Board Diagonostics 3-1 JTAG / 3-1 IDCODE IDCODE JTAG IDCODE 1 0 TCK TMS 42

isptools Repetitive Download 3-2 (Number of) (Stop on Error Number) OK Options Cable and I/O Port Setup Cable and I/O Setting Debug Mode 3-3 43

3-4 Loop ESC Power Check Test Setting Toggle 1-0-1 Hold High Hold Low 0 Read(TDO Only) TDO Apply Loop View Log Cable Signal Test operations Power Check 44

SVF SVF SVF ISP/JTAG JEDEC SVF SVF SVF CPLD SVF 16 SVF SVF SVF isptools SVF Interpreter SVF 3-5 SVF SVF SVF Advanced Debug SVF 45

SVF 3-6 Configuration SVF Options ( SVF Options ) SVF Options 3-6 SVF SVF Options 3-7 JTAG 3-7 SVF Options 46

3-8 3-8 Configuration SVF Output JTAG TAP 3-9 SVF Output () 47