1 2 2.1SEE SEUSingle Event Upset SELSingle Event Latchup 245 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 63
SEBSingle Event Burnout 2.2 64 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 246
2.3SER N 3 3.1 N SER FCS Q F A crit Kexp Q s F K CS A Q Q 247 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 65
3.2 3.3 4 66 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 248
4.1 4.2WN 249 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 67
4.3 SER 68 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 250
5 1 ComputerWorld, p. 12, Dec. 3, 2001. 2In-flight upset, 154 km west of learmonth, WA, 7 October 2008, VH-QPA Airbus A330-303,ATSB Transp. Safety Report - Aviation Occurrence Investig., no. AO-2008-070, pp. 1 313, Dec. 2011. 3 K. Shimbo, T. Toba, K. Nishii, E. Ibe, Y. Taniguchi, and Y. Yahagi, Quantification & mitigation techniques of soft-error rates in routers validated in accelerated neutron irradiation test and field test, SELSE, 2011. 4 J. Warnock, et. al., 22nm next-generation IBM system z microprocessor,in ISSCC, Feb. 2015, pp. 1 3. 5 R. Kan, T. Tanaka, G. Sugizaki, R. Nishiyama, S. Sakabayashi, Y. Koyanagi, R. Iwatsuki, K. Hayasaka, T. Uemura, G. Ito, Y. Ozeki, H. Adachi, K. Furuya, and T. Motokurumada, A 10th generation 16-core sparc64 processor for mission-critical unix server, in ISSCC, 2013, pp. 60 61. 6, SRAM MOSFET, Technical report of IEICE. ICD, vol. 103, no. 2, pp. 57 62, 2003. 7 251 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 69
SRAM,Technical report of IEICE. ICD, vol. 105, no. 2, pp. 31 36, 2005. 8,no. 903, pp. 145 155, 2005. 9 P. Hazucha, C. Svensson, and S. Wender, Cosmic- Ray Soft Error Rate Characterization of a Standard 0.6-m CMOS Process,IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1422 1429, 2000. 10 P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic,in ICDSN, 2002, pp. 389 398. 11 P. Hazucha and C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate,ieee Trans. Nucl. Sci., vol. 47, no. 6, pp. 2586 2594, 2000. 12 M. Hifumi, E. Sonezaki, J. Furuta, and K. Kobayashi, Radiation hardness evaluations of ffs on 28nm and 65nm thin BOX FD-SOI processes by heavy-ion irradiation,in RASEDA, Nov. 2015, pp. 93 96. 13 J. Furuta, J. Yamaguchi, and K. Kobayashi, A radiation-hardened non-redundant flip-flop, stacked leveling critical charge flip-flop in a 65 nm thin BOX FD-SOI process,ieee Trans. Nucl. Sci., vol. 63, no. 4, pp. 2080 2086, Aug. 2016. 14 A. Makihara, T. Yamaguchi, Y. Tsuchiya, T. Arimitsu, H. Asai, Y. Iide, H. Shindou, S. Kuboyama, and S. Matsuda, SEE in a 0.15 m fully depleted CMOS/ SOI commercial process,ieee Trans. Nucl. Sci., vol. 51, no. 6, pp. 3621 3625, 2004. 15 J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera, A 65nm bistable cross-coupled dual modular redundancy flip-flop capable of protecting soft errors on the C-element,in VLSI Circuit Symp., June 2010, pp. 123 124. 16 C. Hamanaka, R. Yamamoto, J. Furuta, K. Kubota, K. Kobayashi, and H. Onodera, Variation-tolerance of a 65-nm error-hardened dual-modular-redundancy flip-flop measured by shift-register-based monitor structures,ieice Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, no. 12, pp. 2669 2675, Dec. 2011. 17 R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera, An area-effcient 65 nm radiationhard dual-modular flip-flop to avoid multiple cell upsets,ieee Trans. Nucl. Sci., vol. 58, no. 6, pp. 3053 3059, Dec. 2011. 18 C. Takahashi, S. Shibahara, K. Fukuoka, J. Matsushima, Y. Kitaji, Y. Shimazaki, H. Hara, and T. Irita, A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10 7 random hardware failures per hour reliability,in ISSCC, Jan. 2016, pp. 80 81. 19 M. Miyamura, S. Nakaya, M. Tada, T. Sakamoto, K. Okamoto, N. Banno, S. Ishida, K. Ito, H. Hada, N. Sakimura, T. Sugibayashi, and M. Motomura, Programmable cell array using rewritable solidelectrolyte switch integrated in 90nm CMOS,in ISSCC, Feb. 2011, pp. 228 229. 20 T. Uemura, Y. Tosaka, H. Matsuyama, K. Shono, C. Uchibori, K. Takahisa, M. Fukuda, and K. Hatanaka, SEILA: Soft error immune latch for mitigating multi-node-seu and local-clock-set,in IRPS, May 2010, pp. 218 223. 21 H. Asai, K. Sugimoto, I. Nashiyama, Y. Iide, K. Shiba, M. Matsuda, and Y. Miyazaki, Terrestrial neutroninduced single-event burnout in SiC power diodes, IEEE Trans. Nucl. Sci., vol. 59, no. 4, pp. 880 885, Aug. 2012. 22 N. Kanekawa, E. H. Ibe, T. Suga, and Y. Uematsu, Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances, Springer Science & Business Media, 2010. 23 https://www.cts-advantest.com/ja/stories/marvelser-evaluation. 24 Y. Tosaka, R. Takasu, T. Uemura, H. Ehara, H. Matsuyama, S. Satoh, A. Kawai, and M. Hayashi, Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of mauna kea,in IRPS, May 2008, pp. 727 728. 25 L. F. Kastensmidt, L. Carro, and R. Reis, Fault- Tolerance Techniques for SRAM-Based FPGAs, Springer, 2006. 26 http://phits.jaea.go.jp/index.html. 27 K. Zhang, S. Umehara, J. Yamaguchi, J. Furuta, and K. Kobayashi, Analysis of soft error rates in 65- and 28-nm FD-SOI processes depending on BOX region thickness and body bias by Monte-Carlo based simulations,ieee Trans. Nucl. Sci., vol. 63, no. 4, pp. 2002 2009, Aug. 2016. 70 J. Particle Accelerator Society of Japan, Vol. 13, No. 4, 2016 252