: Spartan-3E FPGA XAPP928 (v1.1) 2007 4 19 LVDS/DVI IP Spartan-3E HW-SPA3E-DISP-DK-UNI-G (v1.1) LCD TV IP Spartan -3E FPGA 1 DVI (CTC) (PGC) (IDE) (LVDS TX) DVI TX Spartan-3E DIP IP DVI Interface Color Temperature Correction (CTC) Precise Gamma Correction (PGC) Image Dithering Engine (IDE) LVDS or DVI TX Interface Flat Panel 1 : IP X928_01_040907 IP 1 Spartan-3E IP 1 : IP DVI CTC ( ) PGC () IDE ( ) DVI GB PGC 3 x 10 3 x 8 LVDS DVI LCD 2007 Xilinx, Inc. All ights eserved. XILINX Xilinx Xilinx Xilinx Xilinx Inc. : Xilinx Xilinx Xilinx XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 1
IP Spartan-3E DIP ( 2) User Push Button Switch Settings (PSW 2, 1, 0 are above) User Set DIP Switch Block 2 : X928_02_041907 2 : DIP SW4 SW3 SW2 SW1 SW0 DIP DVI X ON PGC () On On (00) : 2.2/2.2 (1.00) On Off (01) : 2.4/2.2 (1.09) Off On (10) : 2.6/2.2 (1.18) On On (11) : PGC CTC ( ) On On (00) : On Off (01) : 6500K Off On (10) : 8500K On On (11) : 10000K 0 : 1 : DVI (X) DVI X DVI 3 DVI X DIP 2 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
CTC IP 3 : LVDS/DVI X LVDS DIP DIP DIP_SWITCH_0 [ SW4] DIPS_X_SELECT ON CTC IP ( K) 5000K 5500K 2000K /15000K G B GB CIE x-y CIE ( 3) 5500K x = y = 0.33 3 : CIE X928_03_040907 PDP ( ) CT ( ) PDP PDP PDP XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 3
CTC IP CTC CIE x y 8 10 GB color-mixing x-y ( ) CIE GB Frame White Point Bus VIDEO_GB Data Bus White Point Bus Frame White Point Estimation -Color Correction CTC_PGC_DATA_DY White Point Calculation Temp Cntr Cntr CIE eference Cntr G-Color Correction Cntr Bypass Logic CTC_PGC DATA[7:0] CTC_PGC_G_DATA[7:0] CTC_PGC_B_DATA[7:0] ESET_N CLK DIPS_CTC_CNT B-Color Correction VIDEO_CTC_DATA_EN VIDEO_CTC_END_FM VIDEO_CTC_STT_FM VIDEO_CTC_DY VIDEO_CTC DATA[7:0] CTC Control Logic CTC_PGC_DATA_EN VIDEO_CTC_G_DATA[7:0] VIDEO_CTC_B_DATA[7:0] 4 : CTC IP X928_04_041907 4 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
CTC IP 4 CTC 4 : CTC ESET_N I/O CTC Low CLK DIPS_CTC_CNT VIDEO_CTC _STT_FM VIDEO_CTC _END_FM VIDEO_CTC _DATA_EN VIDEO_CTC_GB_DATA[23:0] CTC_PGC_DATA_DY CTC_PGC_DATA_EN CTC_PGC_GB_DATA[23:0] DIP ( SW1 SW0) CTC LVDS CTC LVDS CTC LVDS CTC GB 24 CTC PGC PGC CTC_PGC_GB_DATA[23:0] GB 24 PGC (6500K 8000K 9300K) DIP CIE GB CTC GB GB CTC ( ) CTC GB 1 : in = wt in -------- = out wf 1 wt = CIE wf = out = CTC XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 5
CTC IP wt wf G B CTC PGC () CTC_PGC_DATA_DY DIP 5 DIP 5 : CTC DIP DIP DIP_SWITCH_TYPE0 DIP_SWITCH_TYPE1 DIPS_CTC_CNT0_IP DIPS_CTC_CNT1_IP CTC_TYPE1 & CTC_TYPE0 [ 1 0] 11 : 10 : 6500K 01 : 8500K 00 : 10000K CTC 6 CTC Spartan-3E XC3S1600E FG484 FPGA 6 : CTC 5,275 29,504 18% 4 LUT 3,579 29,504 12% 4 LUT 3,664 29,504 12% 3,579 1 84 IOB 58 376 15% AM 4 36 11% MULT18X18 4 36 11% GCLK 1 24 4% 3,423 14,752 23% 3,423 3,423 100% 0 3,423 0% 6 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
PGC () PGC ( ) = ^( ) 5 () V s 0.1 ~ 0.4 0.8 ~ 1.0 I 5 : (V s ) (I) X928_05_040507 10 10 8 10 6 7 8 10 6 : 8 vs X928_06_040407 XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 7
PGC () X928_07_040507 7 : 10 vs 8 10 10 2 Y OUND 1023 X -------- 1 = 256 ------------------- Gamma : 2 X = GB (8 G B ) Y = 10 G B = ( ) 0.5 Y 10 DIP LUT ( ) G B G B 3 x 10 IDE ( ) DATA_EN DIP 8 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
PGC () BYPASSSEL ED[7:0] GEEN[7:0] F/F F/F EDFF GEENFF + + ADDE_OUT_ED ADDESSA ADDE_OUT_GEEN ADDESSB ED GEEN DUAL POT_U1 MUX MUX F/F F/F EDOUT[7:0] GEENOUT[7:0] BLUE[7:0] F/F BLUEFF + ADDE_OUT_BLUE ADDESSA BLUE SINGLE POT_U1 MUX F/F BLUEOUT[7:0] CTC_PGC_DY CLK ESET_N MUX 00 01 EADY Generation Logic PGC_IDE_DY 10 DIPSWITCH_INPUT CTC_PGC_DATA_EN DATAEN Generation Logic PGC_IDE_DATA_EN 8 : PGC X928_08_041907 7 PGC 7 : PGC I/O ESET_N Low CLK CTC_PGC_DY CTC PGC GEEN[7:0] Green 8 BLUE[7:0] Blue 8 ED[7:0] ed 8 CTC_PGC_DATA_EN CTC High BYPASSSEL PGC DIPSWITCH_INPUT[1:0] XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 9
PGC () 7 : PGC () I/O EDOUT[9:0] PGC 10 GEENOUT[9:0] PGC 10 BLUEOUT[9:0] PGC 10 PGC_IDE_DY PGC IDE PGC_IDE_DATA_EN PGC High IDE 0 DIP 8 DIP 8 : PGC DIP DIP DIP_SWITCH_TYPE0 DIP_SWITCH_TYPE1 SW3 SW2 DIPS_PGC_SEL0_IP DIPS_PGC_SEL1_IP PGC_TYPE1 & PGC_TYPE0 [ SW3 SW2] 00 : 2.2 01 : 2.4 10 : 2.6 11 : PGC 9 PGC 9 : PGC 50 29,504 1% 4 LUT 31 29,504 1% 4 LUT 31 29,504 1% IOB 63 376 17% AM 2 36 6% GCLK 1 24 4% 42 14,752 1% 42 42 100% 0 42 0% 10 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
IDE ( ) IDE ( ) ( 9) Black, White Gray 9 : 8 6 1 IDE PGC 30 (10 G B 3 ) IDE 10 ~ 8 2 x 2 3 x 10 3 ( G B) 2 LSB ( ) 8 MSB 2 LSB 2 00 ~ 11 () 8 4 (0% 25% 50% 75%) 2 x 2 0 1 2 3 X928_09_040907 0 1 0 1.. 2 3 2 3.. 0 1 0 1.. 2 3 2 3........ 2 2 LSB 8 8 XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 11
IDE ( ) 2 LSB IDE 2x2 24 ( G B 8 ) dither_data_ready LVDS/DVI TX BITS_IDE_TYPE0 BITS_IDE_TYPE1 ESET_N CLK DIther Matrix PGC_IDE_GB_PIX_DATA 10-bit PGC_IDE_DATA_VALID PGC_IDE_DATA_DY VIDEO_FAME_ACTIVE Bit Extractor LSB 2 bit MSB 8 bit LSB Comparator Adder Energy level to be added 8-bit Dithered FPGA Block AM IDE_PIX_DATA_OP (8 bits of ) DITHE_DATA_DY 10 : ( 1 ) 10 IDE 10 : IDE I/O ESET_N Low IDE CLK DCM ( ) BITS_IDE_TYPE0 11 BITS_IDE_TYPE1 11 X928_10_041007 PGC_IDE_DATA_VALID PGC IDE PGC_IDE_DATA_DY PGC IDE PGC_IDE_GB_PIX_DATA[29:0] PGC IDE 10 G B VIDEO_FAME_ACTIVE High Low 12 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
IDE ( ) 10 : IDE () I/O IDE_PIX_DATA _OP[23:0] 8 GB DITHE_DATA_DY DIP IDE 11 11 : IDE DIP DIP DIP_SWITCH_TYPE0 DIP_SWITCH_TYPE1 [ PSW0 PSW1] DIPS_IDE_TYPE0_IP DIPS_IDE_TYPE1_IP IDE_TYPE1 & IDE_TYPE0 [PSW1 PSW0] 00 : IDE 01 : 10 : 11 : IDE 12 IDE 12 : IDE (XC3S1600EFG484 ) 98 29,504 1% 4 LUT 170 29,504 1% 119 14,752 1% 119 119 100% 0 119 0% 4 LUT 188 29,504 1% 170 18 IOB 62 376 16% GCLK 1 24 4% XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 13
LVDS TX/DVI LVDS TX/DVI LVDS 28 LVCMOS/LVTTL 4 LVDS 5 LVDS 28 Spartan-3E LVDS DVI GB 24 GB 4 ( HSYNC VSYNC ) LVDS LVDS TX ( 11) DCM serdes_4b_7to1 DCM 3.5 clkx3p5 clkx3p5not 2 serdes_4b_7to1 28 4 7-to-1 clkx3p5 clkx3p5not 28 4 DataSync and Mux Selection clkin Digital Clock Manager clkx3p5not clkx3p5 DATAOUT_P[3:0] datain Input Buffer Data_eg._p mux DD egisters TTL to LVDS DATAOUT_N[3:0] CLKOUT_P Data_eg._n CLKOUT_N LVDS_TX X928_11_041007 11 : LVDS 13 LVDS ( LSB ) 13 : LVDS LVDS 0 0 4 8 12 16 20 24 1 1 5 9 13 17 21 25 2 2 6 10 14 18 22 26 3 3 7 11 15 19 23 27 http://japan.xilinx.com/bvdocs/appnotes/xapp928.zip 14 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
12 : X928_12_041007 14 14 : 5,748 29,504 19% 5,743 5 4 LUT 3,878 29,504 13% 3,878 33 88 4 LUT 3,999 29,504 14% IOB 93 376 25% AM 6 36 17% MULT18X18 4 36 11% GCLK 7 24 24% DCM 3 8 38% PM 2 3,709 14,752 25% 3,709 3,709 100% 0 3,821 0% XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 15
I/O I/O 13 Spartan-3E FPGA I/O SYS_ST_IP DVI_X_CLK DVI_X 28 DIPS_CTC_CNT0_IP DIPS_CTC_CNT1_IP DIPS_PGC_EN_IP DIPS_PGC_SEL0_IP DIPS_PGC_SEL1_IP DIPS_IDE_TYPE0_IP DIPS_IDE_TYPE1_IP DIPS_X_SELECT Display Panel Solution FPGA 4 4 EDGE_OUT DKEN_OUT MSEN_OUT PD_OUT ISEL_OUT BSEL_OUT DSEL_OUT DVI_TX_CLK_P DVI_TX_CLK_N DATAOUT_P[3:0] DATAOUT_N[3:0] CLKOUT_P CLKOUT_N 13 : FPGA I/O X928_13_041907 COE I : O : Low _N + - 15 Spartan-3E 15 : I/O SYS_ST_IP GB DVI_X_CLK DVI DVI_X[27:0] DVI (24 GB VSYNC HSYNC DE) LVDS EDGE_OUT TFP410 DVI_TX (DVI ) DKEN_OUT TFP410 DVI_TX MSEN_OUT TFP410 DVI_TX PD_OUT TFP410 DVI_TX ISEL_OUT TFP410 DVI_TX BSEL_OUT TFP410 DVI_TX 16 japan.xilinx.com XAPP928 (v1.1) 2007 4 19
15 : () I/O DSEL_OUT TFP410 DVI_TX DVI_TX[27:0] DVI (24 GB VSYNC HSYNC DE) DVI_TX_CLK DVI DVI_TX_CLK_N TFP410 DVI_TX LVDS TX DATA_OUT_P[3:0] DATA_OUT_N[3:0] CLKOUT_P CLKOUT_N LVDS LVDS 14 VSYNC HSYNC DE ( : ) VSYNC vsync_b vsync_e HSYNC DE x=0; y=0 14 : X928_14_041007 : LVDS IP XAPP486 : Spartan-3E FPGA 666 Mbps 7:1 2007/03/23 1.0 2007/04/19 1.1 XAPP928 (v1.1) 2007 4 19 japan.xilinx.com 17