NoC 1,a) 1,b) Network-on-a-Chip NoC NoC PID NoC Satoru Miyasono 1,a) Hiroshi Saito 1,b) Abstract: In this paper, we propose a code partition tool to implement an application code which targets a single-core on Network-on-a-Chip (NoC). First, we define communication functions for communication between cores of NoC. The code partition tool generates a behavioral function code using the defined communicaiton functions and given task scheduling/allocation result. In addition, the code patiotion tool removes unnecessary function code for each core. In the experiments, we implement a part of the tool and apply it to two applications, PID controller and ABS (Antilock Brake System) as case studies. Then, we evaluate the execution time and code size. 1. Multi-Processor System-on-a-Chip Network-on-a-Chip NoC Mathwarks Simulink C 1 a) m5161151@u-aizu.ac.jp b) hiroshis@u-aizu.ac.jp C NoC EmbeddedCoder 2 3 4 PID NoC 5 1
1 (a) (b) 2. 2.1 Network-on-a-Chip Network-on-a-Chip NoC IP IP System-on-a-Chip IP NI IP 2 3 NoC 2.2 1 a 1 b 1 a 3. C NoC 2 3.1 NoC 3 NoC Altera Nios II NoCGenerator [1] 4 NI XY Nios II ALTERA SOPC NI NI SOPC Nios II Nios II AvalonBus Nios II IOWR 32DIRECT IORD 32DIRECT Nios II 4 NI SOPC Nios II NI Verilog 5 NoC 2
NI NI Nios II receive interrupts IORD 32DIRECT NI IOWR 32DIRECT NI receive interrupts 6 5 send message receive interrupts 32 (id) Nios II NI NI 2 01 10 11 send message receive interrupts C 6 send message send massage IOWR 32 DIRECT NI IOWR 32 DIRECT NI receive interrupts 3.2 3.2.1 app.xml app app n*.xml n xml app.xml app.xml 7 a tasks task task task name node start task succs preds preds task succs task succs succ succ namenode preds pred pred namenode app n*.xml app.xml task node app n*.xml 8 a app task.xml app task.xml app.xml tasks task task name node node id 3.2.2 Simulink EmbeddedCoder Simulink main ert main.c C app.c app.happ.c 3
8 app n.xml 7 app.xml receive interrupts 3.3 5 3.3.1 PatternXML2Comm PatternXML2Comm NoC communication.c communication.c send message receive interrupts C NodeCodeGen app.xml receive interrups app pattern.xml task node preds pred node pred name receive interrupts #define ID * (* ) communication.c NI main volatile unsigned int get =0; communication.c unsigned int receive interrupts if if(identify==) =IORD 32DIRECT();else if(identify== receive interrupts send message communication.c 7 app.xml receive interrupts 3.3.2 NodeXML2appNode NodeXML2appnode NoC EmbeddedCoder Nios II NI app node.c app node app node app n*.xml tasks task preds pred node while task name succs succ send message ValueName xml SwapValueName 8 app.xml receive interrupts 3.3.3 SwapValueName SwapValueName NodeXML2appnode EmbeddedCoder Function.xml Function.xml tasks task task name outputs inputs outputs output output inputs input input Function.xml app.xml task name app.c app.c void } =, ; * / + - % ) ( < >! = 4
9 ; = ; Function.xml Function.xml app.h app.h } ExternalInputs } app.h } ExternalOutputs Function.xml task name outputs output U. Y. task inputs Function.xml app node*.c Function.xml task name ValueName app node*.c task outputs output app node.c Function.xml task app node*.c 9 3.3.4 NodeCodeGen NodeCodeGen 3 app n*.xml NoC node* EmbeddedCoder PatternXML2Comm communication.c NodeXML2appnode app node*.c app.c communication.c app node*.c node* EmbeddedCoder 3.3.5 RemoveCode RemoveCode NodeCodeGen NodeCodeGen app n.xml app.c app initialize app terminate app.c app.h receive interrupts app n.xml task preds pred node receive interrupts 4. PID ABS Simulink EmbeddedCoder NoC Remove- Func Java Eclipse AS AS AS Simulink Simulink AS PID 10 AS ABS 8 AS PID ABS Simulink [3] NoC 2x3 Altera Nios II/f FPGA Cyclone IV EP4CE115F29C7 32KB Nios II/f 1 32KB [2] NoC 2x3 PID ABS 3 5 0 1 2 4 FPGA 7.2 ns NoC 7.4 ns Simulink Nios II EDS 5
10 ABS AS 3,808 81.3% 40.4% 11 NoC task send message sendwait receive interrupts receive PID ABS AS AS 31.5us AS NoC PID 3 send receive wait ABS AS send message receive interrupts 5. 11 objdump Simulink main step NoC 10 10 AS AS 80% AS 820 AS PID 10 ABS 8 AS NoC PID AS 1,372 PID ABS RemoveFunc CREST [1] Hiroki Matsutani et al., Performance Cost and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree- Based On-Chip Network, Proc. Parallel and Distributed Processing Symposium, pp.1-10, March.2007. [2] VLD2012-127 vol.112 no.451 pp.61-67 March.2012. [3] MathWorks, Simulink,http://www.mathworks. co.jp/jp/help/simulink/examples/index.html#general-a pplications 6