Vol. 42 No. 4 Apr VC 2 VC 4 VC VC 4 Recover-x Performance Evaluation of Adaptive Routers Based on the Number of Virtual Channels and Operating F
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1 Vol. 42 No. 4 Apr VC 2 VC 4 VC VC 4 Recover-x Performance Evaluation of Adaptive Routers Based on the Number of Virtual Channels and Operating Frequencies Maki Horita, Tsutomu Yoshinaga, Kanemitsu Ootsu and Takanobu Baba In order to improve the communication performance of the parallel computer network,we should evaluate the various routing algorithms. Adaptive routing or virtual channels (VCs) can improve communication performance by increasing routing flexibility. However,the operating frequencies of the router become degraded,since the adaptive routing and the VCs require a complex and huge amount of hardware resources. Therefore,it is important to consider the trade-off between the routing flexibility and the operating frequency. We clarify this trade-off by evaluating the communication performance in 2D tori network for typical routers, taking into account the operating frequency of the routing circuits. Our experimental results show that the routers with four VCs per physical channel attain a good trade-off between routing flexibility and operating frequency. Adaptive routers show higher performance than non-adaptive routers due to their higher routing flexibility,especially in the case of a nonuniform communication pattern. The Recover-x router with four VCs per physical channel shows robust performance both in uniform and non-uniform traffic Department of Information Science, Faculty of Engineering, Utsunomiya University Graduate School of Information Systems, University of Electro-Communications 4),6),8) VC 4 VC 9) VC 3) HDL 714
2 Vol. 42 No Dimension-order -channel 2) Recover-x 11) Recover-x DISHA 1) Recover-x DISHA VC 100 VC HDL 4 VC RTL Dimension-order Dimension-order 2 X Y X Y channel -channel / VC -channel Duato 5) Recover-x Recover-x Y X -channel VC DISHA Recover-x (a) 4 ± X ± Y Port PE I/F 1 (b)
3 716 Apr VC VC Table 1 The number of VCs for each VC configuration. X Y PE I/F VC VC VC =2 X +2 Y + PE I/F VCC Fig. 1 Hardware organization of the routers. VC BC Buffer Controller AD Address Decoder BC 8 FIFO (1) VC BC AD (2) AD Recover-x (3) OCA Output Channel Arbiter VC VC ( 4 ) OCA AD BC VCC Virtual Channel output Controller VC VC VC VC VC3 VC4 VC5 PE I/F 2 VC VC VC VC VC VC VC node#a node#b node#b node#c node#a node#c node#a 2 X Y Dimension-order X Y 3 VC VC Dimension-order VC 3 -channel VC3 VC / -channel 1 2 / VC 4 Recover-x X VC 1 2 Y
4 Vol. 42 No VC VC VC VC VC 7) Dimension-order VC -channel Recover-x 2 Dimension-order VC Fig. 2 VC assignment for a Dimension-order router. 3 -channel VC Fig. 3 VC assignment for a -channel router. VC AD OCA VC VC VC VC -channel Recover-x VC VC 1 10) Verilog-HDL 4 Recover-x VC Fig. 4 VC assignment for a Recover-x router. -channel Synopsys HDL Compiler version Medium effort LSI Logic 0.6 µm Array- Based Gate Array Verilog-HDL
5 718 Apr Table 2 Synthesis results. Dimension-order -channel Recover-x VCs/port MHz Kgates Kgates Kgates VC Recover-x -channel VC Dimension-order VC VC VC VC3 4 VC4 5 VC VC3 VC5 OCA VC3 VC OCA VC Recover-x 3 Recover-x Kgates Table 3 Each block area for Recover-x routers (Kgates). VC3 VC4 VC5 ±X ±Y ±X ±Y ±X ±Y AD BC OCA VCC channel Dimension-order 1 Recover-x -channel VC3 Recover-x -channel VC4 /5 VC -channel VC VC Dimension-order VC VC 3 Recover-x BC AD OCA VC X AD Y OCA AD BC X Y OCA VC X
6 Vol. 42 No Cadence Verilog-XL = 100 Hot-spot % (4,j) 0 j 9 10 Random PE PE PE I/F Recover-x VC MHz Hot-spot (a) 100 MHz Hot-spot Recover-x -channel Dimension-order Hot-spot Dimension-order -channel VC -channel Dimension-order VC3 4 Recover-x VC3 4 5 VCC VC Recover-x -channel VC5 VC3 4 5 (b) Dimensionorder VC channel 64 VC
7 720 Apr Fig. 5 5 Hot-spot Bandwidth for the Hot-spot traffic. 6 Fig. 6 Hot-spot Latency for the Hot-spot traffic. VC5 128 VC5 VC4 VC4 VC5 Recover-x VC3 Hot-spot VC VC Hot-spot
8 Vol. 42 No PE PE 6(a) -channel Recover-x Recover-x VC 3 -channel 1 VC3 6(b) Recover-x -channel Dimension-order -channel Dimension-order -channel Recover-x VC5 Dimension-order -channel VC3 VC4 5 VC4 5 Recover-x -channel Dimension-order Recover-x VC Random Random Random 7 (a) 100 MHz Hot-spot 32 Hot-spot Dimension-order -channel VC VC 7 (b) -channel Dimension-order Recover-x VC Random 8 (a) 100 MHz -channel VC -channel Recover-x Dimension-order 6(a) Random VC VC 8 (b) Dimension-order -channel Recover-x VC VC5 VC4 Recover-x 3 VC4 6. Dimension-order -channel Recoverx 3 VC VC3 4
9 722 Apr Fig. 7 7 Random Bandwidth for the Random traffic. 8 Fig. 8 Random Latency for the Random traffic. 4 5 Recover-x VC4 /
10 Vol. 42 No CAD B A ) Anjan, K.V. and Pinkston, T.M.: An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA, Proc. 22nd ISCA, pp (1995). 2) Berman, P.E., Gravano, L., Pifarré, G.D. and Sanz, J.L.C.: Adaptive Deadlock and Livelock Free Routing with all Minimal Paths in Torus Networks, Proc. SPAA (1992). 3) Chien, A.A.: A Cost and Speed Model for k- ary n-cube Wormhole Routers, IEEE Trans. Parallel and Distributed Systems, Vol.9, No.2, pp (1998). 4) Dai, D. and Panda, D.K.: How Much Does Network Contention Affect Distributed Shared Memory Performance?, Proc.ICPP 97, pp (1997). 5) Duato, J.: A New Theory of Deadlock-Free Adaptive Routing in Wormhole Network, IEEE Trans. Parallel and Distributed Systems, Vol.4, No.12, pp (1993). 6) Flich, J., Malumbres, M.P., López, P. and Duato, J.: Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation, Proc. ICPP 99 (1999). 7) JSPP2000 pp (2000). 8) adaptive routing Proc. HOKKE2000, 2000-ARC-137-9, pp (2000). 9) Vaidya, A.S., Sivasubramaniam, A. and Das, C.R.: LAPSES: A Recipe for High Performance Adaptive Router Design, Proc. HPCA (1999). 10) Vol.40, No.5, pp (1999). 11) Recover-x Vol.41, No.5, pp (2000). ( ) ( ) IEEE IEEE 1992 Best Author Microprogrammable Parallel Computer MIT Press
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