DDR3 SDRAMメモリ・インタフェースのレベリング手法の活用

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1 WP /JP

2 DLL (PVT compensation) 90 PLL PVT compensated FPGA fabric 90 Stratix III I/O block

3 Read Dynamic OC T FPGA Write Memory

4 Run Time Configurable Run Time Configurable Set at Compile dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs

5 DQS in Offset Reference clock 100 to 400 MHz DLL Block Phase comparator Control signal 16 delay blocks Shifted DQS

6

7 101 Innovation Drive San Jose, CA Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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