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1 DVI December 2003
2 December 2003
3 ? December 2003 Page 3
4 Host Data Device Clock December 2003 Page 4
5 Data Skew Host Data Device Clock Setup Hold Data Skew December 2003 Page 5
6 Host Data Device Clock Setup Hold Propagation Delay December 2003 Page 6
7 EMC Current Host Data Device Clock Current December 2003 Page 7
8 Host Device Device Device December 2003 Page 8
9 CDR D Q PLL Clk ( 2 ) 1 CDR December 2003 Page 9
10 dv/dt = 4V/ns 5V 1ns dv/dt = 4V/ns 1V 200ps December 2003 Page 10
11 (D+) 1V (D-) 1V (D+) (D-) Common mode Noise December 2003 Page 11
12 EMI EMI Current (D+) (D-) Current December 2003 Page 12
13 DVI DVI DVI December 2003
14 DVI DDWG 98 8 DVI Rev Download HDCP Rev EIA EIA/CEA I_Informational_Doc_1_04_02.pdf DDWG Test & Measurement Guide Ver HDMI HDMI December 2003 Page 14
15 DVI(Digital Visual Interface) DVI1.0 Digital Display Working Group Intel PC Video TMDS 2 (Dual Link) Molex Royalty-Free HDCP(High-bandwidth Digital Content Protection) CEA(EIA/CEA-861) (CEA=Consumer Electronics Association ) DVI1.0 DTV Royalty fair & reasonable Thomson, Philips HMDI(High Definition Multimedia Interface) Philips Silicon Image Thomson 7 EIA/CEA-861 TMDS(Transition-Minimized Differential Signaling) HDCP December 2003 Page 15
16 DVI Ser Des Ser Des Ser Des Ser Des 10 X10 X10 X10 X10 PLL PLL PLL PLL Incoherent Coherent December 2003 Page 16
17 DVI PLL DVI PLL 2 PLL December 2003 Page 17
18 HDMI HDMI PLL H( ) 1/(1+j / 0 ) 0 =2 F 0 F 0 =4.0MHz December 2003 Page 18
19 DVI 3 C(Compliance) F(Function) I(Interoperability) December 2003 Page 19
20 DVI December 2003
21 DVI(Digital Visual Interface) DVI R G B 1 DDWG R G Transmitter B Receiver Clk December 2003 Page 21
22 TMDS TMDS December 2003 Page 22
23 DVI DVI December 2003 Page 23
24 DVI RGB1 2 December 2003 Page 24
25 PC CE December 2003 Page 25
26 December 2003 Page 26
27 December 2003 Page 27
28 DVI DVI December 2003
29 December 2003 Page 29
30 (TP2) TP2 December 2003 Page 30
31 December 2003 Page 31
32 December 2003 Page 32
33 DDWG (TPA-R) PLL PLL EEPROM( ) DVI December 2003 Page 33
34 Test & Measurement Guide H(s)=1/(s + 40us) December 2003 Page 34
35 DVI AVcc Data+ R T R T Clk- Data- Clk+ PLL PLL PLL Clk 2.5 December 2003 Page 35
36 Intra-Pair 65MHz 1.5m December 2003 Page 36
37 UXGA(162MHz) TPA-R PLL OD 2.5 December 2003 Page 37
38 1 UXGA(162MHz) TPA-R December 2003 Page 38
39 SDA PLL December 2003 Page 39
40 SDA PLL 4 1 December 2003 Page 40
41 TPA2.0 PLL PLL TPA-P TPA-R HDMI ) December 2003 Page 41
42 UXGA(162MHz) TPA2.0-R PLL OD ( 10 1) (8 )10 December 2003 Page 42
43 UXGA(162MHz) TPA2.0-R PLL 10 1 December 2003 Page 43
44 December 2003
45 SDA6000A, SDA5000A, SDA3000A 4 2.7Gbps 2.5GHz December 2003 Page 45
46 infiniband SDA 25M 2.7G fibre channel DVI/HDMI Rapid IO IEEE 1394b serial ATA gigabit ethernet 100Mb/s 1.25Gbps SDA 2.5Gb/s PCI Express 5Gb/s December 2003 Page 46
47 December 2003 Page 47
48 CDR December 2003 Page 48
49 December 2003 Page 49
50 December 2003 Page 50
51 CRU CRU ( ) CRU ( ) December 2003 Page 51
52 SMA December 2003 Page 52
53 -> -> -> -> December 2003 Page 53
54 50ohm SG 50ohm Probe December 2003 Page 54
55 L1 C1 R L2 December 2003 Page 55
56 Input Impedance? 0 Frequency December 2003 Page 56
57 December 2003 Page 57
58 WaveLink Body Module WaveLink Probe Body Probe Module Body Module December 2003 Page 58
59 WaveLink December 2003 Page 59
60 2:1 D600AT, D300AT have +-2V input range with /2 370 mv LVDS 10% 37 mv,10:1 3.7 mv WaveLink 18.5 mv December 2003 Page 60
61 Probe Splitter DX00AT Probe Module December 2003 Page 61
62 ProLink ProBus December 2003 Page 62
63 WaveLink D600/D600AT WaveLink D600 Frequency Response System Amplitude (db) Scope Amplitude (db) Amplitude (db) Frequency (MHz) December 2003 Page 63
64 D600AT, D300AT December 2003 Page 64
65 TwinTip 45 0 mm 3 mm December 2003 Page 65
66 / (WaveLink ) December 2003 Page 66
67 DX00AT TwinTips SP-ATT December 2003 Page 67
68 Spice December 2003
69 December 2003 Page 69
70 Spice Rout 50ohm TL1 50ohm TL2 25ohm TL3 50ohm V1 1.5ns 1.5ns 0.3ns R1 50ohm December 2003 Page 70
71 Spice V1 1 0 PWL(0,0 500ps,4V 100ns,4V) Rout T Z0=50 TD=1.5ns T Z0=25 TD=0.3ns T Z0=50 TD=1.5ns R December 2003 Page 71
72 Spice December 2003 Page 72
73 Spice December 2003 Page 73
74 Spice Spice December 2003 Page 74
75 IC Rout 50ohm TL1 50ohm L1 8nH V1 50ps C1 6pF RL 50ohm December 2003 Page 75
76 Spice December 2003 Page 76
77 Spice December 2003 Page 77
78 Spice Spice December 2003 Page 78
79 3.125Gbps 3.125Gbps December 2003 Page 79
80 3.125Gbps December 2003 Page 80
81 3.125Gbps December 2003 Page 81
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