LSI間を高速･高密度･低消費電力で接続するシリコンフォトニクス光トランシーバー

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みそらじゅふく
5 years ago
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1 LSI Silicon Photonics Optical Transceiver for High-speed, High-density and Low Power Consumption LSI Interconnect 早川明憲江部広治 Chen Yanfei 森俊彦あらまし CPU CPU CPU Si Si Si Abstract The next-generation servers and supercomputers with advanced functions and low-power consumption require not only CPUs with an enhanced processing capability, but also signal transmission technology that connects CPUs with other CPUs or memories at high density and low power consumption. The conventional signal transmission technologies are becoming outdated and in the near future they will not be able to provide the signal transmission bands required by the CPUs used in high-end servers and supercomputers. Optical transmission technology makes wide-bandwidth, long-distance transmissions possible, and thus, there are high expectations that it will be a key technology. Especially, silicon (Si) photonics technology has been attracting much attention in recent years because it is considered to be promising for reducing the size, increasing the density and lowering power consumption of optical transceivers. This paper explains Fujitsu and Fujitsu Laboratories small, energy-efficient Si photonics optical transceiver technology. The key factors for realizing a small, high-density optical transceiver with reduced energy consumption involve enhancing optical devices and driver circuits, and optimizing the mounting structure to supply good power and signals. We proposed a novel configuration of silicon photonic transceiver utilizing a bridge structure that enabled highdensity integration without wiring, and we optimized the design of optical/electronic devices based on this structure. We achieved the world s best performance in terms of high signal density and low energy consumption, and hence it validated the technology. FUJITSU. 66, 5, p ,

2 まえがき CPU 1 CPU CPU CPU CPU 図 -1 a b Board-edge On-board 1 CPU 2 CPU Onpackage -1 c 1 2 CPU mm On-package Si CPU -マザーボード間端子数制約電気 / 光変換配線による損失光信号マザーボード高速電気信号 (a)board-edge 型 CPU - マザーボード間端子数制約電気 / 光変換光信号マザーボード高速電気信号 (b)on-board 型 CPU 10~20 mm 電気 / 光変換高速電気信号光信号マザーボード (c)on-package 型 FUJITSU. 66, 5 09, 2015

フォトニクスチップ (a) ブリッジ実装構造概略図 * 変調器およびPDはSiフォトニクスチップ上に形成電子回路チップ 150 µm ピッチバンプ電子回路素子 50 µm ピッチバンプ光変調器 /PD ドライバ 6Ch TIA 6Ch 変調器

3 nm Si 1 2 Si 28 nm CMOS On-package25 Gbps 6 Channel Ch On-package 型光インタコネクト On-package On-package CPU 図 -2 a 3 On-package 1 PhotoDetector PD Si 2PD TransImpedance Amplifier TIA 3 Si Si 150 µm ピッチバンプ 50 µm ピッチバンプ CPU 電子回路チップ ( ドライバ /TIA) 光ファイバー Si フォトニクスチップ (a) ブリッジ実装構造概略図 * 変調器およびPDはSiフォトニクスチップ上に形成電子回路チップ 150 µm ピッチバンプ電子回路素子 50 µm ピッチバンプ光変調器 /PD ドライバ 6Ch TIA 6Ch 変調器 6Ch PD 6Ch 4.0 mm Si フォトニクスチップ Si フォトニクスチップ 6.0 mm (b) ブリッジ実装部断面写真 (c) ブリッジ実装後素子上面写真図 -2 ブリッジ実装 FUJITSU. 66, 5 09,

1 mm 10 m Si Si Si -2 a -2 b Si 150 m Si 50 m 30 m -2 c 4.0 6.0 mm 24 mm 2 25 Gbps 6Ch 6.

4 1 mm 10 m Si Si Si -2 a -2 b Si 150 m Si 50 m 30 m -2 c mm 24 mm 2 25 Gbps 6Ch 6.25 Gbps/mm 2 要素技術 Mach-Zehnder MZ MZ 100 m mmv L 1 1 V cm 4 Si Si µm 300 µm 出力ポート 30 µm Si 導波路 n 電極 p i n i p 入力ポート位相変調部 p 電極 (a)p-i-n 型リング光変調器 150 µm n 電極テーパSi 導波路吸収層 300 µm 30 µm p-si p 電極 (b) 導波路集積型 p-i-n 型 Ge-PD -3 Si p-i-n 2 V L V cm 5 MZ p-n 6 p-i-n p-i-n 図 -3 a p-i-n 30 m m p-i-n Germanium Ge 7 Ge Si 2 p n i 22 FUJITSU. 66, 5 09, 2015

Si PD PD PD TIA PD TIA PD PD Ge 30 m 10 m 1470 1570 nm 0.

25 dbm 65 db 20 GHz3 db 25 Gbps 光信号送受信特性 Si 25 Gbps 25 Gbps 入力電気信号 ~10 mm ドライバ TIA

5 db 10-3 10-4 (b)25 Gbps 変調信号光波形 ( 光送信機出力波形 ) 符号誤り率 10-5 10-6 10-7 10-8 160 mv

5 Si PD PD PD TIA PD TIA PD PD Ge 30 m 10 m nm 0.8 A/W20 GHz p-i-n Ge-PD -3 b PD Ge 30 m m PD 0.8 A/W db7.25 dbm 65 db 20 GHz3 db 25 Gbps 光信号送受信特性 Si 25 Gbps 25 Gbps 入力電気信号 ~10 mm ドライバ TIA 変調器 PD 1.55 µm CW 光 25 Gbps 変調信号光 25 Gbps 出力電気信号 25 Gbps 変調信号光 (a) 光送受信機評価系概略図 6.5 db (b)25 Gbps 変調信号光波形 ( 光送信機出力波形 ) 符号誤り率 mv 入力光強度 (dbm) (c)25 Gbps 出力電気信号 ( 光受信機出力波形 ) (d) 符号誤り率の入力光強度依存性 -4 FUJITSU. 66, 5 09,

6 -1 Si Buckwalter JSSC nm SOI Rosenberg IPC nm SOI Takemoto ISSCC nm CMOS Yashiki OFC nm CMOS 28 nm CMOS Gbps V 0.3/ 1.2/ / / /1.8 p-n p-n p-n MZ p-i-n db mw/gbps V / / dbm mw/gbps 図 -4 a 1.55 m 25 Gbps CPU 10 mm Continuous Wave CW 25 Gbps 25 Gbps 25 Gbps PD TIA 25 Gbps Si 3-4 b 6.5 db -4 c 160 mv d c PD TIA9.1 dbm 73 mw 50 mw 2.9 mw/gbps 2.0 mw/ Gbps 8 表 Si むすび On-package Si CPU 24 FUJITSU. 66, 5 09, 2015

7 LSI p-i-n p-i-n Ge-PD mm 25 Gbps 6Ch 6.25 Gbps/mm 2 25 Gbps 9.1 dbm 2.9 mw/gbps 2.0 mw/gbps Ch NEDO PETRA 参考文献 1 X. Zheng et al. Si photonics technology for future optical interconnection. Communications and Photonics Conference and Exhibition 2011 ACP Asia p R. Soref The Past, Present, and Future of Silicon Photonics IEEE Journal of Selected Topics in Quantum Electronics 12 6 p A. Hayakawa et al. A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects OFC2015 Th1G X. Tu et al. 50-Gb/s silicon optical modulator with traveling-wave electrodes Optics Express Vol.21 No.10 p T. Baba et al. 50-Gb/s ring-resonator-based silicon modulator Optics Express Vol.21 No.10 p J. C. Rosenberg et al. A 25 Gbps silicon microring modulator based on an interleaved junction Optics Express Vol.20 No.24 p J. Fujikata et al. Si Waveguide-Integrated Metal- Semiconductor-Metal and p-i-n-type Ge Photodiodes Using Si-Capping Layer. Jpn. J. of Appl. Phys., 52, 04CG10 p Y. Chen et al. A 25Gbps Hybrid Integrated Silicon Photonic Transceiver in 28nm CMOS and SOI. ISSCC Dig. Tech. Paper p J. F. Buckwalter et al. A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Proess IEEE Journal of Solid-State Circuits 47 6 p J. C. Rosenberg et al. A Monolithic Microring Transmitter in 90 nm SOI CMOS Technology IEEE Photonics Conference p T. Takemoto et al. A 4 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm High-Sensitivity Optical Receiver Based on 65nm CMOS for Board-to-Board Interconnects. ISSCC Dig. Tech. Paper p K. Yashiki et al. 5 mw/gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF. OFC2015 Th1G FUJITSU. 66, 5 09,

8 著者紹介早川明憲 ( はやかわあきのり ) Chen Yanfei 江部広治 ( えべひろじ ) 森俊彦 ( もりとしひこ ) 26 FUJITSU. 66, 5 09, 2015

CPUパッケージに搭載可能なTbps級シリコンフォトニクス光送信器技術

CPUパッケージに搭載可能なTbps級シリコンフォトニクス光送信器技術 CPU Tbps Silicon Photonics Optical Transmitter Technology for Tbps-class I/O Co-packaged with CPU 田中信介秋山知之関口茂昭森戸健あらまし HPC High Performance Computing CPU Tbps I/O I/O I/O Si I/O CPU Tbps I/O I/OSi I/O