チップ間広帯域信号伝送を実現する2.1次元有機パッケージ技術

Size: px

Start display at page:

Download "チップ間広帯域信号伝送を実現する2.1次元有機パッケージ技術"

まいかひきぎ
5 years ago
Views:

1 D Organic Package Technology to Realize Die-to-Die Connection for Wide-Band Signal Transmission あらまし D 2.5D D 2.1D2.1D 2.5D Line/Space 2/2 m 2.1D i-thop integrated-thin film High density Organic Package TCB Thermo-Compression Bonding 40 m 2.1D Abstract A 2.5D assembly structure has been attracting attention because it places wide-band memories next to a logic chip using a silicon interposer. Its purpose is to perform a large volume of signal transmissions by expanding the memory bandwidth; therefore, a die-to-die connection on a package has been required. Furthermore, in contrast to the 2.5D structure, a 2.1D structure that integrates interposer functionality in an organic substrate has been proposed. This paper describes the 2.1D organic package that is being developed by SHINKO ELECTRIC INDUSTRIES CO., LTD. This 2.1D package can be created just by adding the functions of an organic substrate to a 2.5D structure, and it was formed by creating a super-high-density multi-wiring layer on an organic package. We have produced a 2.1D organic package (i-thop: integrated-thin film High density Organic Package) with a wiring density of Line/Space=2/2 m by applying a thin-film process to the surface layer of a conventional build-up package. At the same time, we achieved multi-chip assembly with a minimum bump pitch of 40 m by using thermo-compression bonding (TCB) technology for a narrow-pitch flip-chip assembly. And we assembled a test chip on the created 2.1D package and evaluated its reliability. In addition, we simulated the signal transmission properties of the thinfilm wiring, and confirmed that there is no practical issue. FUJITSU. 68, 1, p ,

2 2.1 まえがき SoC System on Chip SiP System in 1 2 Package Wide I/O 3 TSV Through Silicon Via HBM High Bandwidth Memory HBM CPU/GPU CPU D 図 -1 a TSV 100 m 4 2.5D -1 b D TSV 2.1D MCP Multi Chip PackageMCP HBM 55 m 2,000 Line/Space L/S 2/2 m 構造と製造プロセス 2.1D -1 b シリコンインターポーザ半導体チップ半導体チップ薄膜層 ( インターポーザ部 ) ビルドアップ基板ビルドアップ基板層 (a)2.5d 構造 (b)2.1d 構造 ( i-thop) D 構造 2.1D 構造 16 FUJITSU. 68, 1 01, 2017

3 D 2.1Di-THOP integrated-thin film High density Organic Package i-thop 図 -2 CMP Chemical Mechanical Polishing Ti/Cu / 2 m 5 m 10 m 25 m Ti/Cu 25 m40 m i-thop i-thop 図 -3 a 45 mm HBMHBM 800 m 4b c CMP L/S 3/3 m d L/S 2/2 m i-thop 40 m L/S 2/2 m L/S 3/3 m ビルドアップ基板薄膜層多層化 CMP フリップチップパッド形成スパッタリングレジストパターニングソルダーレジスト形成電解銅めっき, シード層エッチング表面処理感光性絶縁層 -2 FUJITSU. 68, 1 01,

125 1,000 10 m 3 10 260 i-thop 45 mm 80 m

4 2.1 ロジックチップエリア基板フリップチップパッド絶縁層 HBM エリア配線ビアビルドアップ基板層 (a) パッケージ外観 (b) 薄膜層断面ランドランド配線配線 (c)l/s=3/3 µm 配線 (d)l/s=2/2 µm 配線 -3 i-thop 外観 10 m 25 m 2 m 5 m i-thop 1 bias-hast V 96 2 m3 m 5 m Thermal Shock , m i-thop 45 mm 80 m 要素技術 i-thop 1 CMP CMP i-thop CMP nm20 nm 3 m 2 18 FUJITSU. 68, 1 01, 2017

Connection C4 TCB Thermo-Compression Bonding TCB NCP Non Conductive Paste CUF Capillary Underfill 6 HBM 4 図 -4 a 20 mm 40 m b HBM 55 m Cu Sn/Ag

5 2.1 i-thop Ti Cu D CTE Coefficient of Thermal Expansion i-thop CTE 60 ppm/ CTE 3 S-S Stress-Strain curve i-thop CTE 実装と信頼性評価 i-thop C4 Controlled Collapse Chip Connection C4 TCB Thermo-Compression Bonding TCB NCP Non Conductive Paste CUF Capillary Underfill 6 HBM 4 図 -4 a 20 mm 40 m b HBM 55 m Cu Sn/Ag / i-thop Ni/Pd/Au / / OSP Organic Solderability Preservative OSP OSP TIM Thermal Interface Materials ロジックチップ Substrate x100 HBM HBM Substrate 40 µm x1, µm x µm 55 µm x100 x1,000 x1,000 HBM 2 か所の接続断面 (a) ロジックチップ部 (b)hbm 部 -4 チップ FUJITSU. 68, 1 01,

2.1 1 30 60 96 245 3 40 125 1,000 110 85 168 150 1,000 2 SAT Scanning Acoustic Transmission

6 , ,000 2 SAT Scanning Acoustic Transmission 配線設計と信号伝送 i-thop 2 m 2.1D 2.5D i-thop 40 m 4 HBM 55 m 6 HBM 図 -5 a b 信号線 #3 信号線 #2 信号線 #1 (a) 配線モデル (b) 配線断面信号線 #3 信号線 #2 信号線 #1 信号周波数 ( データ転送レート ) 0.5 GHz (1 Gbps) 1 GHz (2 Gbps) 2 GHz (4 Gbps) 5 GHz (10 Gbps) (c) シミュレーション結果 -5 シミュレーション 20 FUJITSU. 68, 1 01, 2017

2.1 c HBM 2 Gbps 6 mm 5 N. Shimizu et al. Development of Organic Multi Chip Packaging for High Performance Application. IMAPS 46th p.414-419 2013 6 K. Oi et al. Development of New 2.

7 2.1 c HBM 2 Gbps 6 mm 5 N. Shimizu et al. Development of Organic Multi Chip Packaging for High Performance Application. IMAPS 46th p K. Oi et al. Development of New 2.5D Package with Novel Integrated Organic Interposer Substrate with Ultra-fine Wiring and High Density Bumps. ECTC 64th p むすび HBM 2.1D i-thop L/S 2/2 m 2.1D 100 m 2.1D IoT Internet of Things 著者紹介小山利徳 ( こやまとしのり ) PLP 六川昭雄 ( ろくがわあきお ) PLP 清水規良 ( しみずのりよし ) PLP 参考文献 1 J. Lau et al. Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging SiP IMAPS 45th p P. Dorsey Xilinx stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency. Xilinx White paper. Virtex-7 FPGAs WP380 October27 p C.C. Lee et al. An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer. IEEE 66th p M.J. Wang et al. TSV Technology for 2.5D IC Solution. ECTC 62nd p 大井淳 ( おおいきよし ) FUJITSU. 68, 1 01,

デジタルカメラ用ISP：Milbeaut

デジタルカメラ用ISP：Milbeaut ISP Milbeaut Image Signal Processor: Milbeaut あらまし MilbeautISP Image Signal Processor 20 Mpixel Milbeaut6 MB91696AM MB91696AM Abstract Milbeaut is an image signal processor (ISP) that realizes a digital