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1 Ver.1.04 Reference Document For LCD Module Product No Documenet No 1B3GB02 SPC1B3GB02V104 Version Ver.1.04 REPRO ELECTRONICS CORPORATION Maruwa Building 2F, Sotokanda,Chiyoda-ku,Tokyo Japan TEL: / FAX: SPC1B3GB02V104 1
2 Revision History Version Date by Description Comments /Dec/2006 gyg Initial Version /Dec/2006 rt /Dec/2006 rt /Dec/2006 rt /Jun/2008 Jeffrey Add register description Contents Page 1. General specifications Outline Structure LCD Module Backlight Interface Signals Timing Chart RGB Interface Serial Interface Use LCD Module Data direction Initial code Lcd sleep mode code Lcd Power off code Sub Function Description Register function description...9 SPC1B3GB02V104 1
3 1. General specifications Display format:240 (RGB) 320 Outline dimensions: 2.4 inch Color:262k color (R:6bit,G:6bit,B:6bit) Current LED:typical 20mA Signals:23(Except of Power and GND) Power Signals:Power(+3V)3,Power(+2V)2,GND 5 LED Signals:4 2. Outline Structure 2.1. LCD Module IC1 IC Backlight Fig. 1 LCD outline structure Pin 1, 2 Pin 3, 4 Fig. 2 Backlight structure SPC1B3GB02V104 2
4 2.3. Interface Signals Pin No. Symbol Description I/O 1 GND Ground I 2 *RESET Reset(low active) I 3 GND Ground I 4 VSYNC Vertical synchronizing signal I 5 VEE Power (+3V) I 6 VEE Power (+3V) I 7 VEE Power (+3V) I 8 SDI Serial data input I 9 SCLK Serial clock I 10 GND Ground I 11 VDEN Video data enable signal I 12 VCLK Video data sampling clock I 13 VDD Power logic (+2V) I 14 VDD Power logic (+2V) I 15 *SCS Serial interface chip select(low active) I 16 GND Ground I 17 R5 Red data signal(msb) I 18 R4 Red data signal I 19 R3 Red data signal I 20 R2 Red data signal I 21 R1 Red data signal I 22 R0 Red data signal(lsb) I 23 G5 Green data signal(msb) I 24 G4 Green data signal I 25 G3 Green data signal I 26 G2 Green data signal I 27 G1 Green data signal I 28 G0 Green data signal(lsb) I 29 B5 Blue data signal(msb) I 30 B4 Blue data signal I 31 B3 Blue data signal Backlight Cathode I 32 B2 Blue data signal I 33 B1 Blue data signal I 34 B0 Blue data signal(lsb) I 35 GND Ground I Note: I Input O Output SPC1B3GB02V104 3
5 3. Timing Chart 3.1. RGB Interface B0~B5. Input display data by each terminal of VSYNC, VDEN, VCLK, R0~R5, G0~G5, Fig. 3 RGB timing chart Pin Description Symbol Typical Unit Note VSYNC Cycle tv 334 H Vertical (Frequency) Fv ms synchronizing Front Porch tvf 2 H signal Back Porch tvb 8 H Pulse Width tvp 4 H Display Period tvd 320 H VDEN Cycle td 300 CLK Horizontal (Frequency) Fd 50 us Synchronizing Pulse Width tdp 60 CLK signal Display Period tdd 240 CLK VCLK fclk 6 MHz SPC1B3GB02V104 4
6 3.2. Serial Interface It is possible to set LCD driver register. Specification of register and setting of register value is done by serial interface. This serial interface is composed by 24-bit data or by 32-bit data. Some registers are set by 24-bit data, and some registers are set by 32-bit data. Keep chip select active during transmission of total 24-bit or 32-bit data. SCS SCLK SDI D22 D20 D18 D16 D14 D12 D10 D8 D6 D4 D2 D0 D23 D21 D19 D17 D15 D13 D11 D9 D7 D5 D3 D1 Fig bitdata serial timing chart SCS SCLK SDI D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D8 D6 D4 D2 D0 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D7 D5 D3 D1 4. Use LCD Module Fig bitdata serial timing chart 4.1. Data direction IC1 IC2 Fig. 5 Data direction SPC1B3GB02V104 5
7 4.2. Initial code (1) Power on and Reset (2) Set LCD driver register: LCD_Reg_Set1(0x0070, 0x80); Delay(115); LCD_Reg_Set1(0x007A, 0x01); LCD_Reg_Set1(0x0070, 0xC8); LCD_Reg_Set1(0x00A1, 0x00); LCD_Reg_Set1(0x00A0, 0x00); LCD_Reg_Set1(0x0072, 0xA3); LCD_Reg_Set1(0x0073, 0x04); LCD_Reg_Set1(0x0075, 0x46); LCD_Reg_Set1(0x0076, 0x23); LCD_Reg_Set1(0x0077, 0x08); LCD_Reg_Set1(0x0078, 0x08); LCD_Reg_Set1(0x0079, 0x00); LCD_Reg_Set1(0x007F, 0xF0); LCD_Reg_Set1(0x0071, 0x81); Delay(3); LCD_Reg_Set1(0x000D, 0x20); LCD_Reg_Set1(0x002E, 0x00); LCD_Reg_Set1(0x0011, 0x00); Delay(340); LCD_Reg_Set1(0x0012, 0x00); LCD_Reg_Set1(0x0085, 0x74); LCD_Reg_Set1(0x0021, 0x37); LCD_Reg_Set1(0x0022, 0x02); LCD_Reg_Set1(0x0023, 0x24); LCD_Reg_Set1(0x0024, 0x13); LCD_Reg_Set1(0x0025, 0x0A); LCD_Reg_Set1(0x0026, 0x82); LCD_Reg_Set1(0x0027, 0x01); LCD_Reg_Set1(0x006F, 0x00); LCD_Reg_Set1(0x001E, 0x25); LCD_Reg_Set1(0x001F, 0x59); LCD_Reg_Set2(0x0030, 0x0777); LCD_Reg_Set2(0x0031, 0x0444); LCD_Reg_Set2(0x0032, 0x0555); LCD_Reg_Set2(0x0033, 0x0444); LCD_Reg_Set2(0x0034, 0x0333); LCD_Reg_Set2(0x0035, 0x0333); LCD_Reg_Set2(0x0036, 0x0333); LCD_Reg_Set2(0x0037, 0x0333); LCD_Reg_Set2(0x0038, 0x0444); //11.5ms=115*100us SPC1B3GB02V104 6
8 LCD_Reg_Set2(0x0039, 0x0555); LCD_Reg_Set2(0x003A, 0x0666); LCD_Reg_Set2(0x003B, 0x0666); LCD_Reg_Set2(0x003C, 0x0777); LCD_Reg_Set2(0x003D, 0x0777); LCD_Reg_Set2(0x003E, 0x0777); LCD_Reg_Set2(0x003F, 0x0777); LCD_Reg_Set2(0x0040, 0x0777); LCD_Reg_Set2(0x0041, 0x0777); LCD_Reg_Set2(0x0042, 0x0777); LCD_Reg_Set2(0x0043, 0x0777); LCD_Reg_Set2(0x0044, 0x0777); LCD_Reg_Set2(0x0045, 0x0777); LCD_Reg_Set2(0x0046, 0x0777); LCD_Reg_Set2(0x0047, 0x0777); LCD_Reg_Set2(0x0048, 0x0777); LCD_Reg_Set2(0x0049, 0x0777); LCD_Reg_Set2(0x004A, 0x0777); LCD_Reg_Set2(0x004B, 0x0777); LCD_Reg_Set2(0x004C, 0x0777); LCD_Reg_Set2(0x004D, 0x0666); LCD_Reg_Set2(0x004E, 0x0666); LCD_Reg_Set2(0x004F, 0x0666); LCD_Reg_Set1(0x0014, 0x00); LCD_Reg_Set1(0x0000, 0x04); LCD_Reg_Set1(0x0001, 0x07); LCD_Reg_Set1(0x0002, 0x00); LCD_Reg_Set2(0x0003, 0x0000); LCD_Reg_Set1(0x0004, 0xEF); LCD_Reg_Set2(0x0005, 0x013F); LCD_Reg_Set1(0x0006, 0xFF); LCD_Reg_Set2(0x0007, 0x01FF); LCD_Reg_Set1(0x0008, 0xFF); LCD_Reg_Set2(0x0009, 0x01FF); LCD_Reg_Set1(0x000A, 0x00); LCD_Reg_Set1(0x000B, 0x00); LCD_Reg_Set1(0x000C, 0x00); LCD_Reg_Set1(0x0014, 0x00); LCD_Reg_Set2(0x0015, 0x0000); LCD_Reg_Set2(0x0016, 0x0000); LCD_Reg_Set2(0x0017, 0x01FF); LCD_Reg_Set2(0x0018, 0x01FF); LCD_Reg_Set1(0x0013, 0x00); LCD_Reg_Set2(0x0019, 0x01FF); SPC1B3GB02V104 7
9 LCD_Reg_Set2(0x001B, 0x01FF); LCD_Reg_Set2(0x001C, 0x01FF); LCD_Reg_Set2(0x001A, 0x01FF); LCD_Reg_Set1(0x001D, 0x0E); LCD_Reg_Set1(0x000D, 0x00); Delay(4); //start output of CLK,HSY,VSY now LCD_Reg_Set1(0x0011, 0x80); Delay(400); LCD_Reg_Set1(0x002E, 0x0D);//0x0D LCD_Reg_Set1(0x001E, 0x29); LCD_Reg_Set1(0x0011, 0xC0); LCD_Reg_Set1(0x000D, 0x24); Delay(200); LCD_Reg_Set1(0x0010, 0x02); Delay(26); // Start to send RGB display data Lcd sleep mode code LCD_Reg_Set1(0x0011, 0x40); Delay(390); LCD_Reg_Set1(0x001E, 0x25); LCD_Reg_Set1(0x0011, 0x00); LCD_Reg_Set1(0x002E, 0x00); Delay(130); LCD_Reg_Set1(0x000D, 0x20); LCD_Reg_Set1(0x0010, 0x04); Delay(390); LCD_Reg_Set1(0x0071, 0x09); Delay(160); LCD_Reg_Set1(0x0071, 0x05); LCD_Reg_Set1(0x0071, 0x71); LCD_Reg_Set1(0x007A, 0x01); LCD_Reg_Set1(0x00A0, 0x55); LCD_Reg_Set1(0x00A1, 0xAA); LCD_Reg_Set1(0x0070, 0x00); 4.4. Lcd Power off code LCD_Reg_Set1(0x0011, 0x40); Delay(390); LCD_Reg_Set1(0x001E, 0x25); LCD_Reg_Set1(0x0011, 0x00); LCD_Reg_Set1(0x002E, 0x00); Delay(100); LCD_Reg_Set1(0x000D, 0x20); SPC1B3GB02V104 8
10 LCD_Reg_Set1(0x0010, 0x04); Delay(398); LCD_Reg_Set1(0x0071, 0x09); Delay(160); LCD_Reg_Set1(0x0071, 0x09); LCD_Reg_Set1(0x0071, 0x71); LCD_Reg_Set1(0x007A, 0x01); LCD_Reg_Set1(0x00A0, 0xAA); LCD_Reg_Set1(0x00A1, 0xAA); LCD_Reg_Set1(0x0070, 0x00); Delay(20000); LCD_Reg_Set1(0x0070, 0x80); Delay(53); LCD_Reg_Set1(0x007A, 0x01); LCD_Reg_Set1(0x0071, 0x0A); Delay(160); LCD_Reg_Set1(0x0071, 0x71); LCD_Reg_Set1(0x00A0, 0xAA); LCD_Reg_Set1(0x00A1, 0xAA); LCD_Reg_Set1(0x0070, 0x00); 4.5. Sub Function Description (1) LCD_Reg_Set1(unsigned int reg, unsigned int data) Function: Set the LCD driver register. Para1: reg---- Select the register through serial interface. Para2: data----the set value for register through serial interface, the data should 8 bits. (2) LCD_Reg_Set2(unsigned int reg, unsigned int data) Function: Set the LCD driver register. Para1: reg---- Select the register through serial interface. Para2: data----the set value for register through serial interface, the data should 16 bits. (3) Delay (unsigned int time) Function: Delay time*100us. 5. Register function description (1) Display control (R0010h) R/W IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W DEN 0 DEN: 1 the display turns on, 0 the display turns off. SPC1B3GB02V104 9
11 (2) Entry Mode (R0000h) R/W IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W GSDC 0 SSDC 0 0 SSDC: SSDC is a bit which selects the source scanning direction. If this bit is set, the LR output pin is changed and the display is reversed (right and left). LR signal changes by frame synchronization (VSYNC synchronization). If 1 is set in SSDC, the display will be reversed (right and left). Therefore, in accordance with the display reversal, the analog video output of 4chxRGB is reversed in bit order. At this time, the polarity of SCK and SCKB is reversed. SSDC Description 0 LR output is high 1 LR output is low GSDC: GSDC is a bit to select the direction of gate scanning. If this bit is set, the UD output pin is changed and the display is reversed (up and down).ud signal changes by frame synchronization (VSYNC synchronization). GSDC Description 0 UD output is low 1 UD output is high Select the direction of the source driver channel in pixel unit by setting GSDC and SSDC. ITEM GSDC=1 GSDC=0 SSDC=1 SSDC=0 SPC1B3GB02V104 10
12 Ver1.04 SPC1B3GB02V104 CCopyright Repro Electronics Co. All Rights Reserved.
13 . PRODUCT A FF02S65SV FF02S55SV FF02S45SV FF02S35SV FF02S33SV FF02S31SV FF02S29SV FF02S27SV FF02S25SV FF02S17SV FF02S15SV JAE PMK Div. Proprietary. Copyright 2006 Japan Aviation Electronics Industry, Ltd. SPC1B3GB02V104 CCopyright Repro Electronics Co. All Rights Reserved.
14 . D JAE PMK Div. Proprietary. Copyright 2006 Japan Aviation Electronics Industry, Ltd. SPC1B3GB02V104 CCopyright Repro Electronics Co. All Rights Reserved.
15 No. D±0.1 (1) 2.5±0.15 (0.5) No. 0.5 B A±0.15 (C:FPC (0.15) (0.15) (1.6) 0.9±0.1() HRS (1.3) 2.15± MAX 0.15MAX 3 S 0.15G G ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** Reference Document for 1B3GB02 LCD Module SPC1B3GB02V104CCopyright Repro Electronics Co. All Right Reserverd.
16 0.3± ± ± H H (0.15) (0.15)(0.15) (0.15) (3) (2.5) (A) J±0.1 K± ± ±0.05 (0.2) (0.05) (X) 0.2± MIN() 0.3± MIN() 2-R ±0.07 B± ±0.03 L± ±0.03(FPC) 0.3±0.03(FFC) 2.5±0.3() B B Reference Document for 1B3GB02 LCD Module SPC1B3GB02V104CCopyright Repro Electronics Co. All Right Reserverd.
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