LM Channel 42-Bit Color Scanner Analog Front End (jp)

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1 LM9822 LM Channel 42-Bit Color Scanner Analog Front End Literature Number: JAJS680

2 LM LM9822 AFE CIS CCD CDS / LM MHz ADC 600 / CCD CDS CCD CIS TTL/CMOS 14 6MHz 5V 5% I/O 3.3V 10% 5V 5% 375mW MFP FAX LM Notes: TRI-STATE National Semiconductor Corporation Printed in Japan NSJ 9/2000

3V 10% 5V 5% 375mW MFP FAX LM9822 3 42 Notes: 1-26 2-1000

3 LM9822 LM9822

4 Note 1 2 V + V A V D GND AGND DGND 6.5V 0.3V V + 0.3V Note 3 25mA Note 3 50mA T A 25 Note 4 ESD Note V 450V 10 Note Note 1 2 T MIN 0 T A T MAX 70 V A 4.75V 5.25V V D 3.0V 5.25V V D V A 100mV OS R OS G OS B 0.05V V A 0.05V SCLK SDI SEN MCLK VSMP CLMP 0.05V V D 0.05V LM9822 AGND DGND 0V V A 5.0V DC V D V DC f MCLK 12MHz LSB A/D LSB T A T J T MIN T MAX T A T J 25 Note

T A T MAX 70 V A 4.75V 5.25V V D 3.0V 5.25V V D V A 100mV OS R OS G OS B 0.05V V A 0.

5 LM9822 AGND DGND 0V V A 5.0V DC V D V DC f MCLK 12MHz LSB A/D LSB T A T J T MIN T MAX T A T J 25 Note DC AGND DGND 0V V A 5.0V DC V D V DC f MCLK 12MHz T A T J T MIN T MAX T A T J 25 Note 7 8

A T J 25 Note 7 8 12 16 DC AGND DGND 0V V A 5.

6 AC AGND DGND 0V V A 5.0V DC V D V DC f MCLK 12MHz T A T J T MIN T MAX T A T J 25 Note 7 8 LM9822 Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 GND AGND DGND 0V V IN V IN GNDV IN V A V D 25mA 50mA 25mA 2 T Jmax θ JA T A P D T Jmax T A /θ JA T Jmax 150M28B SOIC θ JA 60 /W ESD 100pF1.5kΩ 220pF 0Ω AN OS V A AGND LM9822 Note 8 V A V D V A V D 5.0V V A V D

4 Note 5 Note 6 Note 7 GND AGND DGND 0V V IN V IN GNDV IN V A V D 25mA 50mA 25mA 2 T Jmax θ

7 LM9822 Note 9 Typical T J T A 25f MCLK 12MHz Note 10 AOQL Note 11 LSB AFE Note 12 Note 13 PGA PGA V --- V G X = = X G G 0 ( ) Note 14 INL DNL CDS DOE b b OS 1 Note 15 IDD7 D0 I SW 2*Nd*P SW *C L *V D /t MCLK Nd P SW C L V D t MCLK MCLK Nd 8 P SW 0.5 V D 5V I SW 40*C L /t MCLK V D 3.3V I SW 26.4*CL/t MCLK D7 D0 20pF t MCLK 1/ 12MHz 83ns 9.6mA V D LM9822 Note 16 LSB 12

000000b OS 1 Note 15 IDD7 D0 I SW 2*Nd*P SW *C L *V D /t MCLK Nd P SW C L V D t MCLK MCLK Nd 8 P SW 0.

8 Full Channel DNL and INL (Divide by 2, Monochrome Mode, 6 MHz Pixel Rate) LM9822 Note: LM CCD CIS LM DNL 12 INL

9 LM V A 5V0.1µF 10µF AGND 2 ADC 14 MCLK 8 D7 D0 d13 d6 MSB D7 D0 d5 d0 LSB D1 D0 low D7 D3 I/O 3.3V 5.0V 0.1µF10µF DGND DC OS V REF+ V REFMID V REF 0.1µF AGND ADC MCLK 1/2 MCLK 12MHz VSMP MCLK high MCLK MCLK 1 4 CDSREF CDS VSMP VSMP MCLK Diagram 1 6 VSMP Note: VSMP MCLK 9 11 Diagram SDI SCLK SCLK 1t MCLK SCLK SDO SEN low SCLK 8 SEN low MSB 8 / 48 MSBSDI SCLK / 0 / 1 SDO SEN low SEN low SDI SEN high SDI 13/ SEN lowlow SEN 3MCLK high CLMP VSMP MCLK high 3OS V CLAMP V CLAMP VREF+ VREF 0 Bit 4

1µF AGND ADC MCLK 1/2 MCLK 12MHz VSMP MCLK high MCLK MCLK 1 4 CDSREF CDS VSMP VSMP MCLK Diagram 1 6 VSMP Note: VSMP MCLK 9 11

10 LM9822 Diagram 1: Divide by 6 Color Mode Sample and Data Output Timing Diagram 2: Divide by 6 Monochrome Mode Sample and Data Output Timing (Green Input shown) Diagram 3: Divide by 8 Color Mode Sample and Data Output Timing

11 LM9822 Diagram 4: Divide by 8 Monochrome Mode Sample and Data Output Timing (Green Input Shown) Diagram 5: Divide by 3 Monochrome Mode Sample and Data Output Timing (Green Input shown) Diagram 6: Divide by 2 Monochrome Mode Sample and Data Output Timing (Green Input shown)

Sample and Data Output Timing (Green Input shown) Diagram 6: Divide

12 LM9822 Diagram 7: Programmable Reference Sample Timing Diagram 8: Clamp Timing With SMPCL = 0 Diagram 9: Clamp Timing With SMPCL = 1 Diagram 10: Configuration Register Serial Write Timing Diagram 11: Configuration Register Serial Read Timing

Timing With SMPCL = 1 Diagram 10: Configuration Register

13 LM9822 Diagram 12: Serial Input and Output Timing Diagram 13: MCLK, VSMP and CLMP Input Timing and Data Output Timing

14 Table 1: LM9822

15 LM9822 Table 2:

16 Table 2: LM9822

17 LM9822 Table 2:

18 1.0 LM9822 AFE CCD CIS 14-3 / LM9822 Figure 1 ø1 low high 4 C1 C1 V RESIDUAL OS 3 4 OS V RESIDUAL V SIGNAL V RESIDUAL V RESIDUAL V SIGNAL 3.0 CIS CDS LM9822 CIS CIS Figure 3 2 CCD LM9822 Figure 1: LM9822 in Basic Color Scanner 2.0 CDS LM9822 CDS CIS Figure 2 CCD Figure 3: CIS LM9822 CIS CDS 0 B5 1 V REF+ V REF 0 Bit 4 1V REF 0 V REF+ Figure 2: CDS 4.0 x3 x V/V 5 1V/V x3 DAC DAC PGAPGA0.93V/ V 3V/V dB 5 x3 PGA 0.93V/V 9.0V/V0.6 19dB ADC PGA C1CCD Q2 CCD Q1 2 5 C1Q1 OSQ1 3OS C1 V RESIDUAL V RESIDUAL Q1 Q1 ON PGA B4 0 1: PGA x3 PGA 3

0 CDS LM9822 CDS CIS Figure 2 CCD Figure 3: CIS LM9822 CIS CDS 0 B5 1 V REF+ V REF 0 Bit 4 1V REF 0 V REF+ Figure 2: CDS 4.

19 LM DAC DAC LM9822 DC 5.1 DAC ADC PGA 1V/V DAC LSB 20 ADC LSB 590 ADC LSB DAC 6.0 LM9822 AC DC CLMP CLMP VSMPMCLKhigh 3 OS V REF+ V REF OS V REF 0OS V REF+ V DAC = 9.75mV B4 B0 2: DAC 12 = t20lsbs B4 B0 PGA 3: ADC t B5 PGA DAC PGA 5.1 Figure 4 LM V IN LM9822 V OS1 V OS2 V OS3 DAC V DAC G B G PGA C CAFE 1 12 LSB C 2048 /V 4096 /2V C 6.1 LM9822 5V DC CCD5V DC C CLAMP LM9822 AC LM9822 OS OS V REF+ V REF CDS 0.1V 1 LM9822 CDS CIS Figure 4: Internal Offset Model D OUT = (((V IN + V OS1 )G B + V DAC + V OS2 )G PGA + V OS3 )C 4: 5LM9822 D OUT = (V IN G B + V DAC )G PGA C 5: Figure 5: Input Circuitry LM9822 CDSLM9822 CDS LM nA CIS CDS LM9822 1/ f sample *C S f sample C S 2pF

1 Figure 4 LM9822 4 V IN LM9822 V OS1 V OS2 V OS3 DAC V DAC G B G PGA C CAFE 1 12 LSB C 2048 /V 4096 /2V C 6.

20 6.1.1 CDS OS f VSMP A V 6: CDS CLMP VSMP MCLK high SMPCL 0 SMPCL 1 LM9822 1/2 CLAMP high 50% 1 LM9822 OS25nA2700 2MHz t VSMP 500ns 0.1V 12: 1 7: CDS C CLAMP MIN CIS CDS LM9822 OS 8: CIS V SAT CIS OS C SAMP LM9822 2pF % f VSMP 2MHz t CLAMP 4.5µs SMPCL SMPLC 0 Figure 8 SMPLC 1 Figure : 1 C CLAMP MAX V 9: CIS C CLAMP MIN C SAMP 2pF V SAT 2V LM V 10: CIS C CLAMP MIN t CLAMP 1 R CLAMP CCD LM Ω t CLAMP 4.5µs 1500Ω 5V 0.1V 5/ C CLAMP MAX CDS CIS DC LM LSB 2V/10242mV 2700 C CLAMP MIN 11: CIS C CLAMP MIN 14: C CLAMP MAX C CLAMP C CLAMP MAX C CLAMP MAX C CLAMP MIN C CLAMP MIN

5µs SMPCL SMPLC 0 Figure 8 SMPLC 1 Figure 9 1 1 13: 1 C CLAMP MAX V 9: CIS C CLAMP MIN C SAMP 2pF V SAT 2V LM9822 9 V 10: CIS C CLAMP MIN t CLAMP 1 R CLAMP

21 LM : 0.01µF : 0.01µF 14 1 LM9822 CDS 0.01µF C CLAMP MIN LM9822 CIS CIS CCD R CLAMP LM Ω R CLAMP 7.0 LM9822 V A 5V LM µF V A 10µF V D 3.3V 5.0V 0.1µF 10µF V D DGND V D V A V D V A 5.0V 1 LM9822 OS V A AGND LM9822 SEN SCLK SDI SDO MCLK SEN MCLK SDI SDI SDOSEN 13 SD013 SCLK SEN low Table 2: 9.1 I/O B7 Bit DOEBit 6 Bit 6 MCLK 0 MCLK D7 D0 Diagram LM CDS Bit 5 CDS Bit 5 LM9822 CDSCCD CIS 9.4 Bit 4 LM9822 CDS Bit 40CCD 1 CIS 1 V REF

22 0 V REF+ 1 V REF 9.5 SMPCL Bit 3 SMPCL 0 CDS 1 MCLK Diagram 8 1 CDS Diagram 9 CDSREF 9.6 CDSREF Bit 2 Bit 1 CDSREF CDS CCD Diagram 7 CDS CDSREF CDSREF CDSREF 0 D2 6 D0 D1 0 Latency DOE DOE 0 MCLK DOE 1 MCLK Diagram CLMP CLMP CCD CIS LM9822 MCLK CLMP VSMP high CLMP SMPCL SMPCL 0 CDS 1 MCLK SMPCL 1 Diagram 8 9 CLMP highlow CLMP LM MCLK VSMP VSMP MCLK 9.7 PD Bit 0 LM9822 1% 10.0 LM9822 LM Diagram MCLK MCLK VSMP CLMP low 3MCLK VSMP CLMP high 10.2 MCLK VSMP 14 ADC 8 13 D7 6 D0 65 D7 : /8 /6 : /8 /6 /3 /2 MCLK/VSMP VSMP MCLK 3 low VSMP MCLK : 1/31/2 VSMP MCLK 3 low 1/2VSMP high VSMP 3 MCLK low LM9822 Figure 6: Timing of Transitions between Divide By Modes

23 LM inches millimeters 8-Pin MSOP Package Order Package Number LMC8101MM or LMC8101MMX NS Package Number MUA08A 1. a b TEL.(03)

24 IMPORTANT NOTICE

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp) ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8 ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV