AD8250 ：ゲイン設定可能（G＝1、2、5、10）な 10MHz、20V/μsのiCMOS®計装アンプ

Transcription

1 G 2 5 MHz 2V/µs icmos AD825 MSOP V DC CMRR 98dB G ppm/.7µv/ G AC.% 65ns 2V/µs khz THD db CMRR 5kHz 8dB 8nV/ Hz G ma IN +IN DGD A A LOGIC AD OUT G = G = 5 AD825 GΩ PGIA A/DADC MHz db THD 65ns.% G.7µV/ ppm/ DC 5kHz 8dB G CMRR DC AD GAIN (db) 5 5 k k k M M M. 2. High Low High Mil Low Digital Performance Cost Voltage Grade Power Gain AD822 AD623 AD628 AD62 AD627 AD823 AD822 AD8553 AD629 AD62 AD825 AD8222 AD52 AD8555 AD822 AD526 AD8556 to G = 2 G = FREQUENCY (Hz) AD62 AD8557 AD825 MSOP REV. REVISION 27 Analog Devices, Inc. All rights reserved MT

2 AD825 /7 Revision : Initial Version

3 AD825 V S 5V V S 5 V V V@T A 25 G R L 2kΩ 2 Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR to 6 Hz with kω Source Imbalance +IN = IN = V to + V G = 8 9 db G = 2 86 db G = db G = 98 6 db CMRR to 5 khz +IN = IN = V to + V G = 8 db G = 2 86 db G = 5 9 db G = 9 db NOISE Voltage Noise, khz, RTI G = nv/ Hz G = 2 27 nv/ Hz G = 5 2 nv/ Hz G = 8 nv/ Hz. Hz to Hz, RTI G = 2.5 µv p-p G = µv p-p G = 5.5 µv p-p G =. µv p-p Current Noise, khz 5 pa/ Hz Current Noise,. Hz to Hz 6 pa p-p VOLTAGE OFFSET Offset RTI V OS G =, 2, 5, ±2 + 6/G µv Over Temperature T = to +85 ±26 + 9/G µv Average TC T = to +85 ±.2 + 5/G µv/ Offset Referred to the Input vs. Supply (PSR) V S = ±5 V to ±5 V ±6 + 2/G µv/v INPUT CURRENT Input Bias Current 5 3 na Over Temperature T = to +85 na Average TC pa/ Input Offset Current 5 3 na Over Temperature T = to na Average TC 6 pa/ DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = MHz G = 2 MHz G = 5 MHz G = 3 MHz Settling Time.% ΔOUT = V step G = 585 ns G = 2 65 ns G = 5 65 ns G = 68 ns

4 AD825 Parameter Conditions Min Typ Max Unit Settling Time.% ΔOUT = V step G = 65 ns G = ns G = ns G = 685 ns Slew Rate G = 2 V/µs G = 2 25 V/µs G = 5 25 V/µs G = 25 V/µs Total Harmonic Distortion f = khz, R L = kω, G = db GAIN Gain Range G =, 2, 5, V/V Gain Error OUT = ± V G =.3 % G = 2, 5,. % Gain Nonlinearity OUT = V to + V G = R L = kω, 2 kω, 6 Ω 6 ppm G = 2 R L = kω, 2 kω, 6 Ω 8 ppm G = 5 R L = kω, 2 kω, 6 Ω 8 ppm G = R L = kω, 2 kω, 6 Ω ppm Gain vs. Temperature All gains ppm/ INPUT Input Impedance Differential GΩ pf Common Mode GΩ pf Input Operating Voltage Range V S = ±5 V to ±5 V +.. V Over Temperature T = to V OUTPUT Output Swing V Over Temperature T = to V Short-Circuit Current 37 ma ERENCE INPUT R IN 2 kω I IN +IN, IN, = µa Voltage Range V Gain to Output ±. V/V DIGITAL LOGIC Digital Ground Voltage, Referred to GND V Digital Input Voltage Low Referred to GND 2. V Digital Input Voltage High Referred to GND 2.8 V Digital Input Current µa Gain Switching Time 325 ns t SU See Figure 3 timing diagram 2 ns t HD ns t -LOW 2 ns t -HIGH ns

5 AD825 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range ±5 ±5 V Quiescent Current, +I S..5 ma Quescent Current, I S ma Over Temperature T = to ma TEMPERATURE RANGE Specified Performance +85 t -HIGH t -LOW t SU t HD A, A

6 AD825 3 Parameter Rating Supply Voltage ±7 V Power Dissipation See Figure 2 Output Short-Circuit Current Indefinite Common-Mode Input Voltage ±V S Differential Input Voltage ±V S Digital Logic Inputs ±V S Storage Temperature Range 65 to +25 Operating Temperature Range 2 to +85 Lead Temperature (Soldering sec) 3 Junction Temperature θ JA (-Layer JEDEC Standard Board) 2 /W Package Glass Transition Temperature AD825 T J AD825 PC θ JA T A P D T J T A (P D θ JA ) P D V S I S R L V S /2 I OUT V OUT I OUT PD Quiescent Power Total Drive Power Load Power VS VOUT VOUT PD ( VS IS) RL RL R L V S V OUT V S /2 θ JA θ JA JEDEC MAXIMUM POWER DISSIPATION (W) AMBIENT TEMPERATURE ( C) ESD. ESD ESD ESD 6288-

7 AD825 IN +IN A A AD825 TOP VIEW (Not to Scale) OUT MSOP RM-. IN 2 3 A LSB 5 A MSB 6 7 OUT 8 9 +IN

8 AD825 T +5V V S 5V R L kω 5 NUMBER OF UNITS UNITS NUMBER OF CMRR (µv/v) INPUT BIAS (na) CMRR G 9. NUMBER OF UNITS OFFSET VOLTAGE RTI (µv) Hz) (nv/ NOISE G = G = 2 3 G = 5 2 G = FREQUENCY (Hz) V OSI. 6 5 UNITS NUMBER OF INPUT BIAS (na) µV/DIV s/div HzG

9 AD G = G = 5 PSRR (db) 9 7 G = 2 G = 5 3 µv/div s/div k k k M FREQUENCY (Hz) HzG 5. PSRR RTI CURRENT NOISE (pa/ Hz) PSRR (db) G = 2 G = G = G = 5 2 FREQUENCY (Hz) k k k M FREQUENCY (Hz) PSRR RTI 5 (na) BIAS CURRENT 5 5 I B I B + I OS pa/div s/div TEMPERATURE ( C) Hz 7.

10 AD G = G = 5 2 G = CMRR (db) 8 G = 2 G = GAIN (db) 5 5 G = 5 G = 2 6 G = 5 2 k k k M FREQUENCY (Hz) 8. CMRR k k k M M M FREQUENCY (Hz) CMRR (db) G = G = 2 G = 5 G = 2 k k k M FREQUENCY (Hz) NONLINEARITY (ppm/div) f = khz OUTPUT VOLTAGE (V) CMRR kω 22. G R L kω 2kΩ 6Ω CMRR (µv/v ) TEMPERATURE ( C) NONLINEARITY (ppm/div) f = khz OUTPUT VOLTAGE (V) CMRRG 23. G 2 R L kω 2kΩ 6Ω

11 AD825 3 f = khz (V) 6 2.V, +3.6V V, +3.8V V S = ±5V +3.6V, +3.V NONLINEARITY (ppm/div) OUTPUT VOLTAGE (V) VOLTAGE COMMON-MODE INPUT 8 +V, +3.5V.2V, +2.2V +.3V, +2.V V S = ±5V.2V, 2.V +.3V, 2.V V,.V 8 2.V, 3.6V V, V +3.6V, 3.V OUTPUT VOLTAGE (V) G 5 R L kω 2kΩ 6Ω 27. G NONLINEARITY (ppm/div) f = khz OUTPUT VOLTAGE (V) INPUT VOLTAGE FERED TO SUPPLY VOLTAGES (V) +25 C +85 C C C C +25 C C C SUPPLY VOLTAGE (±V S ) G R L kω 2kΩ 6Ω 28. G V V R L kω INPUT COMMON-MODE VOLTAGE (V) V, +6.9V 3.8V, 6.9V 3.8V, +.9V 3.8V,.9V V, +3.8V V S = ±5V V, +3.7V V S = ±5V V,.V +3.8V, +6.9V +3.9V, +.9V +3.8V, 2.V +3.8V, 6.9V CURRENT (ma) IN IN 6 V, V OUTPUT VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) G 29. G R L kω

12 AD825 OUTPUT VOLTAGE SWING FERED TO SUPPLY VOLTAGES (V) C +85 C +25 C +25 C C C +85 C +25 C SUPPLY VOLTAGE (±V S ) OUTPUT VOLTAGE SWING ERRED TO SUPPLY VOLTAGES (V). +85 C +25 C C C C +25 C C C OUTPUT CURRENT (ma) G R L 2kΩ 33. OUTPUT VOLTAGE SWING FERED TO SUPPLY VOLTAGES (V) C C +25 C C +25 C C +25 C +85 C SUPPLY VOLTAGE (±V S ) V O U T (V ) NO LOAD 2mV/DIV 7pF pf TIME (µs) 2µs/DIV G R L kω C SWING (V) VOLTAGE OUTPUT C C +85 C +85 C C +25 C 5V/DIV.2%/DIV 585ns TO.% 65ns TO.% +25 C 5 k k LOAD RSISTANCE ( Ω ) TIME (µs) 2µs/DIV G R L kω

13 AD825 5V/DIV.2%/DIV 65ns TO.% 635ns TO.% V O U T (V ) TIME (µs) 2µs/DIV mV/DIV TIME (µs) 2µs/DIV G 2 R L kω 39. G R L 2kΩ C L pf 5V/DIV.2%/DIV 65ns TO.% 635ns TO.% V O U T (V ) TIME (µs) 2µs/DIV mV/DIV TIME (µs) 2µs/DIV G 5 R L kω. G 2 R L 2kΩ C L pf 5V/DIV.2%/DIV 68ns TO.% 685ns TO.% V O U T (V ) TIME (µs) 2µs/DIV mV/DIV TIME (µs) 2µs/DIV G R L kω. G 5 R L 2kΩ C L pf

14 AD SETTLED TO.% V O U T (V ) (ns) TIME 6 SETTLED TO.% 2 2mV/DIV TIME (µs) 2µs/DIV STEP SIZE (V) G R L 2kΩ C L pf 5. G 5 R L kω SETTLED TO.% 8 SETTLED TO.% (ns) TIME 6 SETTLED TO.% (ns) TIME 6 SETTLED TO.% STEP SIZE (V) STEP SIZE (V) G R L kω 6. G R L kω 2 8 SETTLED TO.% (ns) TIME 6 SETTLED TO.% STEP SIZE (V) G 2 R L kω

15 AD825 A A 2.2kΩ IN 2.2kΩ A kω kω DIGITAL GAIN CONTROL A3 OUTPUT A2 kω kω +IN 2.2kΩ 2.2kΩ AD icmos AD THD G.3% G 98dB CMRR CMRR 5kHz 8dB G CMRR CMRR AD825 V 5V 2 AD825 2 A A 8 A A 5 8 AD825 µf.µf +IN IN µf.µf +5V A A AD825 5V +5V +5V G = 5V NOTE:. IN TRANSPARENT GAIN MODE, IS TIED TO V S. THE VOLTAGE LEVELS ON A AND A DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A AND A ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF. 8. A A G

16 AD A A Gain Low Low Low High 2 High Low 5 High High PCB AD825 A A 9 AD825 5V V A A A A 6 µf.µf +IN IN µf.µf +5V + AD825 A A A A G = PREVIOUS STATE +5V V +5V V +5V V G = 6. A A Gain High to Low Low Low Change to High to Low Low High Change to 2 High to Low High Low Change to 5 High to Low High High Change to Low to Low X X No Change Low to High X X No Change High to High X X No Change X AD825 AD825 A A t SU A A t HD t HD A A t -HIGH t -LOW 2 5 AD825 PCB 5V NOTE:. ON THE DOWNWARD EDGE OF, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A AND A ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = G t -HIGH t -LOW t SU t HD A, A

17 AD825 AD825 PSRR DC.µF µf 5 IC INCORRECT AD825 TRANSFORMER CORRECT AD825 TRANSFORMER.µF µf +IN A A AD825 AD825 AD825 V OUT MΩ LOAD IN THERMOCOUPLE THERMOCOUPLE.µF µf C C AD825 f HIGH-PASS = 2 πrc C C R AD825 AD CAPACITIVELY COUPLED CAPACITIVELY COUPLED 52. I BIAS AD825 ESD 7 ESD 2.2kΩ 3V 3V DC 3V AD8256mA AD825 BAV99L FJH SP72 R

18 AD825 kω 7 AD825 ADC V S V S.5V CMRR V AD825 AD INCORRECT AD825 V AD825 PC + CORRECT OP77 AD AD825 AD825 CMRR AD825 2Hz CMRR AD825 CMRR CMRR PCB RF RF RF DC 5 R-C FilterFreq DIFF πr CD CC FilterFreq CM πrcc C D C C AD825

19 AD825 R R C C C D C C.µF +IN IN +5V AD825.µF µf 5V 5. RFI R C C RFI R C C R C C AD825 CMRR C C C D A/D CMRR A/D ADC AD825 ADC µf V OUT nf 9.9Ω AD762 nf ADC 9.9Ω nf AD762 AD825 AD762 AD825 µf.µf +IN IN µf.µf +5V 5V A A AD Ω nf 55. ADC.µF +2V 2V AD762 +5V ADR35.µF

20 AD825 ADC 57 AD825 AD87 V DC ADC ADC ADC V ADC µf.µf +IN IN +5V + A A AD825 MICRO- CONTROLLER µf.µf 5V V.µF +5V 5V AMPLITUDE V IN +IN + A AD825 G = A.99kΩ V OUT A = V IN + V 2 AMPLITUDE +2.5V 2.5V V TIME +2V 2V µf.µf µf 2V.99kΩ 2V pf.µf + AD87 +2V.µF V OUT B = V IN + V V V AMPLITUDE +2.5V 2.5V V TIME

21 AD825 AD825 6 ADC 59AD825x AD825 FPGA AD762 AD825 ADG29 khz db THD 9dB S/N 58 (db) AMPLITUDE FREQUENCY (khz) 58. AD825 AD825x DAQ FFT khz JMP.µF +2V +2V + + 2V µf µf JMP +5V 2kΩ +CH +CH2 +CH3 +CH CH CH3 CH2 CH 86Ω 86Ω 86Ω 86Ω 86Ω 86Ω 86Ω 86Ω V DD 2 SA EN 5 S2A 6 S3A 7 SA 8 ADG29 SB S3B 9 2 S2B 5 A SB A V SS GND Ω Ω C D Ω Ω C C +IN C C IN 2 6 C3.µF 5 JMP + A A AD825 V V 9 S V 2V C.µF +5V 2kΩ VOUT 7 Ω 9.9Ω +IN nf AD762 ADR35 ALTERA EPF6ATC-3.µF 2V JMP +5V 2kΩ JMP +5V R8 2kΩ 59. AD825x DAQ ADG29 AD825 AD

22 AD PIN BSC COPLANARITY MAX SEATING PLANE D6288--/7()-J COMPLIANT TO JEDEC STANDARDS MO-87-BA 6. MSOP RM- mm Model Temperature Range Package Description Package Option Branding AD825ARMZ to +85 -Lead MSOP RM- H AD825ARMZ-RL to +85 -Lead MSOP RM- H AD825ARMZ-R7 to +85 -Lead MSOP RM- H AD825-EVALZ Evaluation Board Z