Cloud[2] (48 ) Xeon Phi (50+ ) IBM Cyclops[9] (64 ) Cavium Octeon II (32 ) Tilera Tile-GX (100 ) PE [11][7] 2 Nsim[10] 8080[1] SH-2[5] SH [8

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1 1600 1,a) 1,b) 8080 SH SH-2 Simulation of a Many-Core Architecture with 16 Million Processing Cores Hisanobu Tomari 1,a) Kei Hiraki 1,b) Abstract: 8080 and SH-2 processors are evaluated as building blocks for a many-core architecture. In manycore architecture processor core designs simpler than conventional ones are often used because the number of processing elements that are integrated on a chip is limited by the size of the processor core. A many-core system design intends to maximize the throughput of instruction execution through the balance between the number of processor cores and the performance of a processor core. We put the 8080, which is one of the simplest processors, and the SH-2 pipelined processor in our many-core design to examine the optimal balance of simplicity and performance for the processor core in many-core designs. 1. [3] 1 The University of Tokyo a) [email protected] b) [email protected] [4] 1 Intel Single-chip 1

2 Cloud[2] (48 ) Xeon Phi (50+ ) IBM Cyclops[9] (64 ) Cavium Octeon II (32 ) Tilera Tile-GX (100 ) PE [11][7] 2 Nsim[10] 8080[1] SH-2[5] SH [8] Processing Element (PE) PE Shuffle Exchange 1 PE 2 Pipe ( ), Rank ( ) Rank Shuffle Exchange 1 ( 1) I/O PE Shuffle Exchange hop hop Reflective Memory [6] PE PE n n 1 PE ( 2) n n + 1 PE PE 1 PE 1 PE SH SH / 8080 PE SH-2 MIPS ARM, PowerPC 32 SH SH 8080 SH-2 SH-2 GNU ROM GNU Binutils 2

3 Pipe 0 Pipe 1 Pipe 2 Pipe 3 Pipe 4 Pipe 5 Pipe 6 Pipe 7 rank 0 rank 1 rank 2 rank 3 rank 4 1 PE PE Address space RM_P1 RM_P2 Other PE Local Memory RM_IN1 RM_IN2 Mapped to local memory in PEs in the next rank Mapped to local memory RM_P1 Another PE RM_P RM_P2 RM_P Config Previous rank 2 PE 3

4 C KiB SH-2 2 KiB bytes Shuffle Exchange 2 1 KiB 256 bytes SH MAME MAME CPU PE 0 MAME CPU 8080 SH S N Number of packets Synchronization bit 3 N packets follow Payload Destination Pipe ID Distasnce to the destination 4 PE SH PE KiB GiB SH-2 2 KiB SH GiB OS PE 4

5 Clock count Npipe 8080 SH N rank N pipe = ,269 6,010 12,059 22, ,594 12,314 23, ,578 24, ,270 1 δ δ2 r(n, t) = r(n, t) (1) δt δn2 r(n, t) = (x, y, z, w) ( SH-2 1 ) ( 3) 1 PE-PE 0 ( ) 1 ( PE) PE 2 PE log 2 N pipe SH-2 Shuffle Exchange log 2 N pipe SH / x t+1 (n) = (x t (n 1) 2x t (n) + x t (n + 1))/4 (2) log 2 N pipe PE log 2 N pipe PE Algorithm 1 hop ID ( 1) log 2 N pipe SH2 ( 6) Routing Calc Send 5

6 Algorithm 1 PE loop wait(output port 0 sync bit=0) output port 0 number of packets 0 wait(output port 1 sync bit=0) output port 1 number of packets 0 for p input port 0 and input port 1 do wait(p sync bit=1) for n = 0 to p number of packets do q pointer to the head of nth packet if distance to destination in q > 0 then route this packet to output port else copy payload to static region end if end for done(input port p, sync bit 0) end for do calculation output port 0, sync bit 1 output port 1, sync bit 1 end loop Cycles Cycles/s Route/SH Calc/SH Route/80 Calc/80 Send Calc Routing SH-2 1/ SH SH SH SH-2 SH SH SH SH-2 33% KiB SH Intel Westmere (2.93 GHz) SH-2 7 SH /7 ( 7) SH SH MHz SH MHz 10 1e+06 1e+07 1e+08 PE count FPGA

7 64 FPGA Xilinx Virtex-6 XC6VLX240T-1FF Shuffle Exchange Shuffle Exchange PE Shuffle Exchange I/O Shuffle Exchange Shuffle Exchange 4. SH SH SH SH-2 FPGA MIPS [1] Intel Corporation. intel 8080 microcomputer systems user s manual. September [2] Jim Held. Single-chip cloud computer an experimental many-core processor from Intel Labs. Intel Labs Singlechip Cloud Computer Symposium, [3] R. Kalla, B. Sinharoy, W.J. Starke, and M. Floyd. Power7: Ibm s next-generation server processor. Micro, IEEE, 30(2):7 15, march-april [4] P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: a 32-way multithreaded sparc processor. Micro, IEEE, 25(2):21 29, march-april [5] Hitachi America Ltd. Superh risc engine sh-1/sh-2 programming manual. September [6] S. Lucci, I. Gertner, A. Gupta, and U. Hegde. Reflectivememory multiprocessor. In System Sciences, Proceedings of the Twenty-Eighth Hawaii International Conference on, volume 1, pages vol.1, jan [7] Hisanobu Tomari. Design and evaluation of sea-of-core array architecture with 32 million processor cores. Masther Thesis, Dept. of Computer Science, the University of Tokyo, Mar [8] M. Yokokawa, F. Shoji, A. Uno, M. Kurokawa, and T. Watanabe. The k computer: Japanese nextgeneration supercomputer development project. In Low Power Electronics and Design (ISLPED) 2011 International Symposium on, pages , aug [9] Ying Ping Zhang, Taikyeong Jeong, Fei Chen, Haiping Wu, R. Nitzsche, and G.R. Gao. A study of the on-chip interconnection network for the ibm cyclops64 multicore architecture. In Parallel and Distributed Processing Symposium, IPDPS th International, page 10 pp., april [10],,,,,, and. PSI-NSIM :. IEICE technical report. Computer systems, 107(276):45 50, [11] and.. ARC 2010-ARC-190(3), jul

Intel Xeon Phi (60 ) IBM Cyclops (64 [7]) [1] 10nm Memory Wall [6] [9] FPGA SH-2 2. FPGA FPGA FPGA Xilinx Virtex-6 HXT XC6VHX565T FPGA 2

Intel Xeon Phi (60 ) IBM Cyclops (64 [7]) [1] 10nm Memory Wall [6] [9] FPGA SH-2 2. FPGA FPGA FPGA Xilinx Virtex-6 HXT XC6VHX565T FPGA 2 FPGA NoC 1,a) 1,b) FPGA SH-2 Design of FPGA-based Many-core Evaluation Platform and NoC Evaluation Hisanobu Tomari 1,a) Kei Hiraki 1,b) Abstract: We developed a platform for examining realistic behavior