1 1 Abstract 7 2 Pin Assignment 9 3 Instruction

Transcription

1 I/O Core Ver

2 1 1 Abstract 7 2 Pin Assignment 9 3 Instruction Opecode Function Rt Rs ALU System Call / Break Point FPU Exception CPU Control Register FPU

3 7 Memory Management Unit MMU MMU Bus External Bus Timer Clock Generator Clock Divider Clock Gating Reset Universal Asynchronous Receiver/Transmitter Receiver Buffer (RB) / Transmitter Holding Register (THR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) FIFO Control Register (FCR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR)

4 Modem Status Register (MSR) Divisor Latches (DL) / Initialization General Purpose I/O Unit Outline Interface Address Format Control Register Operation Serial Peripheral Interface Unit Outline Interface Address Format Control Register Operation Manual Mode Auto Mode I2C Master Controller Outline Interface Address Format Control Register Operation System Configuration I2C Protocol Arbitration Procudure Clock Stretching PWM Generator PWM PWM PWM PWM PWM Input PWM PWMIN PWMIN HIGH PWMIN LOW

5 18 Pulse Counter Real Time Clock Outline Interface Address Map DMA Controller DMA DMA PCI Host Controller Outline Bridge Control Register Block PCI Configuration Space Bridge ID Register (0x40) Bridge Control Register (0x44) Bridge status register (0x46) Interrupt Status Register (0x4A) Interrupt Mask Register (0x48) PCI Address Pointer (0x4C) PCI Transfer Counter (0x50) PCI Command Register (0x54) Initiator Dual-port Memory Data Pointer (0x58) On-Chip Emulator Outline Operation Single Write Single Read

6 23 Responsive Link B B CODEC Bit Stuffing NRZI DPLL SDRAM SDRAM SDRAM LRU LRU SDRAM SDRAM

7 SDRAM DPM (Dual Port Memory) Event Output Event Input Data Output Data Input Responsive Link

8 7 1 Abstract I/O Core I/O System-on-Chip MIPS I/O I/O Responsive Link PCI, GPIO, SPI, I2C, UART, PWM, Encoder 1.1: I/O Core I/O Core I/O Responsive Link (4ch) PCI Controller (1ch)

9 1 Abstract Serial Peripheral Interface (4cs 1ch) UART (2ch) I2C Master Controller(1ch) Digital Port (8bit) PWM Generator (6ch) PWM Input (2ch) Pulse Counter (2ch) Real-Time Clock (1ch) Timer (4ch) On-Chip Emulator (1ch) External Bus I/F (4ch) DMA Controller (4ch 2) DDR SDRAM I/F (1ch) SRAM (16kB) 8

10 9 2 Pin Assignment IO 2.1: Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 0 AC22 PVSS2DGZ b00 PVSS2DGZ - - VSSIO AA20 pci clk PCI66SDGZ LVTTL Input PCI Clock AC21 PVDD2DGZ b00 PVDD2DGZ 3.3V - VDDIO Y19 pci rst PCI66SDGZ LVTTL Input PCI Reset - Active Low 4 W18 pci idsel PCI66SDGZ LVTTL Input Init Dev Sel V17 pci frame PCI66SDGZ LVTTL In/Out Transaction Frame - Active Low 6 AB20 PVSS2DGZ b01 PVSS2DGZ - - VSSIO U17 pci irdy PCI66SDGZ LVTTL In/Out Initiator Ready - Active Low 8 AC20 pci trdy PCI66SDGZ LVTTL In/Out Target Ready - Active Low 9 AA19 pci stop PCI66SDGZ LVTTL In/Out Stop Output - Active Low 10 T16 pci devsel PCI66SDGZ LVTTL In/Out Device Select - Active Low 11 Y18 PVDD2DGZ b01 PVDD2DGZ 3.3V - VDDIO W17 pci ad31 PCI66SDGZ LVTTL In/Out A/D Bus AB19 pci ad30 PCI66SDGZ LVTTL In/Out A/D Bus AC19 pci ad29 PCI66SDGZ LVTTL In/Out A/D Bus U16 pci ad28 PCI66SDGZ LVTTL In/Out A/D Bus AA18 PVSS2DGZ b02 PVSS2DGZ - - VSSIO Y17 pci ad27 PCI66SDGZ LVTTL In/Out A/D Bus V16 pci ad26 PCI66SDGZ LVTTL In/Out A/D Bus AB18 pci ad25 PCI66SDGZ LVTTL In/Out A/D Bus W16 pci ad24 PCI66SDGZ LVTTL In/Out A/D Bus AC18 PVDD2DGZ b02 PVDD2DGZ 3.3V - VDDIO T15 pci ad23 PCI66SDGZ LVTTL In/Out A/D Bus AA17 pci ad22 PCI66SDGZ LVTTL In/Out A/D Bus U15 pci ad21 PCI66SDGZ LVTTL In/Out A/D Bus Y16 pci ad20 PCI66SDGZ LVTTL In/Out A/D Bus AB17 PVSS2DGZ b03 PVSS2DGZ - - VSSIO AC17 pci ad19 PCI66SDGZ LVTTL In/Out A/D Bus V15 pci ad18 PCI66SDGZ LVTTL In/Out A/D Bus AA16 PVSS1DGZ b00 PVSS1DGZ - - VSS - -

11 2 Pin Assignment Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 30 W15 pci ad17 PCI66SDGZ LVTTL In/Out A/D Bus T14 pci ad16 PCI66SDGZ LVTTL In/Out A/D Bus AB16 PVDD1DGZ b00 PVDD1DGZ 1.0V - VDD AC16 pci ad15 PCI66SDGZ LVTTL In/Out A/D Bus Y15 pci ad14 PCI66SDGZ LVTTL In/Out A/D Bus AA15 PVSS1DGZ b01 PVSS1DGZ - - VSS U14 pci ad13 PCI66SDGZ LVTTL In/Out A/D Bus V14 pci ad12 PCI66SDGZ LVTTL In/Out A/D Bus AB15 PVDD1DGZ b01 PVDD1DGZ 1.0V - VDD AC15 pci ad11 PCI66SDGZ LVTTL In/Out A/D Bus T13 pci ad10 PCI66SDGZ LVTTL In/Out A/D Bus W14 PVSS1DGZ b02 PVSS1DGZ - - VSS Y14 pci ad9 PCI66SDGZ LVTTL In/Out A/D Bus AA14 pci ad8 PCI66SDGZ LVTTL In/Out A/D Bus AB14 PVDD1DGZ b02 PVDD1DGZ 1.0V - VDD AC14 pci ad7 PCI66SDGZ LVTTL In/Out A/D Bus U13 pci ad6 PCI66SDGZ LVTTL In/Out A/D Bus V13 PCI66SDGZ b03 PVSS1DGZ - - VSS W13 pci ad5 PCI66SDGZ LVTTL In/Out A/D Bus Y13 pci ad4 PCI66SDGZ LVTTL In/Out A/D Bus AA13 PVDD2DGZ b03 PVDD2DGZ 3.3V - VDDIO AB13 pci ad3 PCI66SDGZ LVTTL In/Out A/D Bus AC13 pci ad2 PCI66SDGZ LVTTL In/Out A/D Bus V12 PVSS2DGZ b04 PVSS2DGZ - - VSSIO W12 pci ad1 PCI66SDGZ LVTTL In/Out A/D Bus Y12 PVSS1DGZ b04 PVSS1DGZ - - VSS AA12 pci ad0 PCI66SDGZ LVTTL In/Out A/D Bus AB12 PVDD1DGZ b03 PVDD1DGZ 1.0V - VDD AC12 pci cbe3 PCI66SDGZ LVTTL In/Out C/B En Bus 3 - Active Low 59 U12 pci cbe2 PCI66SDGZ LVTTL In/Out C/B En Bus 2 - Active Low 60 W11 PVSS1DGZ b05 PVSS1DGZ - - VSS Y11 pci cbe1 PCI66SDGZ LVTTL In/Out C/B En Bus 1 - Active Low 62 AA11 pci cbe0 PCI66SDGZ LVTTL In/Out C/B En Bus 0 - Active Low 63 AB11 PVSS1DGZ b06 PVSS1DGZ - - VSS AC11 pci par PCI66SDGZ LVTTL In/Out Parity V11 PVDD2DGZ b04 PVDD2DGZ 3.3V - VDDIO U11 pci perr PCI66SDGZ LVTTL In/Out Parity Error - Active Low 67 T11 pci serr PCI66SDGZ LVTTL In/Out System Error - Active Low 68 AA10 PVSS2DGZ b05 PVSS2DGZ - - VSSIO AB10 pci req PCI66SDGZ LVTTL Input Master Request - Active Low 70 AC10 pci gnt PCI66SDGZ LVTTL Output Master Grant - Active Low 71 Y10 PVDD1DGZ b04 PVDD1DGZ 1.0V - VDD W10 pci inta PCI66SDGZ LVTTL Input Interrupt A - Active Low 73 V10 PVSS1DGZ b07 PVSS1DGZ - - VSS AA9 pci intb PCI66SDGZ LVTTL Input Interrupt B - Active Low 75 AB9 PVSS1DGZ b08 PVSS1DGZ - - VSS AC9 pci intc PCI66SDGZ LVTTL Input Interrupt C - Active Low 77 Y9 PVDD1DGZ b05 PVDD1DGZ 1.0V - VDD W9 pci intd PCI66SDGZ LVTTL Input Interrupt D - Active Low 79 V9 link sdram oe pnl sstl 2classi SSTL2 Output Output Enable - Active Low 80 U10 link sdram dir pnl sstl 2classi SSTL2 Output Direction AC8 link sdram addr04 pnl sstl 2classi SSTL2 Output SDRAM Address AB8 link sdram addr03 pnl sstl 2classi SSTL2 Output SDRAM Address AA8 link sdram addr05 pnl sstl 2classi SSTL2 Output SDRAM Address Y8 pnl sstl gcs b00 pnl sstl gcs - - VSS AB7 link sdram addr02 pnl sstl 2classi SSTL2 Output SDRAM Address AC7 pnl sstl vc b00 pnl sstl vc 1.0V - VDD W8 link sdram addr06 pnl sstl 2classi SSTL2 Output SDRAM Address AA7 pnl sstl go b00 pnl sstl go - - VSSIO U9 link sdram addr01 pnl sstl 2classi SSTL2 Output SDRAM Address Y7 pnl sstl vq b00 pnl sstl vq 2.5V - VDDIO W7 link sdram addr07 pnl sstl 2classi SSTL2 Output SDRAM Address AC6 pnl sstl gcs b01 pnl sstl gcs - - VSS AB6 link sdram addr00 pnl sstl 2classi SSTL2 Output SDRAM Address

12 Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 94 V8 link sdram addr08 pnl sstl 2classi SSTL2 Output SDRAM Address AA6 link sdram addr10 pnl sstl 2classi SSTL2 Output SDRAM Address V7 pnl sstl vc b01 pnl sstl vc 1.0V - VDD AC5 link sdram addr09 pnl sstl 2classi SSTL2 Output SDRAM Address Y6 link sdram bank1 pnl sstl 2classi SSTL2 Output SDRAM Bank Address AB5 pnl sstl go b01 pnl sstl go - - VSSIO T10 link sdram addr11 pnl sstl 2classi SSTL2 Output SDRAM Address W6 pnl sstl vq b01 pnl sstl vq 2.5V - VDDIO AA5 link sdram bank0 pnl sstl 2classi SSTL2 Output SDRAM Bank Address AC4 link sdram addr12 pnl sstl 2classi SSTL2 Output SDRAM Address U8 link sdram cs1 pnl sstl 2classi SSTL2 Output SDRAM CS 1 - Active Low 105 AB4 link sdram cs0 pnl sstl 2classi SSTL2 Output SDRAM CS0 - Active Low 106 V6 link sdram cke pnl sstl 2classi SSTL2 Output SDRAM Clock Enable Y5 link sdram ras pnl sstl 2classi SSTL2 Output SDRAM RAS - Active Low 108 AC3 pnl sstl go b02 pnl sstl go - - VSSIO U7 link sdram cas pnl sstl 2classi SSTL2 Output SDRAM CAS - Active Low 110 AA4 pnl sstl vq b02 pnl sstl vq 2.5V - VDDIO U6 link sdram we pnl sstl 2classi SSTL2 Output SDRAM Write Enable - Active Low 112 AB3 pnl sstl gcs b02 pnl sstl gcs - - VSS AC2 link sdram dqm3 pnl sstl 2classi SSTL2 Output SDRAM DQM W5 link sdram dqm1 pnl sstl 2classi SSTL2 Output SDRAM DQM Y4 link sdram dqm2 pnl sstl 2classi SSTL2 Output SDRAM DQM T9 link sdram dqm0 pnl sstl 2classi SSTL2 Output SDRAM DQM AB2 link sdram clk pnl sstl 2classi SSTL2 Output SDRAM Clock AA3 pnl sstl go r00 pnl sstl go - - VSSIO AB1 link sdram clk pnl sstl 2classi SSTL2 Output SDRAM Clock X T8 sstl vref pnl sstl vref - - SDRAM VREF V5 link sdram dqs3 pnl sstl 2classi SSTL2 In/Out SDRAM DQS AA2 pnl sstl vp r00 pnl sstl vp 2.5V - VDDIO AA1 link sdram dq31 pnl sstl 2classi SSTL2 In/Out SDRAM DQ Y3 pnl sstl vc r00 pnl sstl vc 1.0V - VDD W4 link sdram dq30 pnl sstl 2classi SSTL2 In/Out SDRAM DQ Y2 pnl sstl gcs r00 pnl sstl gcs - - VSS T7 link sdram dq29 pnl sstl 2classi SSTL2 In/Out SDRAM DQ U5 link sdram dq28 pnl sstl 2classi SSTL2 In/Out SDRAM DQ Y1 pnl sstl gcs r01 pnl sstl gcs - - VSS T6 link sdram dq27 pnl sstl 2classi SSTL2 In/Out SDRAM DQ W3 link sdram dq26 pnl sstl 2classi SSTL2 In/Out SDRAM DQ V4 pnl sstl vc r01 pnl sstl vc 1.0V - VDD W2 link sdram dq25 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R8 link sdram dq24 pnl sstl 2classi SSTL2 In/Out SDRAM DQ W1 pnl sstl go r01 pnl sstl go - - VSSIO T5 link sdram dqs2 pnl sstl 2classi SSTL2 In/Out SDRAM DQS V3 pnl sstl vq r01 pnl sstl vq 2.5V - VDDIO U4 link sdram dq23 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R6 link sdram dq22 pnl sstl 2classi SSTL2 In/Out SDRAM DQ V2 pnl sstl gcs r02 pnl sstl gcs - - VSS V1 link sdram dq21 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R7 link sdram dq20 pnl sstl 2classi SSTL2 In/Out SDRAM DQ U3 pnl sstl gcs r03 pnl sstl gcs - - VSS R5 link sdram dq19 pnl sstl 2classi SSTL2 In/Out SDRAM DQ T4 link sdram dq18 pnl sstl 2classi SSTL2 In/Out SDRAM DQ U2 pnl sstl vc r02 pnl sstl vc 1.0V - VDD U1 link sdram dq17 pnl sstl 2classi SSTL2 In/Out SDRAM DQ P8 link sdram dq16 pnl sstl 2classi SSTL2 In/Out SDRAM DQ P7 pnl sstl go r02 pnl sstl go - - VSSIO P6 link sdram dqs1 pnl sstl 2classi SSTL2 In/Out SDRAM DQS T3 pnl sstl vq r02 pnl sstl vq 2.5V - VDDIO T2 link sdram dq15 pnl sstl 2classi SSTL2 In/Out SDRAM DQ T1 link sdram dq14 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R4 pnl sstl gcs r04 pnl sstl gcs - - VSS N8 link sdram dq13 pnl sstl 2classi SSTL2 In/Out SDRAM DQ P5 link sdram dq12 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R3 pnl sstl vc r03 pnl sstl vc 1.0V - VDD

13 2 Pin Assignment Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 158 R2 link sdram dq11 pnl sstl 2classi SSTL2 In/Out SDRAM DQ R1 link sdram dq10 pnl sstl 2classi SSTL2 In/Out SDRAM DQ N7 pnl sstl gcs r05 pnl sstl gcs - - VSS N6 link sdram dq9 pnl sstl 2classi SSTL2 In/Out SDRAM DQ P4 link sdram dq8 pnl sstl 2classi SSTL2 In/Out SDRAM DQ P3 pnl sstl go r03 pnl sstl go - - VSSIO P2 link sdram dqs0 pnl sstl 2classi SSTL2 In/Out SDRAM DQS P1 pnl sstl vq r03 pnl sstl vq 2.5V - VDDIO M7 link sdram dq7 pnl sstl 2classi SSTL2 In/Out SDRAM DQ N5 link sdram dq6 pnl sstl 2classi SSTL2 In/Out SDRAM DQ N4 pnl sstl vc r04 pnl sstl vc 1.0V - VDD N3 link sdram dq5 pnl sstl 2classi SSTL2 In/Out SDRAM DQ N2 link sdram dq4 pnl sstl 2classi SSTL2 In/Out SDRAM DQ N1 pnl sstl gcs r06 pnl sstl gcs - - VSS M6 link sdram dq3 pnl sstl 2classi SSTL2 In/Out SDRAM DQ M5 link sdram dq2 pnl sstl 2classi SSTL2 In/Out SDRAM DQ M4 pnl sstl vq r04 pnl sstl vq 2.5V - VDDIO M3 link sdram dq1 pnl sstl 2classi SSTL2 In/Out SDRAM DQ M2 link sdram dq0 pnl sstl 2classi SSTL2 In/Out SDRAM DQ M1 pnl sstl go r04 pnl sstl go - - VSSIO L4 lvds vref pnl vref lvds - - LVDS VREF L3 pnl vc lvds r00 pnl vc lvds 3.3V - VDD L5 link data s out1 p pnl lvds85 out gcs LVDS Output Data Link OutP L2 pnl lvds85 out gcs r00 pnl lvds85 out gcs - - VSS L6 link data s out1 n pnl lvds85 out gcs LVDS Output Data Link OutN L1 pnl go lvds r00 pnl go lvds - - VSSIO K5 link data s out2 p pnl lvds85 out vop LVDS Output Data Link OutP K4 pnl lvds85 out vop r00 pnl lvds85 out vop 2.5V - VDDIO K6 link data s out2 n pnl lvds85 out vop LVDS Output Data Link OutN K3 pnl gcs lvds r00 pnl gcs lvds - - VSS K1 link data s in1 p pnl lvds85 se in LVDS Input Data Link In P K2 link data s in1 n pnl lvds85 se in LVDS Input Data Link In N J3 link data s out3 p pnl lvds85 out vc LVDS Output Data Link OutP J2 pnl lvds85 out vc r00 pnl lvds85 out vc 3.3V - VDD J4 link data s out3 n pnl lvds85 out vc LVDS Output Data Link OutN J1 pnl gcs lvds r01 pnl gcs lvds - - VSS H3 link data s out4 p pnl lvds85 out go LVDS Output Data Link OutP H2 pnl lvds85 out go r00 pnl lvds85 out go - - VSSIO H4 link data s out4 n pnl lvds85 out go LVDS Output Data Link OutN H1 pnl vop lvds r00 pnl vop lvds 2.5V - VDDIO J5 link data s in2 p pnl lvds85 se in LVDS Input Data Link In P J6 link data s in2 n pnl lvds85 se in LVDS Input Data Link In N H5 pnl gcs lvds r02 pnl gcs lvds - - VSS G2 link data s in3 p pnl lvds85 se in LVDS Input Data Link In P G1 link data s in3 n pnl lvds85 se in LVDS Input Data Link In N G3 pnl vc lvds r01 pnl vc lvds 3.3V - VDD G4 link data s in4 p pnl lvds85 se in LVDS Input Data Link In P G5 link data s in4 n pnl lvds85 se in LVDS Input Data Link In N H6 pnl gcs lvds r03 pnl gcs lvds - - VSS F1 link event s in4 p pnl lvds85 se in LVDS Input Event Link In P F2 link event s in4 n pnl lvds85 se in LVDS Input Event Link In N F3 pnl go lvds r01 pnl go lvds - - VSSIO G6 link event s out4 p pnl lvds85 out vop LVDS Output Event Link Out P F4 pnl lvds85 out vop r01 pnl lvds85 out vop 2.5V - VDDIO F6 link event s out4 n pnl lvds85 out vop LVDS Output Event Link Out N E1 link event s in3 p pnl lvds85 se in LVDS Input Event Link In P E2 link event s in3 n pnl lvds85 se in LVDS Input Event Link In N E3 pnl gcs lvds r04 pnl gcs lvds - - VSS F5 link event s in2 p pnl lvds85 se in LVDS Input Event Link In P E5 link event s in2 n pnl lvds85 se in LVDS Input Event Link In N D3 link event s out3 p pnl lvds85 out vc LVDS Output Event Link Out P D1 pnl lvds85 out vc r01 pnl lvds85 out vc 3.3V - VDD D2 link event s out3 n pnl lvds85 out vc LVDS Output Event Link Out N E4 pnl gcs lvds r05 pnl gcs lvds - - VSS

14 Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 222 E6 link event s out2 p pnl lvds85 out go LVDS Output Event Link Out P D4 pnl lvds85 out go r01 pnl lvds85 out go - - VSSIO D6 link event s out2 n pnl lvds85 out go LVDS Output Event Link Out N C1 pnl vop lvds r01 pnl vop lvds 2.5V - VDDIO C2 link event s in1 p pnl lvds85 se in LVDS Input Event Link In P C3 link event s in1 n pnl lvds85 se in LVDS Input Event Link In N D5 pnl vc lvds r02 pnl vc lvds 3.3V - VDD C5 link event s out1 p pnl lvds85 out gcs LVDS Output Event Link Out P B1 pnl lvds85 out gcs r01 pnl lvds85 out gcs - - VSS C4 link event s out1 n pnl lvds85 out gcs LVDS Output Event Link Out N B2 uart stx pad1 pnl tf04it0nn2 LVTTL Output UART CH1 TxD L7 uart srx pad1 pnl it2nn2 LVTTL Output UART CH1 RxD L8 uart dtr pad0 pnl tf04it0nn2 LVTTL Input UART CH0 DSR B3 uart rts pad0 pnl tf04it0nn2 LVTTL Output UART CH0 RTS A2 pnl vc t00 pnl vc 1.0V - VDD K7 uart stx pad0 pnl tf04it0nn2 LVTTL Output UART CH0 TxD K8 uart dcd pad0 pnl it2nn2 LVTTL Input UAR CH0T DCD B4 pnl gcs t00 pnl gcs - - VSS J7 uart ri pad0 pnl it2nn2 LVTTL Input UART CH0 RI H7 uart dsr pad0 pnl it2nn2 LVTTL Input UART CH0 DSR A3 uart srx pad0 pnl it2nn2 LVTTL Input UART CH0 RxD C6 uart cts pad0 pnl it2nn2 LVTTL Input UART CH0 CTS B5 pnl go t00 pnl go - - VSSIO D7 spi mosi pnl tf04it0nn2 LVTTL - SPI MOSI Pull-Down E7 spi miso pnl it2nn2 LVTTL - SPI MISO Pull-Down A4 pnl vop t00 pnl vop 3.3V - VDDIO F7 spi sck pnl tf04it0nn2 LVTTL - SPI Clock Pull-Down C7 pnl gcs t01 pnl gcs - - VSS B6 spi ss0 pnl tf04it0nn2 LVTTL - SPI SS 0 Pull-Up Active Low 251 G7 spi ss1 pnl tf04it0nn2 LVTTL - SPI SS 1 Pull-Up Active Low 252 A5 pnl vc t01 pnl vc 1.0V - VDD J8 spi ss2 pnl tf04it0nn2 LVTTL - SPI SS 2 Pull-Up Active Low 254 H8 spi ss3 pnl tf04it0nn2 LVTTL - SPI SS 2 Pull-Up Active Low 255 G8 pnl go t01 pnl go - - VSSIO D8 gpio data7 pnl tf04it0nn2 LVTTL - GPIO Data A6 gpio data6 pnl tf04it0nn2 LVTTL - GPIO Data B7 pnl vop t01 pnl vop 3.3V - VDDIO E8 gpio data5 pnl tf04it0nn2 LVTTL - GPIO Data C8 gpio data4 pnl tf04it0nn2 LVTTL - GPIO Data F8 pnl gcs t02 pnl gcs - - VSS H9 gpio data3 pnl tf04it0nn2 LVTTL - GPIO Data A7 gpio data2 pnl tf04it0nn2 LVTTL - GPIO Data G9 gpio data1 pnl tf04it0nn2 LVTTL - GPIO Data B8 gpio data0 pnl tf04it0nn2 LVTTL - GPIO Data E9 pnl gcs t03 pnl gcs - - VSS D9 i2c scl pnl tf04it0nn2 LVTTL In/Out I2C SCL Pull-Up C9 i2c sda pnl tf04it0nn2 LVTTL In/Out I2C SDA Pull-Up A8 pnl vc t02 pnl vc 1.0V - VDD F9 ext bus data31 pnl tf12it0nn2 LVTTL - Ext Data H10 ext bus data30 pnl tf12it0nn2 LVTTL - Ext Data B9 pnl go t02 pnl go - - VSSIO G10 ext bus data29 pnl tf12it0nn2 LVTTL - Ext Data F10 ext bus data28 pnl tf12it0nn2 LVTTL - Ext Data A9 pnl vop t02 pnl vop 3.3V - VDDIO H11 ext bus data27 pnl tf12it0nn2 LVTTL - Ext Data E10 ext bus data26 pnl tf12it0nn2 LVTTL - Ext Data D10 ext bus data25 pnl tf12it0nn2 LVTTL - Ext Data C10 ext bus data24 pnl tf12it0nn2 LVTTL - Ext Data B10 pnl gcs t04 pnl gcs - - VSS A10 ext bus data23 pnl tf12it0nn2 LVTTL - Ext Data G11 ext bus data22 pnl tf12it0nn2 LVTTL - Ext Data F11 ext bus data21 pnl tf12it0nn2 LVTTL - Ext Data E11 ext bus data20 pnl tf12it0nn2 LVTTL - Ext Data

15 2 Pin Assignment Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 285 D11 pnl vc t03 pnl vc 1.0V - VDD C11 ext bus data19 pnl tf12it0nn2 LVTTL - Ext Data A11 ext bus data18 pnl tf12it0nn2 LVTTL - Ext Data B11 ext bus data17 pnl tf12it0nn2 LVTTL - Ext Data E12 ext bus data16 pnl tf12it0nn2 LVTTL - Ext Data D12 pnl gcs t05 pnl gcs - - VSS C12 ext bus data15 pnl tf12it0nn2 LVTTL - Ext Data B12 ext bus data14 pnl tf12it0nn2 LVTTL - Ext Data A12 ext bus data13 pnl tf12it0nn2 LVTTL - Ext Data F12 ext bus data12 pnl tf12it0nn2 LVTTL - Ext Data G12 pnl go t03 pnl go - - VSSIO H13 ext bus data11 pnl tf12it0nn2 LVTTL - Ext Data G13 ext bus data10 pnl tf12it0nn2 LVTTL - Ext Data F13 ext bus data9 pnl tf12it0nn2 LVTTL - Ext Data A13 ext bus data8 pnl tf12it0nn2 LVTTL - Ext Data B13 pnl vop t03 pnl vop 3.3V - VDDIO C13 ext bus data7 pnl tf12it0nn2 LVTTL - Ext Data D13 ext bus data6 pnl tf12it0nn2 LVTTL - Ext Data E13 pnl gcs t06 pnl gcs - - VSS G14 ext bus data5 pnl tf12it0nn2 LVTTL - Ext Data A14 ext bus data4 pnl tf12it0nn2 LVTTL - Ext Data B14 ext bus data3 pnl tf12it0nn2 LVTTL - Ext Data C14 ext bus data2 pnl tf12it0nn2 LVTTL - Ext Data D14 pnl vc t04 pnl vc 1.0V - VDD E14 ext bus data1 pnl tf12it0nn2 LVTTL - Ext Data F14 ext bus data0 pnl tf12it0nn2 LVTTL - Ext Data A15 pnl gcs t07 pnl gcs - - VSS B15 ext bus addr31 pnl tf12it0nn2 LVTTL - Ext Address C15 ext bus addr30 pnl tf12it0nn2 LVTTL - Ext Address D15 pnl go t04 pnl go - - VSSIO E15 ext bus addr29 pnl tf12it0nn2 LVTTL - Ext Address F15 ext bus addr28 pnl tf12it0nn2 LVTTL - Ext Address A16 pnl vc t05 pnl vc 1.0V - VDD B16 ext bus addr27 pnl tf12it0nn2 LVTTL - Ext Address C16 ext bus addr26 pnl tf12it0nn2 LVTTL - Ext Address D16 pnl vop t04 pnl vop 3.3V - VDDIO E16 ext bus addr25 pnl tf12it0nn2 LVTTL - Ext Address G15 ext bus addr24 pnl tf12it0nn2 LVTTL - Ext Address A17 pnl go t05 pnl go - - VSSIO B17 ext bus addr23 pnl tf12it0nn2 LVTTL - Ext Address C17 ext bus addr22 pnl tf12it0nn2 LVTTL - Ext Address D17 pnl gcs t08 pnl gcs - - VSS E17 ext bus addr21 pnl tf12it0nn2 LVTTL - Ext Address F16 ext bus addr20 pnl tf12it0nn2 LVTTL - Ext Address A18 pnl vc t06 pnl vc 1.0V - VDD B18 ext bus addr19 pnl tf12it0nn2 LVTTL - Ext Address C18 ext bus addr18 pnl tf12it0nn2 LVTTL - Ext Address D18 pnl gcs t09 pnl gcs - - VSS E18 ext bus addr17 pnl tf12it0nn2 LVTTL - Ext Address F17 ext bus addr16 pnl tf12it0nn2 LVTTL - Ext Address A19 pnl go t06 pnl go - - VSSIO B19 ext bus addr15 pnl tf12it0nn2 LVTTL - Ext Address C19 ext bus addr14 pnl tf12it0nn2 LVTTL - Ext Address D19 pnl gcs t10 pnl gcs - - VSS E19 ext bus addr13 pnl tf12it0nn2 LVTTL - Ext Address F18 ext bus addr12 pnl tf12it0nn2 LVTTL - Ext Address A20 pnl vop t05 pnl vop 3.3V - VDDIO B20 ext bus addr11 pnl tf12it0nn2 LVTTL - Ext Address C20 ext bus addr10 pnl tf12it0nn2 LVTTL - Ext Address D20 pnl vc t07 pnl vc 1.0V - VDD E20 ext bus addr9 pnl tf12it0nn2 LVTTL - Ext Address A21 ext bus addr8 pnl tf12it0nn2 LVTTL - Ext Address B21 pnl gcs t11 pnl gcs - - VSS C21 ext bus addr7 pnl tf12it0nn2 LVTTL - Ext Address A22 ext bus addr6 pnl tf12it0nn2 LVTTL - Ext Address

16 Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 350 B22 ext bus addr5 pnl tf12it0nn2 LVTTL - Ext Address B23 ext bus addr4 pnl tf12it0nn2 LVTTL - Ext Address C22 ext bus addr3 pnl tf12it0nn2 LVTTL - Ext Address D21 ext bus addr2 pnl tf12it0nn2 LVTTL - Ext Address F19 pnl gcs l00 pnl gcs - - VSS G19 ext bus mask3 pnl tf12it0nn2 LVTTL - Ext Mask 3 Pull-Up C23 ext bus mask2 pnl tf12it0nn2 LVTTL - Ext Mask 2 Pull-Up F20 ext bus mask1 pnl tf12it0nn2 LVTTL - Ext Mask 1 Pull-Up D22 ext bus mask0 pnl tf12it0nn2 LVTTL - Ext Mask 0 Pull-Up E21 pnl vc l00 pnl vc 1.0V - VDD G18 chip id0 pnl tf12it0nn2 LVTTL - Chip ID 0 Pull-Up G17 ext bus bus req2 pnl tf12it0nn2 LVTTL - Ext Request 2 Pull-Up Active Low 362 D23 ext bus bus req1 pnl tf12it0nn2 LVTTL - Ext Request 1 Pull-Up Active Low 363 G16 ext bus bus req0 pnl tf12it0nn2 LVTTL - Ext Request 0 Pull-Up Active Low 364 E22 pnl gcs l01 pnl gcs - - VSS F21 chip id1 pnl tf12it0nn2 LVTTL - Chip ID 1 Pull-Down G20 ext bus bus grnt2 pnl tf12it0nn2 LVTTL - Ext Grant 2 Pull-Up Active Low 367 H18 ext bus bus grnt1 pnl tf12it0nn2 LVTTL - Ext Grant 1 Pull-Up Active Low 368 E23 ext bus bus grnt0 pnl tf12it0nn2 LVTTL - Ext Grant 0 Pull-Up Active Low 369 H19 pnl go l00 pnl go - - VSSIO H17 ext bus cs3 pnl tf12it0nn2 LVTTL - Ext CS 3 Pull-Up Active Low 371 F22 ext bus cs2 pnl tf12it0nn2 LVTTL - Ext CS 2 Pull-Up Active Low 372 H20 ext bus cs1 pnl tf12it0nn2 LVTTL - Ext CS 1 Pull-Up Active Low 373 G21 ext bus cs0 pnl tf12it0nn2 LVTTL - Ext CS 0 Pull-Up Active Low 374 F23 pnl vop l00 pnl vop 3.3V - VDDIO J18 ext bus oe pnl tf12it0nn2 LVTTL - Ext Output Enable Pull-Up Active Low 376 J17 ext bus as pnl tf12it0nn2 LVTTL - Ext Address Strobe Pull-Up Active Low 377 G22 ext bus rw pnl tf12it0nn2 LVTTL - Ext Read/Write Pull-Up J19 ext bus rdy pnl tf12it0nn2 LVTTL - Ext Ready Pull-Up Active Low 379 H21 pnl vc l01 pnl vc 1.0V - VDD G23 ext bus br req2 pnl tf12it0nn2 LVTTL - Ext Burst Req 2 Pull-Up J20 ext bus br req1 pnl tf12it0nn2 LVTTL - Ext Burst Req 1 Pull-Up K17 ext bus br req0 pnl tf12it0nn2 LVTTL - Ext Burst Req 0 Pull-Up K18 ext bus br ack2 pnl tf12it0nn2 LVTTL - Ext Burst Ack 2 Pull-Up H22 ext bus br ack1 pnl tf12it0nn2 LVTTL - Ext Burst Ack 1 Pull-Up J21 ext bus br ack0 pnl tf12it0nn2 LVTTL - Ext Burst Ack 0 Pull-Up H23 pnl gcs l02 pnl gcs - - VSS L16 ext init size mode0 pnl tf12it0nn2 LVTTL - Ext Init Size 0 Pull-Down K19 ext init size mode1 pnl tf12it0nn2 LVTTL - Ext Init Size 1 Pull-Down L17 ext bus auto rdy en pnl tf12it0nn2 LVTTL - Auto Ready Enable Pull-Up Active Low 390 K20 debug en pnl it2pu8 LVTTL - Debug Enable Pull-Up Active Low 391 J22 ext bus dma ack1 pnl tf12it0nn2 LVTTL - Ext DMA Ack 1 Pull-Up Active Low 392 J23 ext bus dma ack0 pnl tf12it0nn2 LVTTL - Ext DMA Ack 0 Pull-Up Active Low 393 M17 ext bus dma req1 pnl tf12it0nn2 LVTTL - Ext DMA Req 1 Pull-Up Active Low 394 K21 ext bus dma req0 pnl tf12it0nn2 LVTTL - Ext DMA Req 0 Pull-Up Active Low 395 L18 pnl vc l02 pnl vc 1.0V - VDD K22 ext bus irq1 pnl tf12it0nn2 LVTTL - Ext IRQ 1 Pull-Down Active High 397 M18 ext bus irq0 pnl tf12it0nn2 LVTTL - Ext IRQ 0 Pull-Down Active High 398 K23 pnl go l01 pnl go - - VSSIO L19 ext bus clk pnl clk0nn8 LVTTL - Ext Clock L20 pnl vop l01 pnl vop 3.3V - VDDIO L21 ext init sync mode0 pnl tf12it0nn2 LVTTL - Ext Init Sync Mode 0 Pull-Down Active High 402 L22 chip id2 pnl tf12it0nn2 LVTTL - Chip ID 2 Pull-Down L23 pnl vc l03 pnl vc 1.0V - VDD M19 chip id3 pnl tf12it0nn2 LVTTL - Chip ID 3 Pull-Down M20 ext master cs pnl tf12it0nn2 LVTTL - Ext Master CS Pull-Up Active Low 406 M21 pnl gcs l04 pnl gcs - - VSS M22 pnl go bkp l00 pnl go - - VSSIO M23 pwm in1 pnl it2nn2 LVTTL - PWM Input N18 pwm in0 pnl it2nn2 LVTTL - PWM Input N19 pnl vc bkp l00 pnl vc 1.0V - VDD N20 pwm out5 pnl tf04it0nn2 LVTTL - PWM Output N21 pwm out4 pnl tf04it0nn2 LVTTL - PWM Output N22 pwm out3 pnl tf04it0nn2 LVTTL - PWM Output N23 pnl gcs bkp l00 pnl gcs - - VSS

17 2 Pin Assignment Pin Bump Pin Name Master Cell Level Dir. Description Termination Polarity 415 N17 pwm out2 pnl tf04it0nn2 LVTTL - PWM Output N16 pwm out1 pnl tf04it0nn2 LVTTL - PWM Output P18 pwm out0 pnl tf04it0nn2 LVTTL - PWM Output P19 pnl vop bkp l00 pnl vop 3.3V - VDDIO P20 pulse counter pz1 pnl it2nn2 LVTTL - Pulse Counter CH1 PZ P23 pulse counter pb1 pnl it2nn2 LVTTL - Pulse Counter CH1 PB P22 pulse counter pa1 pnl it2nn2 LVTTL - Pulse Counter CH1 PA P21 pnl vc bkp l01 pnl vc 1.0V - VDD R18 pulse counter pz0 pnl it2nn2 LVTTL - Pulse Counter CH0 PZ R19 pulse counter pb0 pnl it2nn2 LVTTL - Pulse Counter CH0 PB R20 pulse counter pa0 pnl it2nn2 LVTTL - Pulse Counter CH0 PA R23 pnl gcs bkp l01 pnl gcs - - VSS R22 rtc pad rtc clk pnl clk0nn8 LVTTL - RTC Clock R21 rtc pad rtc reset pnl it2pu8 LVTTL - RTC Reset Pull-Up Active Low 429 T19 rtc pad rtc hold pnl it2pu8 LVTTL - RTC Hold Pull-Up Active Low 430 T23 pnl vc bkp l02 pnl vc 1.0V - VDD T22 clk iopad reset in pnl it2pu2 LVTTL - Reset Input Pull-Up Active Low 432 T21 clk iopad reset out pnl tf12it0nn2 LVTTL - Reset Output T20 pnl go bkp l01 pnl go - - VSSIO U21 clk iopad clk out pnl tf12it0nn2 LVTTL - Clock Output U23 clk iopad FIN pnl it2nn2 LVTTL - PLL FIN U22 clk iopad FOUT pnl tf12it0nn2 LVTTL - PLL FOUT U20 pnl vop bkp l01 pnl vop 3.3V - VDDIO T18 clk iopad F0 pnl it2pd2 LVTTL - PLL F V21 clk iopad F1 pnl it2pu2 LVTTL - PLL F V22 clk iopad F2 pnl it2pu2 LVTTL - PLL F V23 pnl vc bkp l03 pnl vc 1.0V - VDD U19 clk iopad F3 pnl it2pu2 LVTTL - PLL F P17 clk iopad F4 pnl it2pd2 LVTTL - PLL F V20 clk iopad F5 pnl it2pd2 LVTTL - PLL F W21 pnl gcs bkp l02 pnl gcs - - VSS W22 clk iopad BP pnl it2pd2 LVTTL - PLL BP W23 pnl vc bkp l04 pnl vc 1.0V - VDD R17 clk iopad R0 pnl it2pd2 LVTTL - PLL R P16 clk iopad R1 pnl it2pu2 LVTTL - PLL R U18 pnl gcs bkp l03 pnl gcs - - VSS W20 clk iopad R2 pnl it2pd2 LVTTL - PLL R Y22 clk iopad R3 pnl it2pd2 LVTTL - PLL R Y23 pnl vop bkp l02 pnl vop 3.3V - VDDIO Y21 clk iopad OEB pnl it2pd2 LVTTL - PLL OEB V19 pnl go bkp l02 pnl go - - VSSIO V18 clk iopad OD pnl it2pd2 LVTTL - PLL OD T17 pnl gcs bkp l04 pnl gcs - - VSS R16 clk iopad PD pnl it2pd2 LVTTL - PLL PD AA23 clk iopad PVSS2P PVSS2P - - IO Analog VSS AA22 clk iopad PVDD2P PVDD2P 3.3V - IO Analog VDD Y20 clk iopad PVDD1P1 PVDD1P 3.3V - PLL Analog VDD AA21 clk iopad PVDD1P0 PVDD1P 3.3V - PLL Analog VDD W19 clk iopad PVSS1PC0 PVSS1PC - - PLL Digital VSS AB23 clk iopad PVSS1P1 PVSS1P - - PLL Analog VSS AB22 clk iopad PVSS1P0 PVSS1P - - PLL Analog VSS AB21 clk iopad PVDD1PC0 PVDD1PC 1.0V - PLL Digital VDD

18 17 3 Instruction : LB LH LW LBU LHU SB SH SW LWC1 SWC1 ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI ADD ADDU SUB SUBU AND OR XOR NOR SLL SRL SRA SLLV SRLV SRAV ADD.fmt SUB.fmt MUL.fmt DIV.fmt ABS.fmt MOV.fmt NEG.fmt ROUND.W.fmt TRUNC.W.fmt CEIL.W.fmt FLOOR.W.fmt CVT.S.fmt CVT.D.fmt CVT.W.fmt C.cond.fmt J JAL JR JALR BEQ BNE BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL BC1F BC1T SYSCALL BREAK MULT MULTU DIV DIVU MTIMM MFIMM MTDMM MFDMM MTC0 MFC0 MTC1 MFC1 CTC1 CFC1 ERET 3.2 MIPSI

19 3 Instruction LDC1 SDC1 RFE 3.2: R op rs rt rd 10 6 shamt 5 0 func 6bit 5bit 5bit 5bit 5bit 6bit I op rs rt 15 0 address/immediate 6bit 5bit 5bit 16bit J op 6bit 25 0 target 24bit Opecode OP 25 0 OP[28:26] SPECIAL REGIMM J JAL BEQ BNE BLEZ BGTZ 001 ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI 010 COP0 COP1 OP[31:29] LB LH LW LBU LHU 101 SB SH SW 110 LWC1 111 SWC1 18

20 Function SPECIAL FUNC FUNC[2:0] SLL SRL SRA SLLV SRLV SRAV 001 JR JALR SYSCALL BREAK 010 FUNC[5:3] 011 ERET 100 ADD ADDU SUB SUBU AND OR XOR NOR 101 SLT SLTU Rt REGIMM RT 15 0 RT[18:16] BLTZ BGEZ 01 RT[20:19] 10 BLTZAL BGEZAL Rs COP RS 20 0 RS[23:21] MF CF MT CT 01 BC RS[25:24] 10 S D W 11 19

21 3 Instruction LB (Load Byte) : base rt offset LB Format: LB rt, offset(base) Description: GPR[rt] MEMORY[GPR[base]+offset] Exception: None Programming Notes: 8bit 32bit LBU (Load Byte Unsigned) : base rt offset LBU Format: LBU rt, offset(base) Description: GPR[rt] MEMORY[GPR[base]+offset] Exception: None Programming Notes: 8bit 20

22 3.4. LH (Load Halfword) : base rt offset LH Format: LH rt, offset(base) Description: GPR[rt] MEMORY[GPR[base]+offset] Exception: Address Miss Aligned Programming Notes: 16bit 32bit LHU (Load Halfword Unsigned) : base rt offset LHU Format: LHU rt, offset(base) Description: GPR[rt] MEMORY[GPR[base]+offset] Exception: Address Miss Aligned Programming Notes: 16bit 21

23 3 Instruction LW (Load Word) : base rt offset LW Format: LW rt, offset(base) Description: GPR[rt] MEMORY[GPR[base]+offset] Exception: Address Miss Aligned Programming Notes: 32bit SB (Store Byte) : base rt offset SB Format: SB rt, offset(base) Description: MEMORY[GPR[base]+offset] GPR[rt] Exception: None Programming Notes: 8bit 22

24 3.4. SH (Store Halfword) : base rt offset SH Format: SH rt, offset(base) Description: MEMORY[GPR[base]+offset] GPR[rt] Exception: Address Miss Aligned Programming Notes: 16bit SW (Store Word) : base rt offset SW Format: SW rt, offset(base) Description: MEMORY[GPR[base]+offset] GPR[rt] Exception: Address Miss Aligned Programming Notes: 32bit 23

25 3 Instruction LWC1 (Load Word to Floating Point) : 32bit base rt offset LWC1 Format: LWC1 ft, offset(base) Description: FPR[rt] MEMORY[GPR[base]+offset] Exception: Address Miss Aligned Programming Notes: 32bit SWC1 (Store Word from Floating Point) : 32bit base rt offset SWC1 Format: SWC1 ft, offset(base) Description: MEMORY[GPR[base]+offset] FPR[rt] Exception: Address Miss Aligned Programming Notes: 32bit 24

26 ADDI (Add Immediate Word) : rs rt immediate ADDI Format: ADDI rt, rs, immediate Description: GPR[rt] GPR[rs] + sign extention( immediate ) Exception: Arithmetic Overflow Programming Notes: 32bit ADDIU (Add Immediate Unsigned Word) : rs rt immediate ADDIU Format: ADDIU rt, rs, immediate Description: GPR[rt] GPR[rs] + sign extention( immediate ) Exception: None Programming Notes: 32bit 25

27 3 Instruction SLTI (Set on Less Than Immediate) : rs rt immediate SLTI Format: SLTI rt, rs, immediate Description: GPR[rt] ( GPR[rs] < sign extention( immediate ) ) Exception: None Programming Notes: 32bit rs immediate rd 1 0 SLTIU(Set on Less Than Immediate Unsigned) : rs rt immediate SLTIU Format: SLTIU rt, rs, immediate Description: GPR[rt] ( GPR[rs] < sign extention( immediate ) ) Exception: None Programming Notes: 32bit rs immediate rd

28 3.4. ANDI (And Immediate) : rs rt immediate ANDI Format: ANDI rt, rs, immediate Description: GPR[rt] GPR[rs] AND zero extention( immediate ) Exception: None Programming Notes: 32bit ORI (Or Immediate) : rs rt immediate ORI Format: ORI rt, rs, immediate Description: GPR[rt] GPR[rs] OR zero extention( immediate ) Exception: None Programming Notes: 32bit 27

29 3 Instruction XORI (Exclusive Or Immediate) : rs rt immediate XORI Format: XORI rt, rs, immediate Description: GPR[rt] GPR[rs] XOR zero extention( immediate ) Exception: None Programming Notes: 32bit LUI (Load Upper Immediate) : rt immediate LUI 0 Format: LUI rt, immediate Description: GPR[rt] { immediate, 0 16 } Exception: None Programming Notes: immediate 32bit 16bit 28

30 ALU ADD (Add Word) : rs rt rd SPECIAL 0 ADD Format: ADD rd, rs, rt Description: GPR[rd] GPR[rs] + GPR[rt] Exception: Arithmetic Overflow Programming Notes: 32bit ADDU (Add Unsigned Word) : rs rt rd SPECIAL 0 ADDU Format: ADDU rd, rs, rt Description: GPR[rd] GPR[rs] + GPR[rt] Exception: None Programming Notes: 32bit 29

31 3 Instruction SUB (Subtract Word) : rs rt rd SPECIAL 0 SUB Format: SUB rd, rs, rt Description: GPR[rd] GPR[rs] GPR[rt] Exception: Arithmetic Overflow Programming Notes: 32bit SUBU (Subtract Unsigned Word) : rs rt rd SPECIAL 0 SUBU Format: SUBU rd, rs, rt Description: GPR[rd] GPR[rs] GPR[rt] Exception: None Programming Notes: 32bit 30

32 3.4. AND (And) : rs rt rd SPECIAL 0 AND Format: AND rd, rs, rt Description: GPR[rd] GPR[rs] AND GPR[rt] Exception: None Programming Notes: 32bit OR (Or) : rs rt rd SPECIAL 0 OR Format: OR rd, rs, rt Description: GPR[rd] GPR[rs] OR GPR[rt] Exception: None Programming Notes: 32bit 31

33 3 Instruction XOR (Exclusive Or) : rs rt rd SPECIAL 0 XOR Format: XOR rd, rs, rt Description: GPR[rd] GPR[rs] XOR GPR[rt] Exception: None Programming Notes: 32bit NOR (Not Or) : rs rt rd SPECIAL 0 NOR Format: NOR rd, rs, rt Description: GPR[rd] GPR[rs] NOR GPR[rt] Exception: None Programming Notes: 32bit 32

34 3.4. SLT (Set on Less Than) : rs rt rd SPECIAL 0 SLT Format: SLT rd, rs, rt Description: GPR[rd] ( GPR[rs] < GPR[rt] ) Exception: None Programming Notes: 32bit rs rt rd 1 0 SLTU (Set on Less Than Unsigned) : rs rt rd SPECIAL 0 SLTU Format: SLTU rd, rs, rt Description: GPR[rd] ( GPR[rs] < GPR[rt] ) Exception: None Programming Notes: 32bit rs rt rd

35 3 Instruction SLL (Shift Word Left Logical) : rt rd sa SPECIAL SHIFT SLL Format: SLL rd, rt, sa Description: GPR[rd] GPR[rt] << sa Exception: None Programming Notes: 32bit SRL (Shift Word Right Logical) : rt rd sa SPECIAL SHIFT SRL Format: SRL rd, rt, sa Description: GPR[rd] GPR[rt] >> sa (logical) Exception: None Programming Notes: 32bit 34

36 3.4. SRA (Shift Word Right Arithmetic) : rt rd sa SPECIAL 0 SRA Format: SRA rd, rt, sa Description: GPR[rd] GPR[rt] >> sa (arithmetic) Exception: None Programming Notes: 32bit SLLV (Shift Word Left Logical Variable) : rs rt rd SPECIAL SHIFT SLLV Format: SLLV rd, rt, rs Description: GPR[rd] GPR[rt] << GPR[rs] Exception: None Programming Notes: 32bit 35

37 3 Instruction SRLV (Shift Word Right Logical Variable) : rs rt rd SPECIAL SHIFT SRLV Format: SRLV rd, rt, rs Description: GPR[rd] GPR[rt] >> GPR[rs] (logical) Exception: None Programming Notes: 32bit SRAV (Shift Word Right Arithmetic Variable) : rs rt rd SPECIAL 0 SRAV Format: SRAV rd, rt, rs Description: GPR[rd] GPR[rt] >> GPR[rs] (arithmetic) Exception: None Programming Notes: 32bit 36

38 J (Jump) : J 25 0 target Format: J target Description: PC PC target 00 Exception: None Programming Notes: JAL (Jump and Link) : J 25 0 target Format: JAL target Description: GPR[31] pc + 0x04 PC PC target 00 Exception: None Programming Notes: GPR[31] 37

39 3 Instruction JR (Jump Register) : rs SPECIAL 0 JR Format: JR rs Description: PC target Exception: None Programming Notes: JALR (Jump and Link Register) : rs rd SPECIAL 0 0 JALR Format: JR rs (rd = 31 implied) JR rd, rs Description: GPR[rd] PC+ 0x04 PC GPR[rs] Exception: None Programming Notes: rd 38

40 BEQ (Branch on Equal) : rs rt offset BEQ Format: BEQ rs, rt, offset Description: if GPR[rs] = GPR[rt] then branch Exception: None Programming Notes: rs rt BNE (Branch on Not Equal) : rs rt offset BNE Format: BNE rs, rt, offset Description: if GPR[rs] GPR[rt] then branch Exception: None Programming Notes: rs rt 39

41 3 Instruction BLEZ (Branch on Less Than or Equal to Zero) : rs offset BLEZ 0 Format: BLEZ rs, offset Description: if GPR[rs] 0 then branch Exception: None Programming Notes: rs 0 BGTZ(Branch on Greater Than Zero) : rs offset BGTZ 0 Format: BGTZ rs, offset Description: if GPR[rs] > 0 then branch Exception: None Programming Notes: rs 0 40

42 3.4. BLTZ (Branch on Less Than Zero) : rs offset REGIMM BLTZ Format: BLTZ rs, offset Description: if GPR[rs] < 0 then branch Exception: None Programming Notes: rs 0 BGEZ (Branch on Greater Than or Equal to Zero) : rs offset REGIMM BGEZ Format: BGEZ rs, offset Description: if GPR[rs] 0 then branch Exception: None Programming Notes: rs 0 41

43 3 Instruction BLTZAL (Branch on Less Than Zero and Link) : rs offset REGIMM BLTZAL Format: BLTZAL rs, offset Description: if GPR[rs] < 0 then procedure call Exception: None Programming Notes: rs 0 GPR[31] BGEZAL (Branch on Greater Than or Equal to Zero and Link) : rs offset REGIMM BGEZAL Format: BGEZAL rs, offset Description: if GPR[rs] 0 then procedure call Exception: None Programming Notes: rs 0 GPR[31] 42

44 System Call / Break Point SYSCALL (System Call) : SPECIAL Format: SYSCALL SYSCALL Description: signal exception( System Call ) Exception: System Call Programming Notes: BREAK (Break Point) : SPECIAL Format: BREAK BREAK Description: signal exception( Breakpoint ) Exception: Break Point Programming Notes: 43

45 3 Instruction MFC0 (Move from Coprocessor0) : rt rd COP0 MF 0 Format: MFC0 rt, rd Description: GPR[rt] CTRL[rd] Exception: Coprocessor Unusable Programming Notes: MTC0 (Move to Coprocessor0) : rt rd COP0 MT 0 Format: MTC0 rt, rd Description: CTRL[rd] GPR[rt] Exception: Coprocessor Unusable Programming Notes: 44

46 3.4. MFIMM (Move from Instruction MMU Control Register) : MMU rt rd COP0 MF 0 IMMU Format: MFIMM rt, rd Description: GPR[rt] IMMU[rd] Exception: Coprocessor Unusable Programming Notes: MMU MTIMM (Move to Instruction MMU Control Register) : MMU rt rd COP0 MT 0 IMMU Format: MTIMM rt, rd Description: IMMU[rt] GPR[rd] Exception: Coprocessor Unusable Programming Notes: MMU 45

47 3 Instruction MFDMM (Move from Data MMU Control Register) : MMU rt rd COP0 MF 0 DMMU Format: MFDMM rt, rd Description: GPR[rt] DMMU[rd] Exception: Coprocessor Unusable Programming Notes: MMU MTDMM (Move to Data MMU Control Register) : MMU rt rd COP0 MT 0 DMMU Format: MTDMM rt, rd Description: DMMU[rt] GPR[rd] Exception: Coprocessor Unusable Programming Notes: MMU 46

48 3.4. ERET (Exception Return) : COP0 Format: ERET ERET Description: KUc KUp IEc IEp Exception: Coprocessor Unusable Programming Notes: KUp IEp KUc IEc ERET PC JR FPU MFC1 (Move from Coprocessor1) : rt fs COP1 MF 0 Format: MFC1 rt, fs Description: GPR[rt] FCR[fs] Exception: Coprocessor Unusable Programming Notes: 47

49 3 Instruction MTC1 (Move to Coprocessor1) : rt fs COP1 MT 0 Format: MTC0 rt, fs Description: FPR[fs] GPR[rt] Exception: Coprocessor Unusable Programming Notes: CFC1 (Move Control Word from Coprocessor1) : rt fs COP1 CFC1 0 Format: CFC1 rt, fs Description: GPR[rt] FCR[fs] Exception: Coprocessor Unusable Programming Notes: FPU 48

50 3.4. CTC1 (Move Control Word to Coprocessor1) : rt fs COP1 CTC1 0 Format: CTC1 rt, fs Description: FCR[fs] GPR[rt] Exception: Coprocessor Unusable Programming Notes: FPU ADD.fmt (Floating Point Add) : fmt ft fs fd COP1 FADD Format: ADD.S fd, fs, ft (fmt = 10000) ADD.D fd, fs, ft (fmt = 10001) Description: FPR[fd] FPR[fs] + FPR[ft] Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Programming Notes: 49

51 3 Instruction SUB.fmt (Floating Point Subtract) : fmt fs ft fd COP1 FSUB Format: SUB.S fd, fs, ft (fmt = 10000) SUB.D fd, fs, ft (fmt = 10001) Description: FPR[fd] FPR[fs] FPR[ft] Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Programming Notes: 50

52 3.4. MUL.fmt (Floating Point Multiply) : fmt ft fs fd COP1 FMUL Format: MUL.S fd, fs, ft (fmt = 10000) MUL.D fd, fs, ft (fmt = 10001) Description: FPR[fd] FPR[fs] FPR[ft] Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Programming Notes: 51

53 3 Instruction DIV.fmt (Floating Point Divide) : fmt fs ft fd COP1 FDIV Format: DIV.S fd, fs, ft (fmt = 10000) DIV.D fd, fs, ft (fmt = 10001) Description: FPR[fd] FPR[fs] / FPR[ft] Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Floating Point Divide By 0 Programming Notes: ABS.fmt (Floating Point Absolute Value) : fmt fs ft fd COP1 FABS Format: ABS.S fd, fs (fmt = 10000) ABS.D fd, fs (fmt = 10001) Description: FPR[fd] abs(fpr[fs]) Exception: Floating Point Invalid Operation Programming Notes: 52

54 3.4. MOV.fmt (Floating Point Move) : fmt fs ft fd COP1 FMOV Format: MOV.S fd, fs, ft (fmt = 10000) MOV.D fd, fs, ft (fmt = 10001) Description: FPR[fd] FPR[fs] Exception: Floating Point Invalid Operation Programming Notes: NEG.fmt (Floating Point Negate) : fmt fs ft fd COP1 FNEG Format: NEG.S fd, fs (fmt = 10000) NEG.D fd, fs (fmt = 10001) Description: FPR[fd] (FPR[fs]) Exception: Floating Point Invalid Operation Programming Notes: 53

55 3 Instruction CVT.S.fmt (Floating Point Convert to Single Floating Point) : fmt fs fd COP1 0 CVTS Format: CVT.S.D fd, fs (fmt = 10001) CVT.S.W fd, fs (fmt = 10100) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Programming Notes: 54

56 3.4. CVT.W.fmt (Floating Point Convert to Word Fixed Point) : fmt fs fd COP1 0 CVTW Format: CVT.W.S fd, fs (fmt = 10000) CVT.W.D fd, fs (fmt = 10001) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Floating Point Underflow Programming Notes: 55

57 3 Instruction ROUND.W.fmt (Floating Point Round to Word Fixed Point) : fmt fs fd COP1 0 ROUNDW Format: ROUND.W.S fd, fs (fmt = 10000) ROUND.W.D fd, fs (fmt = 10001) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Programming Notes: TRUNC.W.fmt (Floating Point Truncate to Word Fixed Point) : fmt fs fd COP1 0 TRUNCW Format: TRUNC.W.S fd, fs (fmt = 10000) TRUNC.W.D fd, fs (fmt = 10001) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Programming Notes: 56

58 3.4. CEIL.W.fmt (Floating Point Ceiling to Word Fixed Point) : fmt fs fd COP1 0 CEILW Format: CEIL.W.S fd, fs (fmt = 10000) CEIL.W.D fd, fs (fmt = 10001) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Programming Notes: FLOOR.W.fmt (Floating Point Floor Convert to Word Fixed Point) : fmt fs fd COP1 0 FLOORW Format: FLOOR.W.S fd, fs (fmt = 10000) FLOOR.W.D fd, fs (fmt = 10001) Description: FPR[fd] convert and round(fpr[fs]) Exception: Floating Point Invalid Operation Floating Point Inexact Floating Point Overflow Programming Notes: 57

59 3 Instruction C.cond.fmt (Floating Point Compare) : fmt ft fs cond COP1 0 FC Format: C.cond.S fs, ft (fmt = 10000) C.cond.D fs, ft (fmt = 10001) Description: FCR[31] FPR[fs] compare cond FPR[ft] Exception: Floating Point Invalid Operation Programming Notes: BC1F (Branch on Floating Point False) : offset COP1 BC BC1F Format: BC1F offset Description: if C(FCR[31]) = 0 then branch Exception: None Programming Notes: FCR[31] Condition 0 58

60 3.4. BC1T (Branch on Floating Point True) : offset COP1 BC BC1T Format: BC1T offset Description: if C(FCR[31]) = 1 then branch Exception: None Programming Notes: FCR[31] Condition 1 59

61

62 61 4 Exception : 00 IO 01 ITLB ITLB 02 ITLB 03 DTLB DTLB 04 DTLB syscall 09 break FPU 15 No Exp No Exception Exception Code Exception Program Counter CPU Exception Vector

63 4 Exception : IRQ IRQ 00 Non Maskable Interrupt CH 0 04 CH 1 05 CH 2 06 CH 3 07 UART CH 0 08 UART CH 1 09 GPIO 10 I2C 11 SPI 12 RTC 13 External Bus IRQ 0 14 External Bus IRQ 1 15 PWM Out CH 0 16 PWM Out CH 1 17 PWM Out CH 2 18 PWM Out CH 3 19 PWM Out CH 4 20 PWM Out CH 5 21 PWM In CH 0 22 PWM In CH 1 23 Pulse Counter CH 0 24 Pulse Counter CH 1 25 DMAC CH 0 26 DMAC CH 1 27 Reserved 28 Reserved 29 Responsive Link 30 PCI 31 Software IRQ Interrupt Sense bit 1 62

64 63 5 CPU Control Register : 00 Cause RW 01 Status RW 02 Pending RW 03 Interrupt Mask RW 04 Exception PC RW 05 Exception Vector RW 06 Invalid Address RW 07 Cache RW 08 IRQ Polarity RW IRQ 09 IRQ Trigger RW IRQ 10 Software IRQ RW IRQ 11 Thread ID RW ID 12 Invalid Global Address RW Reserved NA Reserved 26 Clock Counter Low R Clock Counter High R Instruction Counter Low R Instruction Counter High R Global Address R 31 CPU Information R CPU

65 5 CPU Control Register 5.2 Cause Register Number: 0 31 D 30 4 Reserved 3 0 EXP CODE 31 Delay Bit (D) Default: 0x Exception Code (EXP CODE) Default: 0x0 64

66 5.2. Status Register Number: ICE DCE Reserved MODEo IEo MODEp IEp MODEc IEc 31 I-Cache Enable (ICE) Default: 0x1 0 I-Cache 30 D-Cache Enable (DCE) Default: 0x1 0 D-Cache 8-7 Execution Mode Old (MODEo) Default: 0x0 (2) MODEp 6 Interrupt Enable Old (IEo) Default: 0x0 (2) IEp 5-4 Execution Mode Previous (MODEp) Default: 0x0 (3) MODEc ERET MODEo 3 Interrupt Enable Previous (IEp) Default: 0x0 (3) IEc ERET IEo 2-1 Execution Mode Current (MODEc) Default: 0x0 Kernel Mode Kernel Mode : 2 b00, Supervisor Mode : 2 b01, User Mode : 2 b10, Reserved : 2 b11 0 Interrupt Enable Current (IEc) Default: 0x0 1 IRQ ( ) 0 65

67 5 CPU Control Register Pending Register Number: Pending IRQ 31-0 Pending IRQ Default: 0x0 N IRQ N IRQ IRQ 1 1 IRQ Interrupt Mask Register Number: INT MASK 0 0 7:1 Interrupt Mask (INT MASK) Default: 0x7F N IRQ N 1 0 Interrupt Mask (INT MASK) Default: 0x0 IRQ0 (Non Maskable Interrupt : NMI) Exception Program Counter Register Number: EPC :2 Exception Program Counter (EPC) Default: 0x0 Exception Vector Register Number: EXP VECTOR :2 Exception Vector (EXP VECTOR) Default: 0x0 66

68 5.2. Invalid Address Register Number: INV ADDR 31-0 Invalid Address (INV ADDR) Default: 0x0 Cache Control Register Number: Reserved I INITI INVD INIT D INV D SYNC 4 I-Cache Initialize (I INIT) Default: 0x1 0 I-Cache I-Cache 0 Status Register I-Cache Enable 0 3 I-Cache Invalid (I INV) Default: 0x1 0 I-Cache 2 D-Cache Initialize (D INIT) Default: 0x1 0 D-Cache D-Cache 0 Status Register D-Cache Enable 0 1 D-Cache Invalid (D INV) Default: 0x1 0 D-Cache 0 D-Cache Sync (D SYNC) Default: 0x1 0 D-Cache IRQ Polarity Register Number: IRQ POLARITY 31:0 IRQ Polarity (IRQ POLARITY) Default: 0xffffffff N IRQ N 0 IRQ Low (IRQ Trigger ) 1 IRQ High 67

69 5 CPU Control Register IRQ Trigger Register Number: IRQ TRIGGER 31:0 IRQ Trigger (IRQ TRIGGER) Default: 0x0 N IRQ N 0 IRQ 1 IRQ Software IRQ Register Number: SW IRQ 31:0 Software IRQ (SW IRQ) Default: 0x0 N SW IRQ N 1 Thread ID Register Number: TH ID 31:0 Thread ID (TH ID) Default: 0x0 ID Invalid Global Address Register Number: INV GADDR 31-0 Invalid Global Address (INV GADDR) Default: 0x0 68

70 5.2. Clock Counter Register Number: 26, CLK CNT 31:0 Clock Counter (CLK CNT) Default: 0x Instruction Counter Register Number: 28, INSN CNT 31:0 Instruction Counter (INSN CNT) Default: 0x Global Address Register Number: PRIORITY 23 8 CHIP ID 7 0 NODE ID 31:24 Priority (PRIORITY) Default: 0x0 23:8 Chip ID (CHIP ID) Default: 0x1 ID 7:0 Node ID (NODE ID) Default: 0x0 ID 69

71 5 CPU Control Register CPU Information Register Number: Year Month 15 8 Version 7 0 Revision 31:24 Year Default: NaN :16 Month Default: :8 Version Default: NaN 7:0 Revision Default: NaN 70

72 71 6 FPU : 0 30 Reserved NA Reserved 31 Status RW FPU

73 6 FPU Status Register Number: Reserved C Reserved CAUSE EN FLAG RM 23 Condition (C) Default: 0x Exception Cause (CAUSE) Default: 0x Exception Enable (EN) Default: 0x Exception Flags (FLAG) Default: 0x Round Mode (RM) Default: 0x0 2 b00 Round to Nearest 2 b01 Round to Zero 2 b10 Round Ceiling 2 b11 Round Floor 6.2 Status V Z O U I 4 Invalid Operation (V) Default: 0x0 3 Divide By 0 (Z) Default: 0x Overflow (O) Default: 0x0 1 Underflow (U) Default: 0x0 72

74 Inexact (I) Default: 0x0 73

75

76 75 7 Memory Management Unit 7.1 MMU IO Companion Chip 16 TLB TLB Entry High Register Number: TH ID 31-0 Thread ID (TH ID) Default: 0x0 ID ID Entry Middle ID

77 7 Memory Management Unit Entry Middle Register Number: Reserved VPN PSIZE PROT G UC V 28-9 Virtual Page Number (VPN) Default: 0x Page Size (PSIZE) Default: 0x0 3 b000 4KB BYTE ADDRESS[31:12] 3 b001 64KB BYTE ADDRESS[31:16] 3 b010 1MB BYTE ADDRESS[31:20] 3 b011 16MB BYTE ADDRESS[31:24] 3 b MB BYTE ADDRESS[31:27] 3 b MB BYTE ADDRESS[31:28] 3 b MB BYTE ADDRESS[31:29] 3 b111 1GB BYTE ADDRESS[31:30] 5-3 Protection Mode (PROT) Default: 0x0 3 b111 All Read Only 3 b110 All Read Write 3 b101 User Read Write 3 b100 User Read Only 3 b011 Supervisor Read Write 3 b010 Supervisor Read Only 3 b001 Kernel Read Write 3 b000 Kernel Read Only 2 Global Bit (G) Default: 0x0 ID 1 Uncache (UC) Default: 0x0 0 Valid Bit (V) Default: 0x0 TLB 76

78 7.2. MMU Entry Low Register Number: Reserved 19 0 PPN 19-0 Physical Page Number (PPN) Default: 0x0 TLB Entry Global Register Number: PRIORITY 23 8 CHIP ID 7 0 NODE ID Priority (PRIORITY) Default: 0x Chip ID (CHIP ID) Default: 0x0 ID ID ID 7-0 Node ID (NODE ID) Default: 0x0 ID ID 7.2 MMU MMU mfimm I-MMU mtimm I-MMU mfdmm D-MMU mtdmm D-MMU

79 7 Memory Management Unit : Enable 00 R/W TLB Entry High 01 R/W High Entry Middle 02 R/W Middle Entry Low 03 R/W Low Index 04 R/W Lock 05 R/W Exception Code 06 R/W Exception Address 07 R/W Entry Global 08 R/W Global Reserved 9 15 NA Reserved Read Index 16 R/W Write Index 17 R/W Write Random 18 R/W TLB Probe 19 R/W TLB Reserved NA Reserved Enable Register Number: Reserved 0 E 31 Enable (E) Default: 0x0 1 MMU Entry High Register Number: TH ID 31-0 Thread ID (TH ID) Default: 0x0 ID 78

80 7.3. Entry Middle Register Number: Reserved VPN PSIZE PROT G UC V 28-9 Virtual Page Number (VPN) Default: 0x0 8-6 Page Size (PSIZE) Default: 0x0 5-3 Protection Mode (PROT) Default: 0x0 2 Global Bit (G) Default: 0x0 1 Uncache (UC) Default: 0x0 0 Valid Bit (V) Default: 0x0 Entry Low Register Number: Reserved 19 0 PPN 19-0 Physical Page Number (PPN) Default: 0x0 Index Register Number: Reserved P INDEX 31 Probe Hit (P) Default: 0x0 TLB Index (Index) Default: 0x0 TLB TLB TLB TLB 79

81 7 Memory Management Unit Lock Register Number: Reserved 3 0 LOCK 3-0 Lock Index (LOCK) Default: 0x0 TLB Exception Code Register Number: Reserved EXP CODE 3-0 Exception Code (EXP CODE) Default: 0x0 TLB TLB CPU TLB Exception Address Register Number: EXP ADDR 31-0 Exception Address (EXP ADDR) Default: 0x0 TLB Entry Global Register Number: PRIORITY 23 8 CHIP ID 7 0 NODE ID Priority (PRIORITY) Default: 0x Chip ID (CHIP ID) Default: 0x0 ID 7-0 Node ID (NODE ID) Default: 0x0 ID 80

82 7.3. Read Index Register Number: READ INDEX 31-0 Read Index (READ INDEX) Default: 0x0 TLB Index TLB TLB Entry (High, Middle, Low) Write Index Register Number: WRITE INDEX 31-0 Write Index (WRITE INDEX) Default: 0x0 TLB Index TLB Entry (High, Middle, Low) Write Random Register Number: WRITE RANDOM 31-0 Write Random (WRITE RANDOM) Default: 0x0 TLB TLB ( 0) ( TLB ) TLB Entry (High, Middle, Low) 81

83 7 Memory Management Unit TLB Probe Register Number: TLB PROB 31-0 TLB Probe (TLB Probe) Default: 0x0 TLB ( ) TLB Entry (High, Middle) ( ID VPN) 82

84 83 8 Bus : 32bit 16ch 32ch

85 8 Bus 8.2: CH 00 CPU 0 CH 01 CPU 0 CH 02 DMA Controller 0 CH 03 DMA Controller 1 CH 04 Reserved CH 05 Reserved CH 06 External Bus 0 CH 07 Reserved CH 08 Reserved CH 09 Reserved CH 10 PCI Controller CH 11 Reserved CH 12 Reserved CH 13 Reserved CH 14 Reserved CH 15 On-Chip Emulator

86 : CH 00 0x x1FFF FFFF Extenal Bus CH 01 - Reserved CH 02 - Reserved CH 03 - Reserved CH 04 0x x27FF FFFF CH 05 0x x2FFF FFFF CH 06 0x x37FF FFFF Legacy IO CH 07 0x x3FFF FFFF Control IO CH 08 0x x47FF FFFF SRAM CH 09 0x x4FFF FFFF DMA Controller CH 10 0x x57FF FFFF PCI Controller CH 11 - Reserved CH 12 - Reserved CH 13 - Reserved CH 14 - Reserved CH 15 0x x7FFF FFFF On-Chip Emulator CH 16 0x xA7FF FFFF Responsive Link CH 17 - Reserved CH 18 - Reserved CH 19 - Reserved CH 20 - Reserved CH 21 - Reserved CH 22 - Reserved CH 23 - Reserved CH 24 - Reserved CH 25 - Reserved CH 26 - Reserved CH 27 - Reserved CH 28 - Reserved CH 29 0xE xEFFF FFFF Link SDRAM DQS Delay CH 30 0xF xF7FF FFFF External Bus Controller CH 31 0xF xFFFF FFFF Internal Bus Controller 85

87 8 Bus 8.4: Legacy IO CH x x30FF FFFF UART CH x x31FF FFFF GPIO CH x x32FF FFFF SPI CH x x33FF FFFF I2C CH x x34FF FFFF Reserved CH x x35FF FFFF Reserved CH x x36FF FFFF Reserved CH x x37FF FFFF Reserved 8.5: Control IO CH x x38FF FFFF PWM Generator CH x x39FF FFFF PWM Input CH x3A x3AFF FFFF Pulse Counter CH x3B x3BFF FFFF Real-Time Clock CH x3C x3CFF FFFF Reserved CH x3D x3DFF FFFF Reserved CH x3E x3EFF FFFF Reserved CH x3F x3FFF FFFF Reserved xf : 0x0000 Status RW 0x0004 Arbitration Policy RW 0x0008 Watch Dog Timer Enable RW 0x000C Watch Dog Timer Expire Value RW 0x0010 Last Access Address RW 0x0014 Error Address RW 0x4000 0x7FFC Bus Master Priority RW 0x8000 0xBFFC Bus Slave Address Map RW 86

88 Status offset: 0x Reserved 1 0 WD DEC 1 Watch Dog Timer Expired (WD) Default: 0x0 0 Decode Error (DEC) Default: 0x0 Arbitration Policy offset: 0x Reserved 0 P 0 Arbitration Policy (P) Default: 0x0 0 1 Watch Dog Timer Enable offset: 0x Reserved 0 WDE 0 Watch Dog Timer Enable (WDE) Default: 0x0 Watch Dog Timer Expire Value offset: 0x000C 31 0 WD EXPR VAL 31:0 Watch Dog Timer Expire Value Default: 0x0 (WD EXPR VAL) 87

89 8 Bus Last Access Address offset: 0x LA ADDR 31:0 Last Access Address (LA ADDRESS) Default: 0x0 Error Address offset: 0x ERROR ADDR 31:0 Error Address (ERROR ADDRESS) Default: 0x0 Bus Master Arbitration Priorityoffset: 0x4000 0x7FFC 31 8 Reserved 7 0 PRIORITY 7:0 Arbitration Priority (PRIORITY) Default: 0x0 Bus Slave Address Map offset: 0x8000 0xBFFC 31 0 ADDR MAP 7:0 Address Map (ADDR MAP) Default: 0x0 88

90 89 9 External Bus : 32bit 4ch External Channel External Channel xf : 0x0 Status RW 0x4 Auto Ready Time RW 0x8 External Channel RW

91 9 External Bus Status offset: 0x Reserved BR TGL ARE SYN CNCT END SIZE 8 Burst (BR) Default: 0x1 0 7 Chip Select Toggle (TGL) Default: 0x Auto Ready Enable (ARE) Default: 0x1 0 5 Sync (SYN) Default: 0x :3 Connect (CNCT) Default: 0x0 32bit data[31:0] 16bit 8bit 2 b00 data[31:16] data[31:24] 2 b01 data[31:16] data[23:16] 2 b10 data[15:0] data[15:8] 2 b11 data[15:0] data[7:0] 2 Endian (END) Default: 0x :0 Size (SIZE) Default: 0x0 2 b00 32bit 2 b01 16bit 2 b10 8bit 90

92 9.2. Auto Ready Time offset: 0x AR TIME 31:0 Auto Ready Time (AR TIME) Default: 0x20 External Channel offset: 0x Reserved 1 0 EXT CH 1:0 External Channel (EXT CH) Default: 0x0 91

93

94 93 10 Timer 10.1 CPU CH 0: 0x CH 1: 0x CH 2: 0x CH 3: 0x : Control 0x0 R/W Interrupt 0x4 R/W Expiration 0x8 R/W Counter 0xC R/W

95 10 Timer Control : Access : Read / Write Offset: 0x Reserved 1 P 0 S 1 Periodic (P) Default: 0x0 bit 0 bit 1 0 Start (S) Default: 0x0 bit 1 Interrupt : Access : Read / Write Offset: 0x Reserved 0 I 2 Interrupt (I) Default: 0x0 bit 1 Expiration : Access : Read / Write Offset: 0x EXPR 31:0 Expiration (EXPR) Default: 0x0 Counter : 94

96 10.2. Access : Read / Write Offset: 0xC 31 0 COUNTER 8 Counter (COUNTER) Default: 0x0 95

97

98 97 11 Clock Generator x Clock Divider 0x00 Clock Gating 0x04 # 1 # 11.1 PWM OUT 0 0x x x04 = 0x x2 Reset # 11.2 PWM OUT 3 0x x x90 = 0x (Active-Low) : #

99 11 Clock Generator 11.1: 0 CPU 1 Bus 2 SRAM Main 0x000 3 Link Bus 4 DMAC 0 5 DMAC 1 6 DMAC 2 7 DMAC 3 0 Timer Bus 1 Timer 0 Timer 0x100 2 Timer 1 3 Timer 2 4 Timer 3 0 UART Bus UART 0x200 1 UART 0 2 UART 1 GPIO 0x300 0 GPIO Bus 1 GPIO SPI 0x400 0 SPI Bus 1 SPI I2C 0x500 0 I2C Bus 1 I2C 0 PWM OUT Bus 1 PWM OUT 0 2 PWM OUT 1 PWM OUT 0x600 3 PWM OUT 2 4 PWM OUT 3 5 PWM OUT 4 6 PWM OUT 5 0 PWM IN Bus PWM IN 0x700 1 PWM IN 0 2 PWM IN 1 0 Pulse Counter Bus Pulse Counter 0x800 1 Pulse Counter 0 2 Pulse Counter 1 PCI 0x900 0 PCI Bus 1 PCI Link IO Clock 0xa00 0 Link IO Link COM Clock 0xb00 0 Link COM Link SDRAM 1X Link SDRAM 0xc00 0 Link SDRAM X1X 98

100 : Link SDRAM 2X Link SDRAM X2X 11.2: # 0 0x80 1 0x84 2 0x88 3 0x8c 4 0x90 5 0x94 6 0x98 7 0x9c Clock Divider Access : Read / Write Offset: 0x Reserved 16 T 15 0 Divider Ratio 16 Through Mode (T) Default: 0x0 1 PLL 1/1 15:0 Divider Ratio Default: 0x0 n PLL 2 (n + 1) Clock Gating Access : Read / Write Offset: 0x G31G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 n Gating #n (Gn) Default: 0x0 n 1 #n n 11.1 # 99

101 11 Clock Generator Reset Access : Read / Write Offset: 0x80-0x9c Reserved R A Auto Reset Timer 17 Reset (R ) Default: 0x Auto Reset (A ) Default: 0x :0 Auto Reset Timer Default: 0x0 100

102 Universal Asynchronous Receiver/Transmitter : Channel0:0x Channel1:0x offset x0000 RB 0x0000 THR 0x0000 DL1 0x0004 IER 0x0004 DL2 0x0008 IIR 0x0008 FCR 0x000c LCR 0x00010 MCR 0x0014 LSR 0x0018 MSR Receiver Buffer (RB) / Transmitter Holding Register (THR) : 0x bit FIFO FIFO Interrupt Enable Register (IER) : 0x0004

103 12 Universal Asynchronous Receiver/Transmitter bit 24 Received Data availble interrupt. 0 - Disabled. 1 - Enabled. 25 Transmitter Holding Register empty interrupt. 0 - Disabled. 1 - Enabled. 26 Receiver Line Status Interrupt. 0 - Disabled. 1 - Enabled. 27 Modem Status Interrupt. 0 - Disabled. 1 - Enabled Reserved. Should be logic Interrupt Identification Register (IIR) : 0x

104 12.1. bit 24 When this is 0, an interrupt is pending. When this is 1, no interrupt is pending The following table displays the list of possible interrupts along with the bits they enable, priority, and their source and reset control. Prio- Interrupt Interrupt Source Interrupt Reset rity Type Control 011 1th Receiver Parity, Overrun or Reading the Line Line Framing errors or Status Register Status Break Interrupt 010 2nd Receiver FIFO trigger level FIFO drops below Data reached trigger level available 110 2nd Timeout There s at least 1 Reading from the Indication character in the FIFO FIFO (Receiver but no character has Buffer Register) been input to the FIFO or read from it for the last 4 char times rd Transmitter Transmitter Holding Writing to the Holding Register Empty Transmitter Holding Register Register or reading empty the IIR 000 4th Modem CTS, DSR, RI or Reading the Modem Status DCD Status Register Reserved. Should be logic Reserved. Should be logic 1 for compatibility reason FIFO Control Register (FCR) : 0x

105 12 Universal Asynchronous Receiver/Transmitter bit 24 Ignored(Used to enable FIFOs in NS16550D). Since this UART only supports FIFO mode, this bit is ignored. 25 Writing a 1 to bit 1 clears the Receiver FIFO and resets its logic. But it doesn t clear the shift register, i.e. receiving of the current character continues. 26 Writing a 1 to bit 2 clears the Transmitter FIFO and resets its logic. The shift register is not clreared, i.e. transmitting of the current character continues Ignored Define the Receiver FIFO Interrupt trigger level bytes 01-4 bytes 10-8 bytes bytes Line Control Register (LCR) : 0x000c

106 12.1. bit Select number of bits in each character bits 01-6 bits 10-7 bits 11-8 bits 26 Specify the number of generated stop bits. 0-1 stop bit stop bits when 5-bit character length selected and 2 bits otherwise. Note that the receiver always checks the first stop bit only. 27 Parity Enable. 0 - No parity 1 - Parity bit is generated on each outgoing character and is checked on each incoming one. 28 Even Parity select. 0 - Odd number of 1 is transmitted and checked in each word (data and parity combined). In other words, if the data has an even number of 1 in it, then the parity bit is Even number of 1 is transmitted in each word. 29 Stick Parity bit. 0 - Stick Parity disabled. 1 - If bits 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as Break Control bit. 1 - The srial out is forced into logic 0 (break state). 0 - Break is disabled. 31 Divisor Latch Access bit. 1 - The divisor latches can be accessed. 0 - The normal registers are accessed Modem Control Register (MCR) : 0x

107 12 Universal Asynchronous Receiver/Transmitter bit 24 Data Terminal Ready (DTR) signal control. 0 - DTR is DTR is 0 25 Request To Send (RTS) signal control 0 - RTS is RTS is 0 26 Out1. In loopback mode, connected Ring Indicator (RI) signal input. 27 Out2. In loopback mode, connected to Data Carrier Detect (DCD) input. 28 Loopback mode. 0 - normal operation. 1 - loopback mode. When in loopback mode, the Serial Output Signal (STX PAD O) is set to logic 1. The signal of the transmitter shift register is internally connected to the input of the receiver shift register. The following connections are made: DTR DSR RTS CTS Out1 RI Out2 DCD Ignored Line Status Register (LSR) : 0x

108 12.1. bit 24 Data Ready (DR) indicator. 0 - No characters in the FIFO. 1 - At least one character has been received and is in the FIFO. 25 Overrun Error (OE) INDICATOR. 1 - If the FIFO is full and another character has been received in the receiver shift register. If another character is starting to arrive, it will overwrite the data in the shift register but the FIFO will remain intact. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt. 0 - No overrun state. 26 Parity Error (PE) indicator. 1 - The character that is currently at the top of the FIFO has been received with parity error. The bit is cleared upon reading from the register. Generate Receiver Line Status interrupt. 0 - No parity error in the current character. 27 Framing Error (FE) indicator. 1 - The received character at the top of the FIFO did not have a valid stop bit. The UART core tries re-synchronizing by assuming that the bit received was a start bit. Of course, generally, it might be that all the following data is corrupt. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt. 0 - No framing error in the current character. 28 Break Interrupt (BI) indicator. 1 - A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive next character. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt. 0 - No break condition in the current character. 29 Transmit FIFO is empty. 1 - The transmitter FIFO is empty. Generates Transmitter Holding Register Empty interrupt. The bit is cleared in the following cases: The LSR has been read, the IIR has been read or data has been written to the transmitter FIFO. 0 - Otherwise. 30 Transmitter Empty indicator. 1 - Both the transmitter FIFO and transmitter shift register are empty. The bit is cleared upon reading from the register or upon writing data to the transmit FIFO. 0 - Otherwise At least one parity error, framing error or break indications have been received and are inside the FIFO. The bit is cleared upon reading from the register. 0 - Otherwise. 107

109 12 Universal Asynchronous Receiver/Transmitter Modem Status Register (MSR) : 0x bit 24 Delta Clear To Send (DCTS) indicator. 1 - The CTS line has changed its state. 25 Delta Data Set Ready (DDSR) indicator. 1 - The DSR line has changed its state. 26 Trailing Edge of Ring Indicator (TERI) detector. The RI line has changed its state from low to high state. 27 Delta Data Carrier Detect (DDCD) indicator. 1 - The DCD line has changed its state. 28 Complement of the CTS input or equals to RTS in loopback mode. 29 Complement of the DSR input or equals to DTR in loopback mode. 30 Complement of the RI input or equals to Out1 in loopback mode. 31 Complement of the DCD input or equals to Out2 in loopback mode Divisor Latches (DL) : 0x0000(DL1), 0x0004(DL2) The divisor latches can be accessed by setting the 7th bit of LCR to 1. You should restore this bit to 0 after setting the divisor latches in order to restore access to the other registers that occupy the same addresses DL DL2 bit DL1, DL2 The 2 bytes form one 16-bit register, which is internally accessed as a single number. You should therefore set all 2 bytes of the register to ensure normal operation. The register is set to the default value of 0 on reset, which disables all serial I/O operations in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed) / (16 times desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last / This UART core is very similar in operation to the standard UART chip with the main exception being that only the FIFO mode is supported. The scratch register is removed, as it serves no purpose. 108

110 12.2. / Initialization Upon reset the core performs the following tasks: The receiver and transmitter FIFOs are cleared. The receiver and transmitter shift registers are cleared. The Divisor Latch register is set to 0. The Line Control Register is set to communication of 8 bits of data, no parity, 1 stop bit. All interrupts are disabled in the Interrupt Enable Register. For proper operation, perform the following: Set the Line Control Register to the desired line control parameters. Set bit 7 to 1 to allow access to the Divisor Latches. Set the Divisor Latches, MSB first, LSB next. Set bit 7 of LCR to 0 to disable access to Divisor Latches. At this time the transmission engine starts working and data can be sent and received. Set the FIFO trigger level. Generally, higher trigger level values produce less interrupt to the system, so setting it to 14 bytes is recommended if the system responds fast enough. Enable desired interrupts by setting appropriate bits in the Interrupt Enable register. Remember that (Input Clock Speed)/(Divisor Latch value) = 16 the communication baud rate. Since the protocol is asynchronous and the sampling of the bits is performed in the perceived middle of the bit time, it is highly immune to small differences in the clocks of the sending and receiving sides, yet no such assumption should be made calculating the Divisor Latch values. 109

111

112 General Purpose I/O Unit 13.1 Outline General Purpose I/O Unit 8 bit 13.2 Interface Address Format General Purpose I/O Unit 0x General Purpose I/O Unit 4 0 Offset Field Name Range Description Offset 4: Control Register General Purpose I/O Unit Offset Offset

113 13 General Purpose I/O Unit Data offset: 0x Reserved 7 0 Data Field Name Range Description Data 7:0 bit bit Direction offset: 0x Reserved 7 0 Direction Field Name Range Description Direction 7:0 0 1 Interrupt Enable offset: 0x Reserved 7 0 Interrupt Enable Field Name Range Description Interrupt Enable 7:0 1 Data Interrupt Upedge Interrupt Downedge Interrupt Sense offset: 0x0c 31 8 Reserved 7 0 Interrupt Sense Field Name Range Description Interrupt Sense 7:0 bit 1 0 bit 112

114 13.3. Operation Interrupt Upedge offset: 0x Reserved 7 0 Interrupt Upedge Field Name Range Description Interrupt Upedge 7: Interrupt Downedge offset: 0x Reserved 7 0 Interrupt Downedge Field Name Range Description Interrupt Downedge 7: Configuration offset: 0x18 (Read Only) 31 2 Reserved 1 0 BW Field Name Range Description Bit Width (BW) 1:0 General Purpose I/O Bit Width 0x1 : 8 Bit 0x2 : 16 Bit 0x3 : 32 Bit 13.3 Operation General Purpose I/O 8 bit bit Direction General Purpose I/O I/O Data Data I/O bit Interrupt Enable bit 1 Interrupt Upedge Interrupt Downedge bit

115

116 Serial Peripheral Interface Unit 14.1 Outline Serial Peripheral Interface Unit SPI 14.2 Interface Address Format Serial Peripheral Interface Unit 0x SPI Unit 5 0 Offset Field Name Range Description Offset 5: Control Register Serial Peripheral Interface Unit Offset Offset

117 14 Serial Peripheral Interface Unit Slave Control offset: 0x00 Slave 31 5 Reserved 4 1 SS 0 A Field Name Range Description Auto (A) SPI Slave Select (SS ) 4:1 MSB slave0 LSB slave3 Auto bit 1 Slave bit 0 bit Auto bit 0 Slave bit 0 bit FIFO Control offset: 0x04 FIFO Reserved CLR DREQ INTR Field Name Range Description Interrupt (INTR) 3:0 1 0: FIFO DMA (DREQ) Request 1: FIFO 2: FIFO 3: FIFO 7:4 1 DMA Request 4: FIFO DMA Request 5: FIFO DMA Request 6: FIFO DMA Request 7: FIFO DMA Request Clear (CLR) 9:8 1 FIFO bit 0 8: FIFO 9: FIFO 116

118 14.2. Interface FIFO Status offset: 0x08 (Read Only) 31 6 Reserved TF TH TE RF RHRE Field Name Range Description Rx Empty (RE) 0 FIFO 1 Rx Half (RH) 1 FIFO 1 Rx Full (RF) 2 FIFO 1 Tx Empty (RE) 3 FIFO 1 Tx Half (RH) 4 FIFO 1 Tx Full (RF) 5 FIFO 1 FIFO offset: 0x0c 31 0 FIFO Field Name Range Description FIFO 31:0 FIFO Slave Control Auto bit 0 FIFO Interrupt offset: 0x10 1 bit 31 4 Reserved TE TH RF RH Field Name Range Description Rx Half (RH) 0 FIFO Rx Full (RF) 1 FIFO Tx Half (RH) 2 FIFO Tx Empty (RE) 3 FIFO 117

119 14 Serial Peripheral Interface Unit Interval offset: 0x Interval Field Name Range Description Interval 31:0 Slave Control Auto bit 0 Slave Mode3 offset: 0x20 Slave Select W R L Size OLHA Clock Ratio Field Name Range Description Clock Ratio 21:0 2 SPI HA, OL 23:22 SPI 0x0 0x1 0x2 0x3 Size 28: bit LSB (L) 29 1 LSB 0 MSB Read Enable (R ) 30 0 FIFO 1 Write Enable (W ) 31 0 FIFO 1 118

120 14.2. Interface Mode2 offset: 0x24 Slave Select W R L Size OLHA Clock Ratio Field Name Range Description Clock Ratio 21:0 2 SPI HA, OL 23:22 SPI 0x0 0x1 0x2 0x3 Size 28: bit LSB (L) 29 1 LSB 0 MSB Read Enable (R ) 30 0 FIFO 1 Write Enable (W ) 31 0 FIFO 1 119

121 14 Serial Peripheral Interface Unit Mode1 offset: 0x28 Slave Select W R L Size OLHA Clock Ratio Field Name Range Description Clock Ratio 21:0 2 SPI HA, OL 23:22 SPI 0x0 0x1 0x2 0x3 Size 28: bit LSB (L) 29 1 LSB 0 MSB Read Enable (R ) 30 0 FIFO 1 Write Enable (W ) 31 0 FIFO 1 120

122 14.3. Operation Mode0 offset: 0x2c Slave Select W R L Size OLHA Clock Ratio Field Name Range Description Clock Ratio 21:0 2 SPI HA, OL 23:22 SPI 0x0 0x1 0x2 0x3 Size 28: bit LSB (L) 29 1 LSB 0 MSB Read Enable (R ) 30 0 FIFO 1 Write Enable (W ) 31 0 FIFO 1 Configuration offset: 0x30 (Read Only) 31 2 Reserved 1 0 FS Field Name Range Description FIFO Size (FS) 1:0 FIFO 0x1 : 8 Entry 0x2 : 16 Entry 0x3 : 32 Entry 14.3 Operation SPI Unit 4 Slave Select Slave Slave Mode SPI Unit Slave Slave

123 14 Serial Peripheral Interface Unit Manual Mode 1 1 Slave Control Auto bit 1 Slave Slave Control Slave Select bit Slave Mode W bit 0 FIFO Slave Mode R bit 0 FIFO Slave FIFO SPI Slave Mode W bit R bit Auto Mode Auto Mode Slave Slave Control Auto bit 0 Auto Mode Slave Slave Control Slave Select bit Slave Slave Mode Mode R bit W bit 0 Auto Mode SPI Unit Slave Control Slave Select bit 0 Slave (3 ) Slave Interval Slave 122

124 I2C Master Controller 15.1 Outline I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously Interface Address Format I2C Master Controller 0x I2C Master Controller 4 0 Offset Field Name Range Description Offset 4: Control Register I2C Master Controller Offset Offset

125 15 I2C Master Controller Clock Prescale (lo-byte) offset: 0x Reserved 7 0 scale Clock Prescale (hi-byte) offset: 0x Reserved 7 0 scale Field Name Range Description scale 7:0 This register is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when the EN bit is cleared. Example: wb clk i = 32MHz, desired SCL = 100KHz prescale = 32MHz 1 = 63(dec) = 3F (hex) 5 100KHz Control offset: 0x Reserved 7 6 ENIEN 5 0 Reserved Field Name Range Description I2C core enable bit (EN) I2C core interrput enable bit (IEN) 7 When set to 1, the core is enabled. When set to 0, the core is disable. 6 When set to 1, interrupt is enabled. When set to 0, interrupt is disable. 124

126 15.2. Interface Transmit offset: 0x0c (Write Only) 31 8 Reserved 7 1 NB 0 X Field Name Range Description Next byte (NB) 7:0 Next byte to transmit via I2C. X 0 In case of a data tranfer this bit represents the data s LSB. In case of a slave address transfer this bit represents the RW bit. 1 = reading from slave. 0 = writing to slave. Receive offset: 0x0c (Read Only) 31 8 Reserved 7 0 LB Field Name Range Description Last byte (LB) 7:0 Last byte received via I2C. Command offset: 0x10 (Write Only) Reserved STASTO R 4 W AReserved I Field Name Range Description Start (STA) 7 Generate (repeated) start condition. Stop (STO) 6 Generate stop condition. Read (R) 5 Read from slave. Write (W) 4 Write to slave. ACK (A) 3 When a receiver, sent ACK (ACK = 0 ) or NACK (ACK = 1 ). Interrput ACK (I) 1 Interrupt acknowledge. When set, clears a pending interrupt. The STA, STO, R, W, and I bits are cleared automatically. These bits are always read as zeros. 125

127 15 I2C Master Controller Status offset: 0x10 (Read Only) Reserved R B A Reserved T I Field Name Range Description Received acknowledge 7 This flag represents acknowledge from the addressed slave. from slave (R) 1 = No acknowledge received. 0 = Acknowledge received. I2C bus busy (B) 6 1 after START signal detect. 0 after STOP signal detect. Arbitration lost (A) 5 This bit is set when the core lost arbitration. Arbitration is lost when: a STOP signal is detected, but non requested. The master drives SDA high, but SDA is low. See bus-arbitration section for more information. Transfer in progress 1 1 when transferring data. (T) 0 when transfer complete. Interrupt Flag (I) 0 This bit is set when an interrupt is pending, which will cause a processor interrupt request if the IEN bit is set. The Interrupt Flag is set when: one byte transfer has been completed. arbitration is lost Operation System Configuration I2C system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to these two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with external pull-up resistors. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (see START and STOP signals). 126

128 15.3. Operation I2C Protocol Normally, a standard communication consists of four parts: 1. START signal generation 2. Slave address transfer 3. Data transfer 4. STOP signal generation START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a high-to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new data transfer. A Repeated START is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are set. Depending on the current status of the SCL line, a START or Repeated START is generated. Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a seven-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle. Note: The core supports 10bit slave addresses by generating two address transfers. See the Philips I2C specifications for more details. The core treats a Slave Address Transfer as any other write action. Store the slave device s address in the Transmit Register and set the WR bit. The core will then transfer the slave address on the bus. Data Transfer Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a No Acknowledge, the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle. 127

129 15 I2C Master Controller If the master, as the receiving device, does not acknowledge the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. To write data to a slave, store the data to be transmitted in the Transmit Register and set the WR bit. To read data from a slave, set the RD bit. During a transfer the core set the TIP flag, indicating that a Transfer is In Progress. When the transfer is done the TIP flag is reset, the IF flag set and, when enabled, an interrupt generated. The Receive Register contains valid data after the IF flag has been set. The user may issue a new write or read command when the TIP flag is reset. STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a low-to-high transition of SDA while SCL is at logical Arbitration Procudure The I2C bus is a true multimaster bus that allows more than one master to be connected on it. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-and connection of the I2C signals a high to low transition affects all devices connected to the bus. Therefore a high to low transition on the SCL line causes all concerned devices to count off their low period. Once a device clock has gone low it will hold the SCL line in that state until the clock high state is reached. Due to the wired-and connection the SCL line will therefore be held low by the device with the longest low period, and held high by the device with the shortest high period Clock Stretching Slave devices can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave s SCL low period is greater than the master s SCL low period, the resulting SCL bus signal low period is stretched, thus inserting wait-states. 128

130 PWM Generator 16.1 PWM PWM Bit 32bit PWM PWM PWM 6 PWM 0x PWM PWM PWM N REV bit PWM N+1 PWM

131 16 PWM Generator 16.2 PWM 0x00 0x20 0x40 0x60 0x80 0xA0 CTRL PWMCTRL[0] PWMCTRL[1] PWMCTRL[2] PWMCTRL[3] PWMCTRL[4] PWMCTRL[5] INT SYN INV M REVDEN 3 D 2 P 1 0 CLRCEN 130

132 16.2. PWM bit INT Invert: Default 0 0: 1: SYN Invert: Default 0 0: CEN 1: PWM PWM PWM CEN 1 SYN 1 PWM PWM CEN PWM PWM INV Invert: Default 0 0: PWM 1: PWM PWM M Mode: Default 0 0: PWM 1: PWM REV Reverse mode enable: Default 0 0: PWM PWM 1: PWM PWM PWM PWM DEN DEN Data Enable: Default 0 0: PWM 1: D bit REV D Data: Default 0 DEN 1 D bit P Positive: Default 0 PWM 16.1, : 1: CLR Counter clear: Default 0 0: 1: CEN Count Enable: Default 0 0: 1: 131

133 16 PWM Generator 16.3 PWM 0x04 0x24 0x44 0x64 0x84 0xA4 PWM FWCNT[0] FWCNT[1] FWCNT[2] FWCNT[3] FWCNT[4] FWCNT[5] 31 0 FWCNT<31:0> bit FWCNT Forward Counter: Default 0 PWM Mode 0( ) PWM PWM 0 FWCNT Mode 1( ) PWM PWM 0 FWCNT

134 16.4. PWM 16.4 PWM 0x08 0x28 0x48 0x68 0x88 0xA8 PWM REVCNT[0] REVCNT[1] REVCNT[2] REVCNT[3] REVCNT[4] REVCNT[5] 31 0 REVCNT<31:0> bit REVCNT Reverse Counter: Default 0 PWM PWM 16.1, x0C 0x2C 0x4C 0x6C 0x8C 0xAC DT[0] DT[1] DT[2] DT[3] DT[4] DT[5] DT<15:0> bit DT<15:0> Reverse Counter :Default 0 PWM 16.1,

135 16 PWM Generator 16.1: 134

136 : 135

137

138 PWM Input 17.1 PWM PWM High Low Bit 32bit 2 11 PWM 0x PWMIN 0xFFFF7400 0xFFFF7420 PWMIN PWMINCTRL[0] PWMINCTRL[1] LP 5 2 LPO 1 0 CLR IEN

139 17 PWM Input bit IEN CLR LPO LP Interrupt Enable :Default 0 r/w 0: 1: Interrupt Clear :Default 0 r/w 0: 1: 0 Loop Original :Default 1 r/w Loop :Default 1 ro 17.3 PWMIN HIGH 0x04 0x24 PWMIN HIGH HIGH[0] HIGH[1] 31 0 HIGH<31:0> bit HIGH<31:0> High :Default X PWM High PWMIN 17.4 PWMIN LOW 0x08 0x28 PWMIN LOW LOW[0] LOW[1] 31 0 LOW<31:0> bit LOW<31:0> Low :Default X PWM Low PWMIN 138

140 Pulse Counter Up-Down Counter Z bit 32bit 2 0x3A x00 0x20 PLSCTRL[0] PLSCTRL[1] INT - IPCEIZE ZF RFZ ST 6 TI 5 SEL 4 3 MD IE CLR CE

141 18 Pulse Counter bit INT IPCE IZE ZF RFZ ST TI SEL MD<4:3> IE CLR CE Interrupt :Default 0 ro 0: 1: Z Int Pulse Counter Enable :Default Int Z Enable :Default 0 0 Z 1 Z Z Flag :Default 0 0 Z 1 Z 1 0 Z (IZE) 0 Z Reset Flag by phaze Z :Default 0 0 Z 1 Z START :Default Timer Interrupt :Default Select :Default Mode :Default ,11 4 Interrupt Enable :Default 0 0: 1: counter CLear :Default 1 0: 1:don t care Count Enable :Default 0 0: 1: x04 0x24 CMP[0] CMP[1] 31 0 CMP<31:0> bit CMP<31:0> Compare Data :Default X SEL bit 0 140

142 x08 0x28 CNT[0] CNT[1] 31 0 CNT<31:0> bit CNT<31:0> Count Data :Default X x0C 0x2C TIMER[0] TIMER[1] 31 0 TIMER<31:0> bit TIMER<31:0> Timer Data :Default X SEL bit 1 141

143

144 Real Time Clock 19.1 Outline Real Time Clock Unit 1 ( 2 ) 1 rtc clk kHz 1 Clock Compare rtc hold Real Time Clock Unit Real Time Clock 0x3B Interface Address Map Second offset: 0x Reserved 7 U 6 0 Second Field Name Range Description Update (U) Second 6:0 BCD

145 19 Real Time Clock Minute offset: 0x Reserved 7 U 6 0 Minute Field Name Range Description Update (U) Minute 6:0 BCD Hour offset: 0x Reserved U 0 Hour Field Name Range Description Update (U) Hour 5:0 BCD Week offset: 0x0c 31 8 Reserved 7 U 6 0 Week Field Name Range Description Update (U) Week 6:

146 19.2. Interface Day offset: 0x Reserved U 0 Day Field Name Range Description Update (U) Day 5:0 BCD Month offset: 0x Reserved U 00 Month Field Name Range Description Update (U) Month 4:0 BCD Year offset: 0x Reserved 7 0 Year Field Name Range Description Year 7:0 2 BCD 145

147 19 Real Time Clock Second Alarm offset: 0x Reserved 7 D 6 0 Second Field Name Range Description Don t Care (D) Second Second 6:0 BCD Minute Alarm offset: 0x Reserved 7 D 6 0 Minute Field Name Range Description Don t Care (D) Minute Minute 6:0 BCD Hour Alarm offset: 0x Reserved D 0 Hour Field Name Range Description Don t Care (D) Hour Hour 5:0 BCD 146

148 19.2. Interface Week Alarm offset: 0x2c 31 8 Reserved 7 D 6 0 Week Field Name Range Description Don t Care (D) Week Week 6:0 1 Day Alarm offset: 0x Reserved D 0 Day Field Name Range Description Don t Care (D) Day Day 5:0 BCD Month Alarm offset: 0x Reserved D 00 Month Field Name Range Description Don t Care (D) Month Month 4:0 BCD 147

149 19 Real Time Clock Time offset: 0x38 (Read Only) Reserved Hour Minute Second Field Name Range Description Hour 23:16 Hour Minute 15:8 Minute Second 7:0 Second Date offset: 0x3c (Read Only) Week Year Month Day Field Name Range Description Week 31:24 Week Year 23:16 Year Month 15:8 Month Day 7:0 Day Mode offset: 0x Reserved TMPT TE AE EN Field Name Range Description Test Mode (TM) 4 0 Periodic Timer (PT) 3 1 Periodic Timer 0 One Shot Timer Timer Enable (TE) 2 1 Expire One Shot Timer 0 Alarm Enable (AE) 1 1 Enable (EN) 0 1 Real Time Clock 148

150 19.2. Interface Sense offset: 0x Reserved 1 TI 0 AI Field Name Range Description Timer Interrupt (TI) Alarm Interrupt (AI) Timer Compare offset: 0x Timer Compare Field Name Range Description Timer Compare 31:0 Timer Count offset: 0x4c (Read Only) 31 0 Timer Count Field Name Range Description Timer Count 31:0 Timer Setup Clock Compare offset: 0x Clock Compare Field Name Range Description Clock Compare 31:0 Clock Count 1 149

151 19 Real Time Clock Clock Count offset: 0x54 (Read Only) 31 0 Clock Count Field Name Range Description Clock Count 31:0 1 Clock Compare 1 150

152 DMA Controller 32/16/8 bit I/F 4 Memory to memory Bus sizing (8, 16bit I/O ) Bus swapping (8, 16bit I/O ) 20.1 DMAC DMAC0 0x DMAC1 0x offset x800 - PRI 0x804 - IC 0x40*(x)+0x04 PSA< 31 : 0 > 0x40*(x)+0x08 MDA< 31 : 0 > 0x40*(x)+0x18 LN< 31 : 0 > 0x40*(x)+0x0c ID< 31 : 0 > 0x40*(x)+0x10 - DASSAUBM RL PCIMTMMR 32P16P 8P S16 S8 IERIED ST 0x40*(x)+0x14 L0 L1 L2 L3 - ER ED DMA

153 20 DMA Controller : 0x PRI bit PRI PRIority :Default 0 DMA 0: 1: ch0 > ch1 > ch2 > ch DMA : 0x IC bit IC Interrupt Clear DMA 0: : 0x40*(x) +0x PSA< 31 : 0 > bit PSA< 31 : 0 > Port/Source Address :Default X x DMA I/O MODE MTM MODE MTM : 0x40*(x) +0x MDA< 31 : 0 > bit MDA< 31 : 0 > Memory/Destination Address :Default X x DMA I/O MODE MTM MODE MTM 152

154 : 0x40*(x) +0x LN< 31 : 0 > bit LN< 31 : 0 > transfer LeNgth :Default X x DMA : 0x40*(x) +0x0c 31 0 ID< 31 : 0 > bit ID< 31 : 0 > Internal Data :Default X x DMA DMA : 0x40*(x) +0x DASSAU BM RL PCI MTMMR 32P 16P 5 8P 4 S16 3 S IER IED ST 153

155 20 DMA Controller bit DAS Destination Address Update :Default X 0: 1: SAU Source Address Update :Default X 0: 1: BM Burst Mode :Default X 0: 1: RL Responsive Link :Default X 1: DPM DMA PCI PCI :Default X 1:PCI DMA MTM Memory To Memory transfer :Default X 0: I/O DMA MR 1: DMA UP 4 DMA Memory To Memory MR MR Memory Read :Default X 0:I/O 1: I/O 32P 32bit I/O Port :Default X 0:don t care 1:MTM 0 32bit I/O P 16P 16bit I/O Port :Default X 0:don t care 1:MTM 0 16bit I/O 0 D31-16 or D15-0 8P 8P 8bit I/O Port :Default X 0:don t care 1:MTM 0 8bit I/O 1 0 D31-24 or D23-16 or D15-8 or D7-0 S16 Swap at 16bit :Default X 0:don t care 1: 16bit 31 A B C D 0 31 C D A B 0 S8 Swap at 8bit :Default X 0:don t care 1: 8bit 31 A B C D 0 31 B A D C 0 S16=1,S8=1 31 A B C D 0 31 D C B A 0 IER Interrupt enable of ER-bit :Default 0 0: 1: IED Interrupt enable of ED-bit :Default 0 0: 1: ST Start :Default 0 0:DMA 0 DMAC 1:DMA 154

156 20.1. (S16=0,S8=0) (S16=0,S8=1) (S16=1,S8=0) (S16=1,S8=1) (32bit) (32bit) (32bit) I/O 32bit(D31-0) I/O 16bit(D31-16) I/O 16bit(D15-0) I/O 8bit(D31-24) I/O 8bit(D23-16) I/O 8bit(D15-8) I/O 8bit(D7-0) (D31-16) I/O8bit(D31-24) : 0x40*(x)+0x L0 L1 L2 L3-1 ER 0 ED bit L0 L1 L2 L3 ER ED Location 0 :Default 0 0: D : D31-24 Location 1 :Default 0 0: D : D23-16 Location 2 :Default 0 0: D15-8 1: D15-8 Location 3 :Default 0 0: D7-0 1: D7-0 Error :Default 0 0:don t care 1:DMA DMA 0 END :Default 0 0:don t care 1:DMA

157

158 PCI Host Controller 21.1 Outline Control Register Base Address:0x Initiator Memory Base Address:0x Bridge Control Register Block The bridge control register block consists of the 64-byte PCI configuration space register block and a bridge control registers. The registers form a single block which is accessible both from the PCI bus and the host processor bus. In the PCI space the block is mapped in the configuration space. In the host bus the block is mapped as a memory block. The host bus interface implementation depends on the host bus type.

159 21 PCI Host Controller offset x00 Device ID Vendor ID 0x04 Status Register Command Register 0x08 Class Code Revision ID 0x0C BIST Header Type Latency Timer Cache Line Size 0x10 Base Address Register 0 0x14 Base Address Register 1 0x18 Base Address Register 2 0x1C Base Address Register 3 0x20 Base Address Register 4 0x24 Base Address Register 5 0x28 Card Bus CIS Pointer 0x2C Subsytem ID Subsystem Vendor ID 0x30 Expansion ROM Base Address Register 0x34 Reserved 0x38 Reserved 0x3C Maximum Latency Minimum Grant Intterupt Pin Interrupt Line 0x40 Bridge ID Register 0x44 Bridge Status Register Bridge Control Register 0x48 PCI Address Pointer PCI Transfer Counter 0x4C PCI Address Pointer 0x50 PCI Transfer Counter 0x54 Reserved Reserved Reserved PCI Command Register 0x58 Initiator Dual-port Memory Data Pointer PCI Configuration Space Vendor ID This is a 16-bit read-only register that identifies the manufacturer of the device. The value of this register is assigned by the PCI SIG. Device ID This is a 16-bit read-only register that identifies the device type. Command Register This is a 16-bit read/write register that provides basic control of the PCI function to respond to the PCI bus and/or access it. See Table 2-3 for a detailed description. Status Register This is a 16-bit register that provides the status of bus-related events. Read transactions from the status register behave normally. However, write transactions are different from typical write transactions because bits in the status register can be cleared but not set. A bit in the status register is cleared by writing a logic one to that bit. For a detailed description see Table 2-4. Revision ID Register This is an 8-bit read-only register that identifies the revision number of the device. The value of this register is assigned by the manufacturer (designer). Revision ID is defined in the pci hb params by the constant REV ID. Class Code Register This is a 24-bit read-only register divided into three sub-registers: base class, sub- class, and programming interface. Class code is defined in the pci hb params by the constant CLASS ID. Cache Line Size Register This specifies the system cache line size in DWORDS. This read/write register is initialized by system software at power-up. Latency Timer Register This is an 8-bit register. The register defines the maximum amount of time, in PCI bus clock cycles, that the PCI function can retain ownership of the PCI bus. Header Type Register This is an 8-bit read-only register that identifies the PCI function as a single- function device. The PCI-HB Core supports only header type 00. Base Address Registers - The PCI function supports up to six BARs. Each base address register (BARn) has identical attributes. The BAR is formatted per the PCI Local Bus Specification, Revision 2.2. Bit 0 of each BAR is read only and it is used to indicate whether the reserved address space is memory or I/O. BARs that map to 158

160 21.2. Bridge Control Register Block memory space must hardwire bit 0 to 0, and BARs that map to I/O space must hardwire bit 0 to 1. The format of the BAR changes depending on the value of bit 0. Interrupt Line Register This is an 8-bit register that defines to which system interrupt request line the INTA# output is routed. The Interrupt Line Register value is defined in the pci hb params by the constant INT LINE. The Host Bridge does not use the PCI interrupt line, thus the value is set to zero. Interrupt Pin Register This is an 8-bit read-only register that defines the PCI function PCI bus interrupt request line to be INTAn. The Interrupt Pin Register value is defined in the pci hb params by the constant INT PIN. Minimum Grant Register This is an 8-bit read-only register that defines the length of time the function would like to retain mastership of the PCI bus. The value set in this register indicates the required burst period length in 250-ns increments. The minimum Grant value is defined in the pci hb params by the constant MIN GNT. Maximum Latency Register This is an 8-bit read-only register that defines the frequency in which the function would like to gain access to the PCI bus. Maximum Latency value is defined in the pci hb params by the constant MAX LAT. Command Register offset: 0x04 Field Name Range Description IO EN 0 I/O access enable. Controls a device s response to I/O accesses. When high, it lets the device respond to the PCI bus I/O accesses as a target. MEM EN 1 Memory access enable. Controls a device s response to Memory space accesses. When high, it lets the device respond to the PCI bus memory accesses as a target. MASTER EN 2 Master enable SPEC CYC 3 Special Cycle Enable. Controls a device s action on the Special Cycle operation. The current version of the PCI Interface Core doesn t support this feature, however it is possible to add Special Cycle support by the user. MWI EN 4 Memory write and invalidate enable. VGA PS 5 VGA Palette Snoop. Currently unused. PERR EN 6 Parity error enable. When high, it enables the function to report parity errors via the PERR# output. STEP EN 7 Stepping Enable. The current version of the PCI Core doesn t support address/data stepping. STERR EN 8 System error enable. When high, it allows the function to report address parity errors via the SERR# output. 159

161 21 PCI Host Controller Status Register offset: 0x06 Field Name Range Description 3:0 Reserved. CAP EN 4 Read Capabilities list enable. When set, this bit enables the capabilities list pointer register at offset 34h. PCI 66M 5 Read PCI 66-MHz capable. When set, it indicates that the PCI device is capable of running at 66 MHz. 7:6 Reserved. MDPERR DET 8 Master Data Parity Error. When high, it indicates that during a read transaction the function asserted the PERRn output as a master device, or that during a write transaction the PERRn output was asserted as a target device. DEVSEL TIM 10:9 Device select timing. The devsel tim bits indicate target access timing of the function via the DEVSELn output. The PCI-HB Core is designed to be medium speed target device ( 01 b) TABORT SIG 11 Signaled target abort. This bit is set when a local peripheral device terminates a transaction. Currently not used. TABORT DET 12 Detected Target Abort. When high, it indicates that the function in master mode has detected a target abort from the current target device MABORT SIG 13 Master abort. When high, MABORT SIG indicates that the function in master mode has terminated the current transaction with a master abort. SERR SIG 14 Signaled system error. When high, SERR SIG indicates that the function drove the SERR# output active, i.e., an address phase parity error has occurred. The function signals a system error only if an address phase parity error was detected and SERR EN was set. PERR DET 15 Detected parity error. When high, PERR DET indicates that the function detected either an address or data parity error. Even if parity error reporting is disabled (via perr ena), the function sets the PERR DET bit Bridge ID Register (0x40) Bridge ID register uniquely identifies type of the bridge. The ID has encoded the host bus type and core revision. 160

162 21.2. Bridge Control Register Block Bridge ID Register offset: 0x40 Field Name Range Description version 7:0 PCI-Host bridge version subtype 11:8 Bridge subtype type 15:12 Bridge type. This defines a bridge type 0 generic bridge 1 PCI-AMBA bridge 2 PCI-CoreConnect bridge 3 PCI-OCP bridge Bridge Control Register (0x44) Bridge Control Register offset: 0x44 Field Name Range Description genpcirst 0 PCI reset. This bit generates a PCI bus reset. initena 1 Enable initiator transfer Bridge status register (0x46) offset: Field Name Range Description pciready 0 PCI ready. This bit indicates that a PCI bus reset was completed. The bit is clear when the PCI bus reset is in progress. reserved 4:1 ptxdone 5 PCI transfer done. ptxrerr 6 PCI transfer error Interrupt Status Register (0x4A) 161

163 21 PCI Host Controller Interrupt Status Register offset: 0x4A Field Name Range Description serrsts 0 SERR status. This bit indicates that a system error was reported on the PCI bus. The bit is set by SERR# line assertion. The bit is cleared by writing a 1 value to this bit. intasts 1 INTA# status. This bit indicates an interrupt request on INTA# interrupt line. The bit is equal to 1 when the line is asserted. intbsts 2 INTB# status. This bit indicates an interrupt request on INTB# interrupt line. The bit is equal to 1 when the line is asserted. intcsts 3 INTC# status. This bit indicates an interrupt request on INTC# interrupt line. The bit is equal to 1 when the line is asserted. intdsts 4 INTD# status. This bit indicates an interrupt request on INTD# interrupt line. The bit is equal to 1 when the line is asserted Interrupt Mask Register (0x48) Interrupt Mask Register offset: 0x48 Field Name Range Description serrimask 0 System error interrupt mask. intaimask 1 INTA# interrupt mask. intbimask 2 INTB# interrupt mask. intcimask 3 INTC# interrupt mask. intdimask 4 INTD# interrupt mask. txtimask 5 PCI transfer finished interrupt mask. txterrimask 6 PCI transfer error interrupt mask PCI Address Pointer (0x4C) The contents of the PCI address pointer register depends on a PCI transaction type. There are four basic types of PCI transaction: Memory space access transaction is used for accessing PCI memory space Address

164 21.2. Bridge Control Register Block I/O space access transaction is used for accessing PCI I/O space. The address bits [1:0] must be consistent with byte enables in PCI Command register. For more details about the valid address bit encoding see the Table Address AD[1:0] Stating byte Valid BE#[e:0] 00 Byte 0 xxx0 or Byte 1 xx01 or Byte 2 x011 or Byte or 1111 Configuration space access type 01 transaction is used to access devices that reside on another bus (behind a PCI-to-PCI bridge). A PCI-to-PCI bridge translates the access type 01 to access type 00 on the target bus. The format of the PCI address register for the configuration space access type 01 is described in Figure 2-9 and Table The PCI-Host bridge core sends the address register unchanged to the PCI bus. Field Name Range Description 01 1:0 Type 01 identifier Register number 7:0 This is an encoded value to select a DWORD in the configuration space of a target device. Function number 10:8 This is a function number used to select a configuration space within a multifunction device. Device number 15:11 This is a device number used to select a device on a given bus Bus number 23:16 This is a bus number where the device has to be accessed. Configuration space access type 00 transaction is used to select a device on the bus where the transaction is being run. The format of the PCI address register for the configuration space access type 00 is described in Figure 2-10 and Table The PCI-Host bridge core converts the address register contents to the PCI bus address as shown in Figure The AD[31:11] lines can be used as an IDSEL signal for PCI devices or slots. The bridge is using the AD[31:16] address lines for the IDSEL encoding. Field Name Range Description 00 1:0 Type 00 identifier Register number 7:0 This is an encoded value to select a DWORD in the configuration space of a target device. Function number 10:8 This is a function number used to select a configuration space within a multifunction device. Device number 15:11 This is a device number used to select a device on a given bus 163

165 21 PCI Host Controller PCI Transfer Counter (0x50) The PCI transfer counter register defines a number of data transfers to be completed. The number is DWORD aligned however a number of bytes can be reduced by byte enables in the PCI command register. The maximum number of data to be transferred is limited by the size of the dual-port memory Count PCI Command Register (0x54) The PCI command register defines a transaction command and a byte enable for the transaction reserved cmd 3 0 ben C/BE#[3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Access Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Initiator Dual-port Memory Data Pointer (0x58) 31 2 data pointer

166 On-Chip Emulator 22.1 Outline On-Chip Emulator SPI 22.2 Operation On-Chip Emulator SPI 1bit General Purpose I/O RELOAD SPI 1( ) MSB RELOAD Single Write SPI 8bit 0xAB RELOAD 0 MSB 8bit RELOAD 0 4 MSB 8bit RELOAD 0 4 On-Chip Emulator Single Read SPI 8bit 0xAA RELOAD 0 MSB 8bit RELOAD 0 4 On-Chip Emulator MISO I/O 0 1 RELOAD 0 MISO I/O MSB 8bit 4

167

168 Responsive Link 23.1 Responsive Link Responsive Link Hot-Plug&Play Responsive Link (IPSJ-TS 2003:0006) ISO/IEC JTC1 SC25 WG4

169 23 Responsive Link Responsive Link point-to-point 23.1 Responsive Link Connector Responsive Link Cable Responsive Link Connector (RJ-45) (Enhanced Category 5) (RJ-45) 1 2 Tx Data+ Tx Data- Data Link Tx Data+ Tx Data Rx Data+ Rx Data- Rx Data+ Rx Data Tx Event+ Tx Event- Event Link Tx Event+ Tx Event Rx Event+ Rx Event- Rx Event+ Rx Event : Responsive Link 168

170 Responsive Link Data Packet Format (64B) Event Packet Format (16B) Source Addr. Destination Addr. Source Addr. Destination Addr. Payload Control & Status Payload Control & Status 1 byte Control & Status Format (32bits) 1 bit Full Data Length Dirty0 Dirty1 Dirty2 Dirty3 Dirty4 Dirty5 Dirty6 Dirty7 Dirty8 Dirty9 Dirty10 Dirty11 Dirty12 Dirty13 Dirty14 Dirty15 3 Start End Int. Fatal Correct Serial Number (Cnt.) Frame Format (12bits) Data bits Redundancy bits 23.2: Responsive Link 169

171 23 Responsive Link (8bit) 0 Priority[7-4] Source Address Priority[3-0] Destination Address : Responsive Link Responsive Link 2 32 ( 23.3 ) Responsive Link 12bit 12bit 8bit 2 12 = bit 8bit 2 24 = 16M B (64byte) 2byte 2byte 56byte 4byte 64byte 4byte UD Full 56byte 1 0 Data Length Dirty byte 2 Dirty1 1 Start 1 0 End 1 0 Int 1 0 Fatal Correct Serial Number B (16byte) 170

172 byte UD Full 8byte 1 0 Data Length Dirty Dirty1 1 Start 1 0 End 1 0 Int 1 0 Fatal Correct Serial Number RMTP Responsive Link (In0 4) (Out0 4) bit byte 8 (DDR SDRAM) (In) (In-Pointer) (L0 L4) L

173 23 Responsive Link 8bit In0 Fifo00 Fifo01 Fifo02 Fifo03 In1 Fifo10 Fifo11 Fifo12 Fifo13 In2 Fifo20 Fifo21 Fifo22 Fifo23 In3 Fifo30 Fifo31 Fifo32 Fifo33 In4 Fifo40 Fifo41 Fifo42 Fifo43 32bit SDRAM Arbitor SDRAM I/F Table Arbitor Routing Table Priority Arbitor0 MUX0 Priority Arbitor1 MUX1 Priority Arbitor2 MUX2 Priority Arbitor3 MUX3 Priority Arbitor4 MUX4 SDRAM MPU Out0 Out1 Out2 Out3 Out4 23.4: Responsive Link 23.5: Responsive Link 23.5 L0 L4 (Out0 Out4) ( 23.4 Priority ArbitorN) 23.5 PriorityN 23.4 Priority ArbitorN 172

174 23.4. In-pointer 1 In 1 L1 L3 Out-pointer1 Out-pointer3 1 Out1 Out3 Priority1 Priority3 Out3 Priority Arbitor3 1 Out3 Out3 1 L3 Out1 Priorty1 Out1 Out1 2 Out-pointer1 2 Priority1 Out1 Out-pointer (DDR SDRAM) 2 Responsive Link byte 23.2 Frame Format Data bits 8bit Redundancy bits byte Redudancy bits CRC byte 23.5 Responsive Link 23.6 Responsive Link 173

175 23 Responsive Link 23.6 Reference Referent EE DE L[4-0] Responsive Link TLB MMU Responsive Link RT-OS Responsive Link LRU RT-OS Priority[7-4] Source Address (16bit) Priority[3-0] Destination Address (16bit) EE DE P7 P6 P5 P4 P3 P2 P1 P0 PE L4 L3 L2 L1 L0 EE DE P7 P6 P5 P4 P3 P2 P1 P0 PE L4 L3 L2 L1 L0 EE DE P7 P6 P5 P4 P3 P2 P1 P0 PE L4 L3 L2 L1 L0 EE DE P7 P6 P5 P4 P3 P2 P1 P0 PE L4 L3 L2 L1 L0 Reference Referent Priority[7-0] : Priority EE : Event Enable DE : Data Enable PE : Priority exchange Enable P[7-0] : New Priority L[4-0] : Output Port Number 23.6: Responsive Link PE 174

176 23.7. PE (Priority[7-0]) (P7 P0) Responsive Link 175

177 23 Responsive Link Source Data (Priority0) Data (Priority1) Event (Priority3) Destination Event (Priority0) 23.7: Responsive Link

178 23.8. Data (Priority1) Source Node0 Data (Priority0) Node1 Node2 Node3 Node4 Node5 Node6 Node7 Node8 Node9 Node10 Destination 23.8: Responsive Link 23.8 Responsive Link CRC (8bit +4bit ) 1bit CODEC Responsive Link CODEC 8bit 4bit 12bit 1 CODEC Bit Stuffing NRZI 177

179 23 Responsive Link x 4 + x + 1 8bit (LSB) 4bit 12bit 1bit bit MSB 1bit 23.1: Syndrome Error Position (4 Meaning redundancy bits) No error Redundancy-bit error Redundancy-bit error Redundancy-bit error Redundancy-bit error bit error bit error bit error bit error bit error bit error bit error bit error Bit Stuffing NRZI NRZI(Non Return to Zero Inverted) NRZI bit stuffing 1 178

180 : Speed (Mbaud) Maximum Length (m) Recommendable Cable Cat5e Cat5e Cat DPLL DPLL(Digital Phase Lock Loop) 1bit (4,8,16,32,64,128,256) DPLL 23.2 DPLL p mode2 p mode1 p mode0 d clk /1bit Mode Mode Mode Mode Mode : DPLL Responsive Link 1[bit/frame] 23.2 Dirty (4byte) Dirty Dirty 1 Correct Fatal Responsive Link 400, 200, 100, 50, 12.5, 6.25 [Mbaud] [Mbaud] Category6 60[m] DPLL [MHz] 4 DPLL DPLL 179

181 23 Responsive Link DPLL I/O 0x8000 xxxx 0x90xx xxxx 0x94xx xxxx 0x98xx xxxx 0x9Cxx xxxx 0xA000 0xxx 0xA000 1xxx 0xA000 2xxx 0xA000 3xxx 0xA800 xxxx Link SDRAM DPM (r) DPM (r/w) DPM (r) DPM (r/w) IRC (r/w) (r/w) (r/w) Link SDRAM : 0xA SDRAM : 0x h0 SDMODE Responsive Link SDRAM SDMODE(SDram MODE) DDR SDRAM SDRAM 8 bit 29 h0 0 SDMODE Default : SDRAM 001 : SDRAM 8MB 010 : SDRAM 16MB 011 : SDRAM 32MB 100 : SDRAM 64MB 101 : SDRAM 128MB 110 : SDRAM 256MB 111 : SDRAM 512MB 180

182 : 0xA Data Data Data Data Event4 8 6 Event3 5 3 Event2 2 0 Event1 RSL(Responsive Link Speed): Default : 800 Mbaud 000 : 400 Mbaud 001 : 200 Mbaud 010 : 100 Mbaud 011 : 50 Mbaud bit Data4 Data3 Data2 Data1 Event4 Event3 Event2 Event1 Data Link 4 RSL Data Link 3 RSL Data Link 2 RSL Data Link 1 RSL Event Link 4 RSL Event Link 3 RSL Event Link 2 RSL Event Link 1 RSL : 0xA EDINIT EMI EEINIT 16 E s DDINIT 8 DMI DEINIT 0 D s RLINIT(Responsive Link INITialization) 0: 1: 181

183 23 Responsive Link bit EDINIT EMI ELINIT E s DDINIT DMI DEINIT D s Event Link EDINIT[4]: RLINIT[28]: Event link4 EDINIT[3]: RLINIT[27]: Event link3 EDINIT[2]: RLINIT[26]: Event link2 EDINIT[1]: RLINIT[25]: Event link1 Event Link Event link EEINIT[4]: RLINIT[20]: Event link4 EEINIT[3]: RLINIT[19]: Event link3 EEINIT[2]: RLINIT[18]: Event link2 EEINIT[1]: RLINIT[17]: Event link1 Event link switch Data link DDINIT[4]: RLINIT[12]: Data link4 DDINIT[3]: RLINIT[11]: Data link3 DDINIT[2]: RLINIT[10]: Data link2 DDINIT[1]: RLINIT[9]: Data link1 Data Link Data link DEINIT[4]: RLINIT[4]: Data link4 DEINIT[3]: RLINIT[3]: Data link3 DEINIT[2]: RLINIT[2]: Data link2 DEINIT[1]: RLINIT[1]: Data link1 Data link switch : 0xA C RLIC 0 - Responsive Link IRQ1-6 RLIC(Responsive Link Irq Clear) Default 0 0: 1: 182

184 bit RLIC[1] RLIC[2] RLIC[3] RLIC[4] RLIC[5] RLIC[6] Data-Out EOP(End Of Packet) IRQ Clear: DPM Event-Out EOP IRQ Clear: DPM Data-In EOP IRQ Clear: DPM Event-In EOP IRQ Clear: DPM Data Packet-In IRQ Clear: Event Packet-In IRQ Clear: : 0xA C Event Data Responsive Link IRQ1-6 Default 0 0: 1: bit Event Data Event Link Event[4]: Event link4 Event[3]: Event[2]: Event[1]: Event[0]: Event link3 Event link2 Event link1 Event link0 Data Link Data[4]: Data link4 Data[3]: Data[2]: Data[1]: Data[0]: Data link3 Data link2 Data link1 Data link0 183

185 23 Responsive Link : 0xA DWIRQC EWIRQC Responsive Link SDRAM SDRAM SDRAM WIRQC(Wait IRQ Clear) Default 0 0: 1: bit DWIRQC EWIRQC Data link WIRQC DWIRQC[4]: WIRQC[20]: Data link4 DWIRQC[3]: WIRQC[19]: Data link3 DWIRQC[2]: WIRQC[18]: Data link2 DWIRQC[1]: WIRQC[17]: Data link1 DWIRQC[0]: WIRQC[16]: Data link0(cpu) Event link WIRQC EWIRQC[4]: WIRQC[4]: Event link4 EWIRQC[3]: WIRQC[3]: Event link3 EWIRQC[2]: WIRQC[2]: Event link2 EWIRQC[1]: WIRQC[1]: Event link1 EWIRQC[0]: WIRQC[0]: Event link0(cpu) : 0xA DCIC ECIC Responsive Link SDRAM CI(Coutinuous Irq) CIC(Continuous Irq Clear) CI Default 0 0: 1: 184

186 bit DCIC ECIC Data CIC DCIC[4]: CIC[20]: Data link4 DCIC[3]: CIC[19]: Data link3 DCIC[2]: CIC[18]: Data link2 DCIC[1]: CIC[17]: Data link1 DCIC[0]: CIC[16]: Data link0(cpu) Event CIC ECIC[4]: CIC[4]: Event link4 ECIC[3]: CIC[3]: Event link3 ECIC[2]: CIC[2]: Event link2 ECIC[1]: CIC[1]: Event link1 ECIC[0]: CIC[0]: Event link0(cpu) : 0xA DFIC EFIC Responisve Link FI(Fatal Irq) FIC(Fatal Irq Clear) FI Default 0 0: 1: bit DFIC Data FIC DFIC[4]: FIC[20]: Data link4 DFIC[3]: FIC[19]: Data link3 DFIC[2]: FIC[18]: Data link2 DFIC[1]: FIC[17]: Data link1 DFIC[0]: FIC[16]: Data link0(cpu) EFIC Event FIC EFIC[4]: FIC[4]: Event link4 EFIC[3]: FIC[3]: Event link3 EFIC[2]: FIC[2]: Event link2 EFIC[1]: FIC[1]: Event link1 EFIC[0]: FIC[0]: Event link0(cpu) 185

187 23 Responsive Link : 0xA C RTIRQC Responsive Link (RTIRQ) RTIRQC(Routing Table IRQ Clear) RTIRQ Default 0 0: (r) (w) 1: (r) (w) bit RTIC[0] RTIC[1] Event Routing Table IRQ Clear Data Routing Table IRQ Clear SDRAM : 0xA RLSDBREQ Responsive Link SDRAM Responsive Link 2 SDRAM SDRAM SDRAM DMAC Responsive Link SDRAM ( ) bit RLSDBREQ RLSDBREQ (Responsive Link SDram-Bus REQuest) : Default 1 SDRAM 0: 1: SDRAM : 0xA MSG - DSG ESG RLSDBGRNT(Responsive Link SDram Bus GRaNT) SDRAM 186

188 : 1: bit MSG DSG Mpu Sdram bus Grant: MPU Data link Sdram bus Grant: Data Link DSG[4]: RLSDBGRNT[20]: Data link4 DSG[3]: RLSDBGRNT[19]: Data link3 DSG[2]: RLSDBGRNT[18]: Data link2 DSG[1]: RLSDBGRNT[17]: Data link1 DSG[0]: RLSDBGRNT[16]: Data link0(cpu) ES Event link Sdram bus Grant: Event Link ESG[4]: RLSDBGRNT[4]: Event link4 ESG[3]: RLSDBGRNT[3]: Event link3 ESG[2]: RLSDBGRNT[2]: Event link2 ESG[1]: RLSDBGRNT[1]: Event link1 ESG[0]: RLSDBGRNT[0]: Event link0(cpu) : 0xA BRQ Responsive Link Responsive Link 2 Responsive Link DMAC Responsive Link bit BRQ RLTBLBREQ (Responsive Link rouging TaBLe Bus REQuest): Default 1 0: 1: : 0xA MRR DRR ERR 0: 1: 187

189 23 Responsive Link bit MRR DRR ER Mpu Routing table bus Request Data link Routing table bus Request DRR[4]: RLTBLBREQ[20]: Data link4 DRR[3]: RLTBLBREQ[19]: Data link3 DRR[2]: RLTBLBREQ[18]: Data link2 DRR[1]: RLTBLBREQ[17]: Data link1 DRR[0]: RLTBLBREQ[16]: Data link0(cpu) Event link Routing table bus Request ERR[4]: RLTBLBREQ[4]: Event link4 ERR[3]: RLTBLBREQ[3]: Event link3 ERR[2]: RLTBLBREQ[2]: Event link2 ERR[1]: RLTBLBREQ[1]: Event link1 ERR[0]: RLTBLBREQ[0]: Event link0(cpu) : 0xA C MRG DRG ERG RLTBLBGRNT (Responsive Link routing TaBLe Bus GRaNT) 0: 1: bit MRG DRG Mpu Routing table bus Grant: MPU Data link Routing table bus Grant: Data Link DRG[4]: RLTBLBGRNT[20]: Data link4 DRG[3]: RLTBLBGRNT[19]: Data link3 DRG[2]: RLTBLBGRNT[18]: Data link2 DRG[1]: RLTBLBGRNT[17]: Data link1 DRG[0]: RLTBLBGRNT[16]: Data link0(cpu) ERG Event link Routing table bus Grant: Event Link ERG[4]: RLTBLBGRNT[4]: Event link4 ERG[3]: RLTBLBGRNT[3]: Event link3 ERG[2]: RLTBLBGRNT[2]: Event link2 ERG[1]: RLTBLBGRNT[1]: Event link1 ERG[0]: RLTBLBGRNT[0]: Event link0(cpu) 188

190 LRU : 0xA ELLRUA bit ELLRUA ELLRUA (Event Link LRU Address) LRU : 0xA DLLRUA bit DLLRUA DLLRUA (Data Link LRU Address) : 0xA RLICE bit RLICE RLICE (Responsive Link Interrupt Controller Enable) RLIRC 1 RLIRC SDRAM : 0xA ELSDCNT SDRAM Responsive Link 189

191 23 Responsive Link bit ELSDCNT ELSDCNT (Event Link SDram loop CouNTer) SDRAM 1 (1-40) Default: SDRAM : 0xA DLSDCNT SDRAM Responsive Link bit DLSDCNT DLSDCNT (Data Link SDram loop CouNTer) SDRAM 1 (1-95) Default: : 0xA RLSM RLSM(Responsive Link Switch Mode) 0: Cut Through Mode 1: Store and Forward Mode Default: 0 bit RLSM[0] RSLM[1] Event Link Switch Data Link Switch : 0xA c DRLOL ERLOL Responsive Link Plug&Play 190

192 RLOL(Responsive Link OffLine) 1: Offline 0: Online bit DRLOL Data link RLOL DRLOL[4]: RLOL[20]: Data link4 DRLOL[3]: RLOL[19]: Data link3 DRLOL[2]: RLOL[18]: Data link2 DRLOL[1]: RLOL[17]: Data link1 DRLOL[0]: RLOL[16]: Data link0(cpu) ERLOL Event link RLOL ERLOL[4]: RLOL[4]: Event link4 ERLOL[3]: RLOL[3]: Event link3 ERLOL[2]: RLOL[2]: Event link2 ERLOL[1]: RLOL[1]: Event link1 ERLOL[0]: RLOL[0]: Event link0(cpu) : 0xA c RLOL 1: 0: bit RLOL[0] RLOL[1] Responsive Link Down IRQ Clear: Responsive Link Wakeup IRQ Clear: : 0xA Port 0 - Responsive Link 1: 0: 191

193 23 Responsive Link bit Port Responsive Link Port[3]: 4 Port[2]: 3 Port[1]: 2 Port[0]: : Event Link : 0xA : Data Link : 0xA Header Value Routing Table : Event Link : 0xA C Err Header Ptr Default : Event Link : 0xA Err Header Mode E : Data Link : 0xA Err Header Mode D SDRAM : Event Link : 0xA

194 DPM (Dual Port Memory) sdram restore en : Event Link : 0xA c : Data Link : 0xA CH4 CH3 CH2 7 0 CH1 Responsive Link RS - ECC - Line Code bit CH*[7] CH*[5:4] CH*[2:0] Reed Solomon ECC 00: ECC 01: Hamming 10: BCH 001: NRZI+BitStuffing 010: 8B10B 100: 4B10B DPM (Dual Port Memory) Responsive Link DPM DPM 2port Responsive Link Link0 Data in/out control register Event in/out control register / Event packet in/out DPM Data packet in/out DPM Event in/out Data in/out DPM Event Output 23.9 DPM Event out control register From Addr (byte address word address) To Addr (word address) From Addr To Addr From Addr, To Addr 193

195 23 Responsive Link word address 1 DPM DPM Link0 Mode0 From Addr 0x00 To Addr 0x07 (byte address: 0x1c) DMAC Payload0, Payload1 DPM DPM 0x06 DPM Responsive Link Link0 From Addr Mode0 From Addr 0x1f(byte address 0x3c) To Addr 0x2f(byte address: 0x7c) DMAC continuous mode Payload0 3 Payload4 7 DPM DPM CS DPM 194

196 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 offset address 0xC400_00XX Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Mode0 Payload 0 Control & Status Payload 1 Control & Status Payload 2 Control & Status Payload 3 Control & Status Payload 4 Control & Status Payload 5 Control & Status Payload 6 Control & Status Payload 7 Control & Status DPM for Event Output Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Source Addr DPM (Dual Port Memory) Mode1 Payload 0 Payload 1 Payload 2 Payload 3 Payload 4 Payload 5 Payload 6 Payload 7 Payload 8 Payload 9 Payload 10 Payload 11 Payload 12 Payload 13 Payload 14 Control & Status Destination Addr. 23.9: DPM for Event Output 195

197 23 Responsive Link offset address 0xFFFE_F40X Control Register for Event Output 0x0 0x4 0x8 From Addr. To Addr. DMA Counter Current Packet Number mode dreq int 23.10: Event Out Control Register DPM DPM (r/w) Mode0: mode bit 0 headr trailer Mode1: mode bit 1 header trailer ( ) Int: 1 EOP(End Of Packet) Dreq: 1 DMA Counter DMA From Addr: word address 1 DPM DPM Link0 To Addr: word address 1 DPM DPM Link0 DMA Counter (r/w) DMA Current Packet Number (r) 23.9 payload Event Input DPM Event in control register From Addr (byte address word address) To Addr (word address) From Addr To Addr From Addr, To Addr word address 1 DPM Responsive Link DPM (DMA ) (dreq bit int bit Mode0 From Addr 0x00 To Addr 0x07 (byte address: 0x1c) Responsive Link Payload0, Payload1 DPM Responsive Link DPM 196

198 DPM (Dual Port Memory) 0x06 DPM DMA From Addr Mode0 From Addr 0x1f(byte address 0x3c) To Addr 0x2f(byte address: 0x7c) DMAC continuous mode Payload0 3 Payload4 7 DPM DPM CS DPM 197

199 23 Responsive Link 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 offset address 0xC000_00XX Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Mode0 Payload 0 Control & Status Payload 1 Control & Status Payload 2 Control & Status Payload 3 Control & Status Payload 4 Control & Status Payload 5 Control & Status Payload 6 Control & Status Payload 7 Control & Status DPM for Event Input Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Source Addr. Mode1 Payload 0 Payload 1 Payload 2 Payload 3 Payload 4 Payload 5 Payload 6 Payload 7 Control & Status Control & Status Control & Status Control & Status Control & Status Control & Status Control & Status Control & Status Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr. Destination Addr : DPM for Event Input 198

200 DPM (Dual Port Memory) offset address 0xFFFE_F00X 0x0 0x4 0x8 0xC Control Registers for Event Input From Addr. To Addr. Current Packet Number Packet Valid Status mode dreq int 23.12: Event in control register DPM DPM (r/w) Mode0: mode bit 0 header trailer DPM Mode1: mode bit Int: 1 Dreq: 1 From Addr To Addr word address 1 DMA DREQ From Addr: word address 1 DPM Responsive Link DPM To Addr: word address 1 DPM Responsive Link DPM Current Packet Number (r) payload Packet Valid Status Data Output DPM Data out control register From Addr (byte address word address) To Addr (word address) From Addr To Addr From Addr, To Addr word address 1 DPM DPM Link0 Mode0 From Addr 0x000 To Addr 0x01f (byte address: 0x07c) DMAC Payload0, Payload1 DPM 199

201 23 Responsive Link DPM word address 0x01e DPM Responsive Link Link0 From Addr Mode0 From Addr 0x0ff(byte address 0x3fc) To Addr 0x1ff(byte address: 0x7fc) DMAC continuous mode Payload0 15 Payload16 31 DPM DPM CS DPM offset address 0xCC00_0XXX Mode0 DPM for Data Output Mode1 0x000 Source Addr. Destination Addr. Payload 0 Control & Status 0x000 0x038 Payload 0 Payload 1 0x040 Source Addr. Destination Addr. Payload 1 0x070 Payload 2 Control & Status 0x080 Source Addr. Destination Addr. Payload 2 Control & Status 0x0C0 0x780 0x7C0 Source Addr. Destination Addr. Payload 30 Control & Status Source Addr. Destination Addr. 0x770 0x7A8 0x7E0 Payload 34 Payload 35 Payload 31 0x7F8 Source Addr. Destination Addr. Control & Status 0x7FC Control & Status 23.13: DPM for Data Output 200

202 DPM (Dual Port Memory) offset address 0xFFFE_FC0X Control Register for Data Output 0x0 0x4 0x8 From Addr. To Addr. DMA Counter Current Packet Number mode dreq int 23.14: Data Out Control Register DPM DPM (r/w) Mode0: (r/w) mode bit 0 headr trailer Mode1: (r/w) mode bit 1 header trailer ( ) Int: (r/w) 1 EOP(End Of Packet) Dreq: (r/w) 1 DMA Counter DMA From Addr: (r/w) word address 1 DPM DPM Link0 To Addr: (r/w) word address 1 DPM DPM Link0 DMA Counter (r/w) DMA Current Packet Number (r) payload Data Input DPM Data in control register From Addr (byte address word address) To Addr (word address) From Addr To Addr From Addr, To Addr word address 1 DPM Responsive Link DPM (DMA ) (dreq bit int bit Mode0 From Addr 0x000 To Addr 0x01f (byte address: 0x07c) Responsive Link Payload0, Payload1,... DPM Responsive Link 201

203 23 Responsive Link DPM word address 0x1e DPM DMA From Addr Mode0 From Addr 0x0ff(byte address 0x3fc) To Addr 0x1ff(byte address: 0x7fc) DMAC continuous mode Payload0 15 Payload16 31 DPM DPM CS DPM offset address 0xC800_0XXX Mode0 DPM for Data Input Mode1 0x000 Source Addr. Destination Addr. Payload 0 Control & Status 0x000 0x038 Payload 0 Payload 1 0x040 Source Addr. Destination Addr. Payload 1 0x070 0x0A8 Payload 2 Control & Status 0x080 Source Addr. Destination Addr. Payload 2 Control & Status 0x0C0 0x070 Payload 31 0x700 Source Addr. Destination Addr. Control & Status 0 0x780 Source Addr. Destination Addr. 0x708 Source Addr. Destination Addr. Payload 30 Control & Status 1 Control & Status 0x7C0 Source Addr. Destination Addr. Payload 31 0x7F8 Source Addr. Destination Addr. Control & Status 0x7FC Control & Status : DPM for Data Input 202

204 offset address 0xFFFE_F80X 0x0 0x4 0x8 0xC Control Registers for Data Input From Addr. To Addr. Current Packet Number Packet Valid Status mode dreq int 23.16: Data In Control Register DPM DPM (r/w) Mode0: mode bit 0 header trailer DPM Mode1: mode bit Int: 1 Dreq: 1 From Addr To Addr word address 1 DMA DREQ Current Packet Number (r) payload Packet Valid Status Responsive Link 2. Responsive Link 3. Responsive Link Responsive Link 6. DPM Event in/out control Data in/out control 7. DPM 203

205 23 Responsive Link DMA DPM DMA DPM DPM N packet DPM 1. N f f<36 f DPM DMA Counter (N/f)-1 3. DPM MODE1 HEADER MODE1 TRAILER ( ) 4. DPM mode 1,from(0),to(f*0xe+0xd),DREQ (mode 0 DMA ) DMA 1. DMA 2. DMA DPM 3. DMA DPM 4. DMA SAU, RL, MTM, ST ON ( ST DMA Counter 1 ) Responsive Link IRQ1 4 DPM from addr to addr IRQ1 6 (0xa c) Request Sense Register, Request Clear Register, Mask Register bit IRQ i bit IRQi : Responsive Link IRC: 0xa

206 Responsive Link offset x00 16 h0 IRQ15IRQ14IRQ13IRQ12IRQ11IRQ10 IRQ9 IRQ8 0x04 16 h0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 2 h0 0x08 16 h0 Request Sense Register 0 0x0c 16 h0 Request Clear Register 0 0x10 16 h0 Mask Register 0 0x14 26 h0 CL IRL Latch 0x18 31 h0 Mode 23.4: Responsive Link Offset Name 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 RL IRC TMR0 OFFSET RL IRC TMR1 OFFSET RL IRC RSR OFFSET RL IRC RCR OFFSET RL IRC MR OFFSET RL IRC ICR OFFSET RL IRC MOD OFFSET 205

207 23 Responsive Link 23.5: Responsive Link IRC IRQ Name IRQ31 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 Reserved RL DEC RESET IRC RL IRQ DOWN RL IRQ WAKEUP RL IRQ FATAL RL IRQ TABLE RL IRQ WAIT RL IRQ CONT RL IRQ EVP IN RL IRQ DAP IN RL IRQ EV INEOP RL IRQ DA INEOP RL IRQ EV OUTEOP RL IRQ DA OUTEOP 206

208 Responsive Link IRQ Name Description RL DEC RESET IRC - RL IRQ DOWN - RL IRQ WAKEUP - RL IRQ FATAL FI (Fatal IRQ) RL IRQ TABLE RTIRQ (Routing IRQ) RL IRQ WAIT WIRQ (Wait IRQ) SDRAM SDRAM RL IRQ CONT CI (Continuous SDRAM IRQ) RL IRQ EVP IN Event Packet-In IRQ event RL IRQ DAP IN Data Packet-In IRQ data RL IRQ EV INEOP Event-In End of Packet Event-In DPM RL IRQ DA INEOP Data-In End of Packet Data-In DPM RL IRQ EV OUTEOP Event-Out End of Event-Out DPM Packet RL IRQ DA OUTEOP Data-Out End of Data-Out DPM Packet 207

209

210 Revision Date Description Abstract Bus External Bus, Timer, UART, PIO, SPI, Responsive Link Responsive Link Responsive Link Responsive Link SDRAM UART Line Control Register